35 lines
843 B
VHDL
35 lines
843 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity ALU4 is
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port
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(
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a,b : in std_logic_vector(3 downto 0);
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op : in std_logic_vector(2 downto 0);
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r, m : out std_logic_vector(3 downto 0)
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);
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end ALU4;
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architecture Behavioral of ALU4 is
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signal s_a, s_b, s_r : unsigned(3 downto 0);
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signal s_m : unsigned(7 downto 0);
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begin
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s_a <= unsigned(a);
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s_b <= unsigned(b);
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s_m <= s_a * s_b;
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with op select
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s_r <= s_a + s_b when "000",
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s_a - s_b when "001",
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s_m(3 downto 0) when "010",
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s_a / s_b when "011",
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s_a rem s_b when "100",
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s_a and s_b when "101",
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s_a or s_b when "110",
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s_a xor s_b when "111";
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r <= std_logic_vector(s_r);
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m <= std_logic_vector(s_m(7 downto 4)) when (op = "010") else (others => '0');
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end Behavioral; |