65 lines
3.5 KiB
Plaintext
65 lines
3.5 KiB
Plaintext
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
|
# Your use of Intel Corporation's design tools, logic functions
|
|
# and other software and tools, and any partner logic
|
|
# functions, and any output files from any of the foregoing
|
|
# (including device programming or simulation files), and any
|
|
# associated documentation or information are expressly subject
|
|
# to the terms and conditions of the Intel Program License
|
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
# the Intel FPGA IP License Agreement, or other applicable license
|
|
# agreement, including, without limitation, that your use is for
|
|
# the sole purpose of programming logic devices manufactured by
|
|
# Intel and sold by Intel or its authorized distributors. Please
|
|
# refer to the applicable agreement for further details, at
|
|
# https://fpgasoftware.intel.com/eula.
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Quartus Prime
|
|
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
|
# Date created = 20:48:57 March 08, 2023
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
#
|
|
# Notes:
|
|
#
|
|
# 1) The default values for assignments are stored in the file:
|
|
# DisplayDemoVHDL_assignment_defaults.qdf
|
|
# If this file doesn't exist, see file:
|
|
# assignment_defaults.qdf
|
|
#
|
|
# 2) Altera recommends that you do not modify this file. This
|
|
# file is updated automatically by the Quartus Prime software
|
|
# and any changes you make may be lost or overwritten.
|
|
#
|
|
# -------------------------------------------------------------------------- #
|
|
|
|
|
|
set_global_assignment -name FAMILY "Cyclone IV E"
|
|
set_global_assignment -name DEVICE EP4CE115F29C7
|
|
set_global_assignment -name TOP_LEVEL_ENTITY Bin7SegDecoder
|
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
|
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:48:57 MARCH 08, 2023"
|
|
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
|
|
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
|
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
|
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
|
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
|
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
|
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
|
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
|
|
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
|
|
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
|
|
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
|
|
set_global_assignment -name VHDL_FILE Bin7SegDecoder.vhd
|
|
set_global_assignment -name VHDL_FILE DisplayDemoVHDL.vhd
|
|
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
|
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
|
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |