76 lines
7.2 KiB
Plaintext
76 lines
7.2 KiB
Plaintext
Determining the location of the ModelSim executable...
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Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/
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To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
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Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
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**** Generating the ModelSim Testbench ****
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quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/tiagorg/repos/DecoderDemo/Waveform1.vwf" --testbench_file="/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform1.vwf.vht"
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Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Mon Nov 14 21:42:30 2022Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source=/home/tiagorg/repos/DecoderDemo/Waveform1.vwf --testbench_file=/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform1.vwf.vhtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Completed successfully.
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**** Generating the functional simulation netlist ****
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quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/DecoderDemo/simulation/qsim/" DecoderDemo -c DecoderDemo
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Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Mon Nov 14 21:42:30 2022Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/DecoderDemo/simulation/qsim/ DecoderDemo -c DecoderDemoWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file DecoderDemo.vho in folder "/home/tiagorg/repos/DecoderDemo/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 603 megabytes Info: Processing ended: Mon Nov 14 21:42:31 2022 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00
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Completed successfully.
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**** Generating the ModelSim .do script ****
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/home/tiagorg/repos/DecoderDemo/simulation/qsim/DecoderDemo.do generated.
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Completed successfully.
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**** Running the ModelSim simulation ****
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/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do DecoderDemo.do
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Reading pref.tcl
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# 2020.1
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# do DecoderDemo.do
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# ** Warning: (vlib-34) Library already exists at "work".
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# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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# Start time: 21:42:31 on Nov 14,2022# vcom -work work DecoderDemo.vho
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package VITAL_Timing
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# -- Loading package VITAL_Primitives
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# -- Loading package cycloneive_atom_pack# -- Loading package cycloneive_components
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# -- Compiling entity hard_block
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# -- Compiling architecture structure of hard_block
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# -- Compiling entity Dec2_4
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# -- Compiling architecture structure of Dec2_4
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# End time: 21:42:31 on Nov 14,2022, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
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# Start time: 21:42:31 on Nov 14,2022# vcom -work work Waveform1.vwf.vht
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164# -- Compiling entity Dec2_4_vhd_vec_tst# -- Compiling architecture Dec2_4_arch of Dec2_4_vhd_vec_tst
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# End time: 21:42:31 on Nov 14,2022, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst # Start time: 21:42:31 on Nov 14,2022# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.dec2_4_vhd_vec_tst(dec2_4_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.dec2_4(structure)# Loading work.hard_block(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
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# after#33
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# End time: 21:42:31 on Nov 14,2022, Elapsed time: 0:00:00# Errors: 0, Warnings: 0
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Completed successfully.
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**** Converting ModelSim VCD to vector waveform ****
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Reading /home/tiagorg/repos/DecoderDemo/Waveform1.vwf...
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Reading /home/tiagorg/repos/DecoderDemo/simulation/qsim/DecoderDemo.msim.vcd...
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Processing channel transitions...
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Writing the resulting VWF to /home/tiagorg/repos/DecoderDemo/simulation/qsim/DecoderDemo_20221114214232.sim.vwf
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Finished VCD to VWF conversion.
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Completed successfully.
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All completed. |