uaveiro-leci/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.msim.vcd

$comment
	File created using the following command:
		vcd file DecoderDemo.msim.vcd -direction
$end
$date
	Mon Nov 14 21:42:31 2022
$end
$version
	ModelSim Version 2020.1
$end
$timescale
	1ps
$end

$scope module dec2_4_vhd_vec_tst $end
$var wire 1 ! E0L $end
$var wire 1 " E1 $end
$var wire 1 # X0 $end
$var wire 1 $ X1 $end
$var wire 1 % Y0 $end
$var wire 1 & Y1 $end
$var wire 1 ' Y2 $end
$var wire 1 ( Y3 $end

$scope module i1 $end
$var wire 1 ) gnd $end
$var wire 1 * vcc $end
$var wire 1 + unknown $end
$var wire 1 , devoe $end
$var wire 1 - devclrn $end
$var wire 1 . devpor $end
$var wire 1 / ww_devoe $end
$var wire 1 0 ww_devclrn $end
$var wire 1 1 ww_devpor $end
$var wire 1 2 ww_Y3 $end
$var wire 1 3 ww_E0L $end
$var wire 1 4 ww_E1 $end
$var wire 1 5 ww_X1 $end
$var wire 1 6 ww_X0 $end
$var wire 1 7 ww_Y2 $end
$var wire 1 8 ww_Y1 $end
$var wire 1 9 ww_Y0 $end
$var wire 1 : \Y3~output_o\ $end
$var wire 1 ; \Y2~output_o\ $end
$var wire 1 < \Y1~output_o\ $end
$var wire 1 = \Y0~output_o\ $end
$var wire 1 > \E1~input_o\ $end
$var wire 1 ? \X1~input_o\ $end
$var wire 1 @ \X0~input_o\ $end
$var wire 1 A \E0L~input_o\ $end
$var wire 1 B \inst~combout\ $end
$var wire 1 C \inst1~combout\ $end
$var wire 1 D \inst3~combout\ $end
$var wire 1 E \inst2~combout\ $end
$upscope $end
$upscope $end
$enddefinitions $end
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