TiagoRG 4fbb93468b LSD aula01 initial commit, base VHDL files, to be finished along the hardware		2023-02-20 22:37:38 +00:00
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AND2Gate.asm.rpt	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.done	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.eda.rpt	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.fit.rpt	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.fit.smsg	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.fit.summary	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.flow.rpt	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.jdi	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.map.rpt	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.map.summary	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.pin	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.sld	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.sof	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.sta.rpt	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00
AND2Gate.sta.summary	LSD aula01 initial commit, base VHDL files, to be finished along the hardware	2023-02-20 22:37:38 +00:00