22 lines
413 B
VHDL
22 lines
413 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1664.all;
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entity FlipFlopD_Demo is
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port(
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SW : std_logic_vector(2 downto 0);
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KEY : std_logic_vector(0 downto 0);
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LEDR : std_logic_vector(0 downto 0)
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);
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end FlipFlopD_Demo
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architecture Shell of FlipFlopD_Demo is
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begin
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ff_d : work.FlipFlopD(Behav)
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port map(
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clk => KEY(0 downto 0),
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d => SW(0),
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set => SW(1),
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reset => SW(2),
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q => LEDR(0 downto 0),
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);
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end Shell; |