37 lines
721 B
VHDL
37 lines
721 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity ShiftRegister_Demo is
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generic ( size : positive := 18);
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port
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(
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SW : in std_logic_vector(2 downto 0);
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CLOCK_50 : in std_logic;
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LEDR : out std_logic_vector((size-1) downto 0)
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);
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end ShiftRegister_Demo;
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architecture Shell of ShiftRegister_Demo is
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signal clk : std_logic;
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begin
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freqDevider : entity work.FreqDivider(Behavioral)
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generic map (divFactor => 25_000_000)
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port map
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(
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clkIn => CLOCK_50,
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clkOut => clk
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);
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system : entity work.ShiftRegisterN(Behav)
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generic map (size => size)
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port map
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(
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clk => clk,
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sin => SW(0),
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toleft => SW(1),
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enable => SW(2),
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dataOut => LEDR
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);
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end Shell; |