32 lines
739 B
VHDL
32 lines
739 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity ShiftRegisterN is
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generic ( size : positive := 4 );
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port
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(
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clk : in std_logic;
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sin : in std_logic;
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toleft : in std_logic;
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enable : in std_logic;
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dataOut : out std_logic_vector((size-1) downto 0)
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);
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end ShiftRegisterN;
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architecture Behav of ShiftRegisterN is
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signal aux : std_logic_vector((size-1) downto 0) := (others => '0');
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begin
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process(clk)
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begin
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if (rising_edge(clk)) then
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if (enable = '1') then
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if (toleft = '1') then
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aux <= aux((size-2) downto 0) & sin; -- deslocamento à esquerda
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else
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aux <= sin & aux((size-1) downto 1); -- deslocamento à direita
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end if;
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end if;
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end if;
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end process;
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dataOut <= aux;
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end Behav; |