30 lines
1.0 KiB
VHDL
30 lines
1.0 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Bin7SegDecoder is
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port
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(
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binInput : in std_logic_vector(3 downto 0);
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decOut_n : out std_logic_vector(6 downto 0)
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);
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end Bin7SegDecoder;
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architecture Behavioral of Bin7SegDecoder is
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begin
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decOut_n <= "1111001" when (binInput = "0001") else --1
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"0100100" when (binInput = "0010") else --2
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"0110000" when (binInput = "0011") else --3
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"0011001" when (binInput = "0100") else --4
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"0010010" when (binInput = "0101") else --5
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"0000010" when (binInput = "0110") else --6
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"1111000" when (binInput = "0111") else --7
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"0000000" when (binInput = "1000") else --8
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"0010000" when (binInput = "1001") else --9
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"0001000" when (binInput = "1010") else --A
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"0000011" when (binInput = "1011") else --b
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"1000110" when (binInput = "1100") else --C
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"0100001" when (binInput = "1101") else --d
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"0000110" when (binInput = "1110") else --E
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"0001110" when (binInput = "1111") else --F
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"1000000"; --0
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end Behavioral; |