38 lines
751 B
VHDL
38 lines
751 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Bin2Bcd is
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port
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(
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hexIn : in std_logic_vector(3 downto 0);
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decOut0 : out std_logic_vector(3 downto 0);
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decOut1 : out std_logic_vector(3 downto 0)
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);
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end Bin2Bcd;
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architecture Behavioral of Bin2Bcd is
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begin
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process (hexIn) is
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begin
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if hexIn < "1010" then
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decOut0 <= hexIn;
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decOut1 <= "0000";
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else
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if hexIn = "1010" then
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decOut0 <= "0000";
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elsif hexIn = "1011" then
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decOut0 <= "0001";
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elsif hexIn = "1100" then
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decOut0 <= "0010";
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elsif hexIn = "1101" then
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decOut0 <= "0011";
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elsif hexIn = "1110" then
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decOut0 <= "0100";
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else
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decOut0 <= "0101";
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end if;
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decOut1 <= "0001";
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end if;
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end process;
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end Behavioral;
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