vendor_name = ModelSim
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicUnit.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/LogicTop.bdf
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part3/db/LogicTop.cbx.xml
design_name = hard_block
design_name = LogicTop
instance = comp, \LEDR[5]~output\, LEDR[5]~output, LogicTop, 1
instance = comp, \LEDR[4]~output\, LEDR[4]~output, LogicTop, 1
instance = comp, \LEDR[3]~output\, LEDR[3]~output, LogicTop, 1
instance = comp, \LEDR[2]~output\, LEDR[2]~output, LogicTop, 1
instance = comp, \LEDR[1]~output\, LEDR[1]~output, LogicTop, 1
instance = comp, \LEDR[0]~output\, LEDR[0]~output, LogicTop, 1
instance = comp, \SW[1]~input\, SW[1]~input, LogicTop, 1
instance = comp, \SW[0]~input\, SW[0]~input, LogicTop, 1
instance = comp, \inst|norOut~0\, inst|norOut~0, LogicTop, 1
instance = comp, \inst|nandOut~0\, inst|nandOut~0, LogicTop, 1
instance = comp, \inst|xorOut\, inst|xorOut, LogicTop, 1