{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678882327474 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678882327475 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 15 12:12:07 2023 " "Processing started: Wed Mar 15 12:12:07 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678882327475 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882327475 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off FlipFlopD_Demo -c FlipFlopD_Demo" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882327475 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678882327844 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678882327844 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FlipFlopD_Demo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FlipFlopD_Demo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FlipFlopD_Demo-Shell " "Found design unit 1: FlipFlopD_Demo-Shell" {  } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 12 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882338356 ""} { "Info" "ISGN_ENTITY_NAME" "1 FlipFlopD_Demo " "Found entity 1: FlipFlopD_Demo" {  } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882338356 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882338356 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FlipFlopD.vhd 3 1 " "Found 3 design units, including 1 entities, in source file FlipFlopD.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FlipFlopD-BehavS " "Found design unit 1: FlipFlopD-BehavS" {  } { { "FlipFlopD.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd" 15 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882338357 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 FlipFlopD-BehavAs " "Found design unit 2: FlipFlopD-BehavAs" {  } { { "FlipFlopD.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd" 31 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882338357 ""} { "Info" "ISGN_ENTITY_NAME" "1 FlipFlopD " "Found entity 1: FlipFlopD" {  } { { "FlipFlopD.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678882338357 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882338357 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "FlipFlopD_Demo " "Elaborating entity \"FlipFlopD_Demo\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678882338433 ""}
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[1\] FlipFlopD_Demo.vhd(8) " "Using initial value X (don't care) for net \"LEDR\[1\]\" at FlipFlopD_Demo.vhd(8)" {  } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 8 0 0 } }  } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882338435 "|FlipFlopD_Demo"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "FlipFlopD FlipFlopD:ff_d A:behavs " "Elaborating entity \"FlipFlopD\" using architecture \"A:behavs\" for hierarchy \"FlipFlopD:ff_d\"" {  } { { "FlipFlopD_Demo.vhd" "ff_d" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 14 0 0 } }  } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678882338441 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" {  } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 8 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678882339208 "|FlipFlopD_Demo|LEDR[1]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1678882339208 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678882339364 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678882340198 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678882340198 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "No output dependent on input pin \"KEY\[1\]\"" {  } { { "FlipFlopD_Demo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/FlipFlopD_Demo/FlipFlopD_Demo.vhd" 7 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1678882340239 "|FlipFlopD_Demo|KEY[1]"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1678882340239 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "8 " "Implemented 8 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678882340240 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678882340240 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678882340240 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678882340240 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "432 " "Peak virtual memory: 432 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678882340249 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 15 12:12:20 2023 " "Processing ended: Wed Mar 15 12:12:20 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678882340249 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678882340249 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:35 " "Total CPU time (on all processors): 00:00:35" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678882340249 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678882340249 ""}