vendor_name = ModelSim
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo.cbx.xml
design_name = CounterDown4
instance = comp, \count[0]~output\, count[0]~output, CounterDown4, 1
instance = comp, \count[1]~output\, count[1]~output, CounterDown4, 1
instance = comp, \count[2]~output\, count[2]~output, CounterDown4, 1
instance = comp, \count[3]~output\, count[3]~output, CounterDown4, 1
instance = comp, \clk~input\, clk~input, CounterDown4, 1
instance = comp, \s_count[0]~0\, s_count[0]~0, CounterDown4, 1
instance = comp, \s_count[0]\, s_count[0], CounterDown4, 1
instance = comp, \Add0~0\, Add0~0, CounterDown4, 1
instance = comp, \s_count[1]\, s_count[1], CounterDown4, 1
instance = comp, \Add0~1\, Add0~1, CounterDown4, 1
instance = comp, \s_count[2]\, s_count[2], CounterDown4, 1
instance = comp, \Add0~2\, Add0~2, CounterDown4, 1
instance = comp, \s_count[3]\, s_count[3], CounterDown4, 1