$comment
	File created using the following command:
		vcd file CounterDemo.msim.vcd -direction
$end
$date
	Thu Mar 16 16:48:06 2023
$end
$version
	ModelSim Version 2020.1
$end
$timescale
	1ps
$end

$scope module counterdown4_vhd_vec_tst $end
$var wire 1 ! clk $end
$var wire 1 " count [3] $end
$var wire 1 # count [2] $end
$var wire 1 $ count [1] $end
$var wire 1 % count [0] $end

$scope module i1 $end
$var wire 1 & gnd $end
$var wire 1 ' vcc $end
$var wire 1 ( unknown $end
$var wire 1 ) devoe $end
$var wire 1 * devclrn $end
$var wire 1 + devpor $end
$var wire 1 , ww_devoe $end
$var wire 1 - ww_devclrn $end
$var wire 1 . ww_devpor $end
$var wire 1 / ww_clk $end
$var wire 1 0 ww_count [3] $end
$var wire 1 1 ww_count [2] $end
$var wire 1 2 ww_count [1] $end
$var wire 1 3 ww_count [0] $end
$var wire 1 4 \count[0]~output_o\ $end
$var wire 1 5 \count[1]~output_o\ $end
$var wire 1 6 \count[2]~output_o\ $end
$var wire 1 7 \count[3]~output_o\ $end
$var wire 1 8 \clk~input_o\ $end
$var wire 1 9 \s_count[0]~0_combout\ $end
$var wire 1 : \Add0~0_combout\ $end
$var wire 1 ; \Add0~1_combout\ $end
$var wire 1 < \Add0~2_combout\ $end
$var wire 1 = s_count [3] $end
$var wire 1 > s_count [2] $end
$var wire 1 ? s_count [1] $end
$var wire 1 @ s_count [0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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