{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1677674780626 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1677674780626 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar  1 12:46:20 2023 " "Processing started: Wed Mar  1 12:46:20 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1677674780626 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674780626 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off Dec2_4EnDemo -c Dec2_4EnDemo" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674780626 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1677674780758 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1677674780758 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec2_4En.vhd 4 1 " "Found 4 design units, including 1 entities, in source file Dec2_4En.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Dec2_4En-BehavEquations " "Found design unit 1: Dec2_4En-BehavEquations" {  } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 12 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785314 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 Dec2_4En-BehavAssign " "Found design unit 2: Dec2_4En-BehavAssign" {  } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 20 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785314 ""} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 Dec2_4En-BehavProc " "Found design unit 3: Dec2_4En-BehavProc" {  } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 29 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785314 ""} { "Info" "ISGN_ENTITY_NAME" "1 Dec2_4En " "Found entity 1: Dec2_4En" {  } { { "Dec2_4En.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4En.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785314 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674785314 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec2_4EnDemo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Dec2_4EnDemo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Dec2_4EnDemo-Shell " "Found design unit 1: Dec2_4EnDemo-Shell" {  } { { "Dec2_4EnDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd" 12 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785315 ""} { "Info" "ISGN_ENTITY_NAME" "1 Dec2_4EnDemo " "Found entity 1: Dec2_4EnDemo" {  } { { "Dec2_4EnDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd" 4 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1677674785315 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674785315 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "Dec2_4EnDemo " "Elaborating entity \"Dec2_4EnDemo\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1677674785339 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "Dec2_4En Dec2_4En:system_core A:behavproc " "Elaborating entity \"Dec2_4En\" using architecture \"A:behavproc\" for hierarchy \"Dec2_4En:system_core\"" {  } { { "Dec2_4EnDemo.vhd" "system_core" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/aula02/part1/Dec2_4EnDemo.vhd" 14 0 0 } }  } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677674785342 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1677674785652 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1677674785940 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1677674785940 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "11 " "Implemented 11 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1677674785955 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1677674785955 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1677674785955 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1677674785955 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "429 " "Peak virtual memory: 429 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1677674785958 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar  1 12:46:25 2023 " "Processing ended: Wed Mar  1 12:46:25 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1677674785958 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1677674785958 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1677674785958 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1677674785958 ""}