# do Mux4_1Demo.do
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:35:04 on Mar 07,2023
# vcom -work work Mux4_1Demo.vho 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package VITAL_Timing
# -- Loading package VITAL_Primitives
# -- Loading package cycloneive_atom_pack
# -- Loading package cycloneive_components
# -- Compiling entity Mux4_1
# -- Compiling architecture structure of Mux4_1
# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 22:35:05 on Mar 07,2023
# vcom -work work Mux4_1.vwf.vht 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity Mux4_1_vhd_vec_tst
# -- Compiling architecture Mux4_1_arch of Mux4_1_vhd_vec_tst
# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux4_1_vhd_vec_tst 
# Start time: 22:35:05 on Mar 07,2023
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.mux4_1_vhd_vec_tst(mux4_1_arch)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading cycloneive.cycloneive_atom_pack(body)
# Loading cycloneive.cycloneive_components
# Loading work.mux4_1(structure)
# Loading ieee.std_logic_arith(body)
# Loading cycloneive.cycloneive_io_obuf(arch)
# Loading cycloneive.cycloneive_io_ibuf(arch)
# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
# after#29
# End time: 22:35:05 on Mar 07,2023, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0