vendor_name = ModelSim
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/FullAdder.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/Adder4.vwf
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AdderDemo.bdf
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/AddSub4.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/AdderDemo/db/AdderDemo.cbx.xml
design_name = hard_block
design_name = AdderDemo
instance = comp, \LEDR[14]~output\, LEDR[14]~output, AdderDemo, 1
instance = comp, \LEDR[13]~output\, LEDR[13]~output, AdderDemo, 1
instance = comp, \LEDR[12]~output\, LEDR[12]~output, AdderDemo, 1
instance = comp, \LEDR[11]~output\, LEDR[11]~output, AdderDemo, 1
instance = comp, \LEDR[10]~output\, LEDR[10]~output, AdderDemo, 1
instance = comp, \LEDR[9]~output\, LEDR[9]~output, AdderDemo, 1
instance = comp, \LEDR[8]~output\, LEDR[8]~output, AdderDemo, 1
instance = comp, \LEDR[7]~output\, LEDR[7]~output, AdderDemo, 1
instance = comp, \LEDR[6]~output\, LEDR[6]~output, AdderDemo, 1
instance = comp, \LEDR[5]~output\, LEDR[5]~output, AdderDemo, 1
instance = comp, \LEDR[4]~output\, LEDR[4]~output, AdderDemo, 1
instance = comp, \LEDR[3]~output\, LEDR[3]~output, AdderDemo, 1
instance = comp, \LEDR[2]~output\, LEDR[2]~output, AdderDemo, 1
instance = comp, \LEDR[1]~output\, LEDR[1]~output, AdderDemo, 1
instance = comp, \LEDR[0]~output\, LEDR[0]~output, AdderDemo, 1
instance = comp, \KEY[0]~input\, KEY[0]~input, AdderDemo, 1
instance = comp, \SW[17]~input\, SW[17]~input, AdderDemo, 1
instance = comp, \SW[13]~input\, SW[13]~input, AdderDemo, 1
instance = comp, \AddSub4Demo|Add0~0\, AddSub4Demo|Add0~0, AdderDemo, 1
instance = comp, \SW[12]~input\, SW[12]~input, AdderDemo, 1
instance = comp, \AddSub4Demo|Add0~1\, AddSub4Demo|Add0~1, AdderDemo, 1
instance = comp, \SW[16]~input\, SW[16]~input, AdderDemo, 1
instance = comp, \SW[11]~input\, SW[11]~input, AdderDemo, 1
instance = comp, \AddSub4Demo|Add0~2\, AddSub4Demo|Add0~2, AdderDemo, 1
instance = comp, \SW[15]~input\, SW[15]~input, AdderDemo, 1
instance = comp, \SW[10]~input\, SW[10]~input, AdderDemo, 1
instance = comp, \AddSub4Demo|Add0~3\, AddSub4Demo|Add0~3, AdderDemo, 1
instance = comp, \SW[14]~input\, SW[14]~input, AdderDemo, 1
instance = comp, \AddSub4Demo|Add0~5\, AddSub4Demo|Add0~5, AdderDemo, 1
instance = comp, \AddSub4Demo|Add0~6\, AddSub4Demo|Add0~6, AdderDemo, 1
instance = comp, \AddSub4Demo|Add0~8\, AddSub4Demo|Add0~8, AdderDemo, 1
instance = comp, \AddSub4Demo|Add0~10\, AddSub4Demo|Add0~10, AdderDemo, 1
instance = comp, \AddSub4Demo|Add0~12\, AddSub4Demo|Add0~12, AdderDemo, 1
instance = comp, \AddSub4Demo|Add0~14\, AddSub4Demo|Add0~14, AdderDemo, 1
instance = comp, \SW[1]~input\, SW[1]~input, AdderDemo, 1
instance = comp, \SW[0]~input\, SW[0]~input, AdderDemo, 1
instance = comp, \SW[5]~input\, SW[5]~input, AdderDemo, 1
instance = comp, \SW[4]~input\, SW[4]~input, AdderDemo, 1
instance = comp, \Adder4Demo|bit1|cout~0\, Adder4Demo|bit1|cout~0, AdderDemo, 1
instance = comp, \SW[6]~input\, SW[6]~input, AdderDemo, 1
instance = comp, \SW[2]~input\, SW[2]~input, AdderDemo, 1
instance = comp, \Adder4Demo|bit2|cout~0\, Adder4Demo|bit2|cout~0, AdderDemo, 1
instance = comp, \SW[3]~input\, SW[3]~input, AdderDemo, 1
instance = comp, \SW[7]~input\, SW[7]~input, AdderDemo, 1
instance = comp, \Adder4Demo|bit3|cout~0\, Adder4Demo|bit3|cout~0, AdderDemo, 1
instance = comp, \Adder4Demo|bit3|s\, Adder4Demo|bit3|s, AdderDemo, 1
instance = comp, \Adder4Demo|bit2|s~0\, Adder4Demo|bit2|s~0, AdderDemo, 1
instance = comp, \Adder4Demo|bit1|s~0\, Adder4Demo|bit1|s~0, AdderDemo, 1
instance = comp, \Adder4Demo|bit0|s~0\, Adder4Demo|bit0|s~0, AdderDemo, 1
instance = comp, \SW[9]~input\, SW[9]~input, AdderDemo, 1
instance = comp, \SW[8]~input\, SW[8]~input, AdderDemo, 1