// Copyright (C) 2020  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"

// DATE "11/18/2022 13:06:36"

// 
// Device: Altera EP4CE6E22C6 Package TQFP144
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module Mux16_1 (
	pin_name1,
	Sel4,
	Sel3,
	Sel2,
	Sel1,
	I0,
	ze,
	I2,
	I3,
	I4,
	I5,
	I6,
	I7,
	I8,
	I9,
	I10,
	I11,
	I12,
	I13,
	I14,
	I15);
output 	pin_name1;
input 	Sel4;
input 	Sel3;
input 	Sel2;
input 	Sel1;
input 	I0;
input 	ze;
input 	I2;
input 	I3;
input 	I4;
input 	I5;
input 	I6;
input 	I7;
input 	I8;
input 	I9;
input 	I10;
input 	I11;
input 	I12;
input 	I13;
input 	I14;
input 	I15;

// Design Ports Information
// pin_name1	=>  Location: PIN_76,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I10	=>  Location: PIN_46,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Sel2	=>  Location: PIN_80,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I9	=>  Location: PIN_65,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Sel1	=>  Location: PIN_112,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I8	=>  Location: PIN_68,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I11	=>  Location: PIN_87,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Sel4	=>  Location: PIN_121,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I5	=>  Location: PIN_85,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I6	=>  Location: PIN_86,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I4	=>  Location: PIN_69,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I7	=>  Location: PIN_88,	 I/O Standard: 2.5 V,	 Current Strength: Default
// Sel3	=>  Location: PIN_89,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I2	=>  Location: PIN_74,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ze	=>  Location: PIN_90,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I0	=>  Location: PIN_91,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I3	=>  Location: PIN_84,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I13	=>  Location: PIN_66,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I14	=>  Location: PIN_120,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I12	=>  Location: PIN_83,	 I/O Standard: 2.5 V,	 Current Strength: Default
// I15	=>  Location: PIN_77,	 I/O Standard: 2.5 V,	 Current Strength: Default


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \pin_name1~output_o ;
wire \I14~input_o ;
wire \Sel2~input_o ;
wire \Sel1~input_o ;
wire \I12~input_o ;
wire \inst14|inst2~7_combout ;
wire \I13~input_o ;
wire \I15~input_o ;
wire \inst14|inst2~8_combout ;
wire \I5~input_o ;
wire \I6~input_o ;
wire \I4~input_o ;
wire \inst14|inst2~2_combout ;
wire \I7~input_o ;
wire \inst14|inst2~3_combout ;
wire \Sel4~input_o ;
wire \Sel3~input_o ;
wire \I2~input_o ;
wire \ze~input_o ;
wire \I0~input_o ;
wire \inst14|inst2~4_combout ;
wire \I3~input_o ;
wire \inst14|inst2~5_combout ;
wire \inst14|inst2~6_combout ;
wire \I10~input_o ;
wire \I8~input_o ;
wire \I9~input_o ;
wire \inst14|inst2~0_combout ;
wire \I11~input_o ;
wire \inst14|inst2~1_combout ;
wire \inst14|inst2~9_combout ;


hard_block auto_generated_inst(
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// Location: IOOBUF_X34_Y4_N23
cycloneive_io_obuf \pin_name1~output (
	.i(\inst14|inst2~9_combout ),
	.oe(vcc),
	.seriesterminationcontrol(16'b0000000000000000),
	.devoe(devoe),
	.o(\pin_name1~output_o ),
	.obar());
// synopsys translate_off
defparam \pin_name1~output .bus_hold = "false";
defparam \pin_name1~output .open_drain_output = "false";
// synopsys translate_on

// Location: IOIBUF_X23_Y24_N8
cycloneive_io_ibuf \I14~input (
	.i(I14),
	.ibar(gnd),
	.o(\I14~input_o ));
// synopsys translate_off
defparam \I14~input .bus_hold = "false";
defparam \I14~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X34_Y7_N8
cycloneive_io_ibuf \Sel2~input (
	.i(Sel2),
	.ibar(gnd),
	.o(\Sel2~input_o ));
// synopsys translate_off
defparam \Sel2~input .bus_hold = "false";
defparam \Sel2~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X28_Y24_N1
cycloneive_io_ibuf \Sel1~input (
	.i(Sel1),
	.ibar(gnd),
	.o(\Sel1~input_o ));
// synopsys translate_off
defparam \Sel1~input .bus_hold = "false";
defparam \Sel1~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X34_Y9_N22
cycloneive_io_ibuf \I12~input (
	.i(I12),
	.ibar(gnd),
	.o(\I12~input_o ));
// synopsys translate_off
defparam \I12~input .bus_hold = "false";
defparam \I12~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X28_Y8_N12
cycloneive_lcell_comb \inst14|inst2~7 (
// Equation(s):
// \inst14|inst2~7_combout  = (\Sel2~input_o  & ((\I14~input_o ) # ((\Sel1~input_o )))) # (!\Sel2~input_o  & (((!\Sel1~input_o  & \I12~input_o ))))

	.dataa(\I14~input_o ),
	.datab(\Sel2~input_o ),
	.datac(\Sel1~input_o ),
	.datad(\I12~input_o ),
	.cin(gnd),
	.combout(\inst14|inst2~7_combout ),
	.cout());
// synopsys translate_off
defparam \inst14|inst2~7 .lut_mask = 16'hCBC8;
defparam \inst14|inst2~7 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X28_Y0_N1
cycloneive_io_ibuf \I13~input (
	.i(I13),
	.ibar(gnd),
	.o(\I13~input_o ));
// synopsys translate_off
defparam \I13~input .bus_hold = "false";
defparam \I13~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X34_Y4_N15
cycloneive_io_ibuf \I15~input (
	.i(I15),
	.ibar(gnd),
	.o(\I15~input_o ));
// synopsys translate_off
defparam \I15~input .bus_hold = "false";
defparam \I15~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X28_Y8_N6
cycloneive_lcell_comb \inst14|inst2~8 (
// Equation(s):
// \inst14|inst2~8_combout  = (\inst14|inst2~7_combout  & (((\I15~input_o )) # (!\Sel1~input_o ))) # (!\inst14|inst2~7_combout  & (\Sel1~input_o  & (\I13~input_o )))

	.dataa(\inst14|inst2~7_combout ),
	.datab(\Sel1~input_o ),
	.datac(\I13~input_o ),
	.datad(\I15~input_o ),
	.cin(gnd),
	.combout(\inst14|inst2~8_combout ),
	.cout());
// synopsys translate_off
defparam \inst14|inst2~8 .lut_mask = 16'hEA62;
defparam \inst14|inst2~8 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X34_Y9_N8
cycloneive_io_ibuf \I5~input (
	.i(I5),
	.ibar(gnd),
	.o(\I5~input_o ));
// synopsys translate_off
defparam \I5~input .bus_hold = "false";
defparam \I5~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X34_Y9_N1
cycloneive_io_ibuf \I6~input (
	.i(I6),
	.ibar(gnd),
	.o(\I6~input_o ));
// synopsys translate_off
defparam \I6~input .bus_hold = "false";
defparam \I6~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X30_Y0_N1
cycloneive_io_ibuf \I4~input (
	.i(I4),
	.ibar(gnd),
	.o(\I4~input_o ));
// synopsys translate_off
defparam \I4~input .bus_hold = "false";
defparam \I4~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X28_Y8_N20
cycloneive_lcell_comb \inst14|inst2~2 (
// Equation(s):
// \inst14|inst2~2_combout  = (\Sel1~input_o  & (((\Sel2~input_o )))) # (!\Sel1~input_o  & ((\Sel2~input_o  & (\I6~input_o )) # (!\Sel2~input_o  & ((\I4~input_o )))))

	.dataa(\I6~input_o ),
	.datab(\I4~input_o ),
	.datac(\Sel1~input_o ),
	.datad(\Sel2~input_o ),
	.cin(gnd),
	.combout(\inst14|inst2~2_combout ),
	.cout());
// synopsys translate_off
defparam \inst14|inst2~2 .lut_mask = 16'hFA0C;
defparam \inst14|inst2~2 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X34_Y12_N22
cycloneive_io_ibuf \I7~input (
	.i(I7),
	.ibar(gnd),
	.o(\I7~input_o ));
// synopsys translate_off
defparam \I7~input .bus_hold = "false";
defparam \I7~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X28_Y8_N22
cycloneive_lcell_comb \inst14|inst2~3 (
// Equation(s):
// \inst14|inst2~3_combout  = (\inst14|inst2~2_combout  & (((\I7~input_o ) # (!\Sel1~input_o )))) # (!\inst14|inst2~2_combout  & (\I5~input_o  & (\Sel1~input_o )))

	.dataa(\I5~input_o ),
	.datab(\inst14|inst2~2_combout ),
	.datac(\Sel1~input_o ),
	.datad(\I7~input_o ),
	.cin(gnd),
	.combout(\inst14|inst2~3_combout ),
	.cout());
// synopsys translate_off
defparam \inst14|inst2~3 .lut_mask = 16'hEC2C;
defparam \inst14|inst2~3 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X23_Y24_N15
cycloneive_io_ibuf \Sel4~input (
	.i(Sel4),
	.ibar(gnd),
	.o(\Sel4~input_o ));
// synopsys translate_off
defparam \Sel4~input .bus_hold = "false";
defparam \Sel4~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X34_Y12_N15
cycloneive_io_ibuf \Sel3~input (
	.i(Sel3),
	.ibar(gnd),
	.o(\Sel3~input_o ));
// synopsys translate_off
defparam \Sel3~input .bus_hold = "false";
defparam \Sel3~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X34_Y2_N15
cycloneive_io_ibuf \I2~input (
	.i(I2),
	.ibar(gnd),
	.o(\I2~input_o ));
// synopsys translate_off
defparam \I2~input .bus_hold = "false";
defparam \I2~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X34_Y12_N8
cycloneive_io_ibuf \ze~input (
	.i(ze),
	.ibar(gnd),
	.o(\ze~input_o ));
// synopsys translate_off
defparam \ze~input .bus_hold = "false";
defparam \ze~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X34_Y12_N1
cycloneive_io_ibuf \I0~input (
	.i(I0),
	.ibar(gnd),
	.o(\I0~input_o ));
// synopsys translate_off
defparam \I0~input .bus_hold = "false";
defparam \I0~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X33_Y8_N8
cycloneive_lcell_comb \inst14|inst2~4 (
// Equation(s):
// \inst14|inst2~4_combout  = (\Sel2~input_o  & (((\Sel1~input_o )))) # (!\Sel2~input_o  & ((\Sel1~input_o  & (\ze~input_o )) # (!\Sel1~input_o  & ((\I0~input_o )))))

	.dataa(\ze~input_o ),
	.datab(\Sel2~input_o ),
	.datac(\Sel1~input_o ),
	.datad(\I0~input_o ),
	.cin(gnd),
	.combout(\inst14|inst2~4_combout ),
	.cout());
// synopsys translate_off
defparam \inst14|inst2~4 .lut_mask = 16'hE3E0;
defparam \inst14|inst2~4 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X34_Y9_N15
cycloneive_io_ibuf \I3~input (
	.i(I3),
	.ibar(gnd),
	.o(\I3~input_o ));
// synopsys translate_off
defparam \I3~input .bus_hold = "false";
defparam \I3~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X28_Y8_N24
cycloneive_lcell_comb \inst14|inst2~5 (
// Equation(s):
// \inst14|inst2~5_combout  = (\Sel2~input_o  & ((\inst14|inst2~4_combout  & ((\I3~input_o ))) # (!\inst14|inst2~4_combout  & (\I2~input_o )))) # (!\Sel2~input_o  & (((\inst14|inst2~4_combout ))))

	.dataa(\I2~input_o ),
	.datab(\Sel2~input_o ),
	.datac(\inst14|inst2~4_combout ),
	.datad(\I3~input_o ),
	.cin(gnd),
	.combout(\inst14|inst2~5_combout ),
	.cout());
// synopsys translate_off
defparam \inst14|inst2~5 .lut_mask = 16'hF838;
defparam \inst14|inst2~5 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y8_N18
cycloneive_lcell_comb \inst14|inst2~6 (
// Equation(s):
// \inst14|inst2~6_combout  = (\Sel4~input_o  & (((\Sel3~input_o )))) # (!\Sel4~input_o  & ((\Sel3~input_o  & (\inst14|inst2~3_combout )) # (!\Sel3~input_o  & ((\inst14|inst2~5_combout )))))

	.dataa(\inst14|inst2~3_combout ),
	.datab(\Sel4~input_o ),
	.datac(\Sel3~input_o ),
	.datad(\inst14|inst2~5_combout ),
	.cin(gnd),
	.combout(\inst14|inst2~6_combout ),
	.cout());
// synopsys translate_off
defparam \inst14|inst2~6 .lut_mask = 16'hE3E0;
defparam \inst14|inst2~6 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X7_Y0_N1
cycloneive_io_ibuf \I10~input (
	.i(I10),
	.ibar(gnd),
	.o(\I10~input_o ));
// synopsys translate_off
defparam \I10~input .bus_hold = "false";
defparam \I10~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X30_Y0_N8
cycloneive_io_ibuf \I8~input (
	.i(I8),
	.ibar(gnd),
	.o(\I8~input_o ));
// synopsys translate_off
defparam \I8~input .bus_hold = "false";
defparam \I8~input .simulate_z_as = "z";
// synopsys translate_on

// Location: IOIBUF_X28_Y0_N22
cycloneive_io_ibuf \I9~input (
	.i(I9),
	.ibar(gnd),
	.o(\I9~input_o ));
// synopsys translate_off
defparam \I9~input .bus_hold = "false";
defparam \I9~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X28_Y8_N0
cycloneive_lcell_comb \inst14|inst2~0 (
// Equation(s):
// \inst14|inst2~0_combout  = (\Sel1~input_o  & (((\I9~input_o ) # (\Sel2~input_o )))) # (!\Sel1~input_o  & (\I8~input_o  & ((!\Sel2~input_o ))))

	.dataa(\I8~input_o ),
	.datab(\Sel1~input_o ),
	.datac(\I9~input_o ),
	.datad(\Sel2~input_o ),
	.cin(gnd),
	.combout(\inst14|inst2~0_combout ),
	.cout());
// synopsys translate_off
defparam \inst14|inst2~0 .lut_mask = 16'hCCE2;
defparam \inst14|inst2~0 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: IOIBUF_X34_Y10_N8
cycloneive_io_ibuf \I11~input (
	.i(I11),
	.ibar(gnd),
	.o(\I11~input_o ));
// synopsys translate_off
defparam \I11~input .bus_hold = "false";
defparam \I11~input .simulate_z_as = "z";
// synopsys translate_on

// Location: LCCOMB_X28_Y8_N10
cycloneive_lcell_comb \inst14|inst2~1 (
// Equation(s):
// \inst14|inst2~1_combout  = (\inst14|inst2~0_combout  & (((\I11~input_o ) # (!\Sel2~input_o )))) # (!\inst14|inst2~0_combout  & (\I10~input_o  & ((\Sel2~input_o ))))

	.dataa(\I10~input_o ),
	.datab(\inst14|inst2~0_combout ),
	.datac(\I11~input_o ),
	.datad(\Sel2~input_o ),
	.cin(gnd),
	.combout(\inst14|inst2~1_combout ),
	.cout());
// synopsys translate_off
defparam \inst14|inst2~1 .lut_mask = 16'hE2CC;
defparam \inst14|inst2~1 .sum_lutc_input = "datac";
// synopsys translate_on

// Location: LCCOMB_X28_Y8_N8
cycloneive_lcell_comb \inst14|inst2~9 (
// Equation(s):
// \inst14|inst2~9_combout  = (\inst14|inst2~6_combout  & ((\inst14|inst2~8_combout ) # ((!\Sel4~input_o )))) # (!\inst14|inst2~6_combout  & (((\Sel4~input_o  & \inst14|inst2~1_combout ))))

	.dataa(\inst14|inst2~8_combout ),
	.datab(\inst14|inst2~6_combout ),
	.datac(\Sel4~input_o ),
	.datad(\inst14|inst2~1_combout ),
	.cin(gnd),
	.combout(\inst14|inst2~9_combout ),
	.cout());
// synopsys translate_off
defparam \inst14|inst2~9 .lut_mask = 16'hBC8C;
defparam \inst14|inst2~9 .sum_lutc_input = "datac";
// synopsys translate_on

assign pin_name1 = \pin_name1~output_o ;

endmodule

module hard_block (

	devpor,
	devclrn,
	devoe);

// Design Ports Information
// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_6,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_8,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DCLK~	=>  Location: PIN_12,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_DATA0~	=>  Location: PIN_13,	 I/O Standard: 2.5 V,	 Current Strength: Default
// ~ALTERA_nCEO~	=>  Location: PIN_101,	 I/O Standard: 2.5 V,	 Current Strength: 8mA

input 	devpor;
input 	devclrn;
input 	devoe;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

wire \~ALTERA_ASDO_DATA1~~padout ;
wire \~ALTERA_FLASH_nCE_nCSO~~padout ;
wire \~ALTERA_DATA0~~padout ;
wire \~ALTERA_ASDO_DATA1~~ibuf_o ;
wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ;
wire \~ALTERA_DATA0~~ibuf_o ;


endmodule