vendor_name = ModelSim
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/Teste/Teste1.bdf
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/Teste/Waveform.vwf
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/isd/quartus-projects/Teste/Teste3.bdf
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/others/maxplus2/74153.bdf
design_name = hard_block
design_name = Teste3
instance = comp, \F~output\, F~output, Teste3, 1
instance = comp, \C~input\, C~input, Teste3, 1
instance = comp, \D~input\, D~input, Teste3, 1
instance = comp, \A~input\, A~input, Teste3, 1
instance = comp, \B~input\, B~input, Teste3, 1
instance = comp, \inst|inst3~0\, inst|inst3~0, Teste3, 1