Flow report for AND2Gate Tue Mar 7 20:31:07 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Flow Summary 3. Flow Settings 4. Flow Non-Default Global Settings 5. Flow Elapsed Time 6. Flow OS Summary 7. Flow Log 8. Flow Messages 9. Flow Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2020 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details, at https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+---------------------------------------------+ ; Flow Status ; Successful - Tue Mar 7 20:31:07 2023 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Revision Name ; AND2Gate ; ; Top-level Entity Name ; GateDemo ; ; Family ; Cyclone IV E ; ; Device ; EP4CE115F29C7 ; ; Timing Models ; Final ; ; Total logic elements ; 1 / 114,480 ( < 1 % ) ; ; Total combinational functions ; 1 / 114,480 ( < 1 % ) ; ; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ; ; Total registers ; 0 ; ; Total pins ; 4 / 529 ( < 1 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 / 3,981,312 ( 0 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; ; Total PLLs ; 0 / 4 ( 0 % ) ; +------------------------------------+---------------------------------------------+ +-----------------------------------------+ ; Flow Settings ; +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ ; Start date & time ; 03/07/2023 20:30:44 ; ; Main task ; Compilation ; ; Revision Name ; AND2Gate ; +-------------------+---------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------+ ; Flow Non-Default Global Settings ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; COMPILER_SIGNATURE_ID ; 2690080394329.167822104406633 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ; ; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ; ; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ; ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; ; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; GateDemo ; Top ; ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; GateDemo ; Top ; ; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; GateDemo ; Top ; ; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; ; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ; TOP_LEVEL_ENTITY ; GateDemo ; AND2Gate ; -- ; -- ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Flow Elapsed Time ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 432 MB ; 00:00:16 ; ; Fitter ; 00:00:10 ; 1.0 ; 1142 MB ; 00:00:15 ; ; Assembler ; 00:00:03 ; 1.0 ; 367 MB ; 00:00:03 ; ; Timing Analyzer ; 00:00:02 ; 1.0 ; 533 MB ; 00:00:01 ; ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:00 ; ; Total ; 00:00:23 ; -- ; -- ; 00:00:35 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------------------------------------------------------------------------+ ; Flow OS Summary ; +----------------------+------------------+----------------+------------+----------------+ ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; +----------------------+------------------+----------------+------------+----------------+ ; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; ; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; ; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; ; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; ; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; +----------------------+------------------+----------------+------------+----------------+ ------------ ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate quartus_fit --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate quartus_sta VHDLDemo -c AND2Gate quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate