vendor_name = ModelSim
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/Bin7SegDecoder.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd
source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd
source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.cbx.xml
design_name = hard_block
design_name = DisplayDemo
instance = comp, \HEX0[6]~output\, HEX0[6]~output, DisplayDemo, 1
instance = comp, \HEX0[5]~output\, HEX0[5]~output, DisplayDemo, 1
instance = comp, \HEX0[4]~output\, HEX0[4]~output, DisplayDemo, 1
instance = comp, \HEX0[3]~output\, HEX0[3]~output, DisplayDemo, 1
instance = comp, \HEX0[2]~output\, HEX0[2]~output, DisplayDemo, 1
instance = comp, \HEX0[1]~output\, HEX0[1]~output, DisplayDemo, 1
instance = comp, \HEX0[0]~output\, HEX0[0]~output, DisplayDemo, 1
instance = comp, \LEDG[3]~output\, LEDG[3]~output, DisplayDemo, 1
instance = comp, \LEDG[2]~output\, LEDG[2]~output, DisplayDemo, 1
instance = comp, \LEDG[1]~output\, LEDG[1]~output, DisplayDemo, 1
instance = comp, \LEDG[0]~output\, LEDG[0]~output, DisplayDemo, 1
instance = comp, \LEDR[6]~output\, LEDR[6]~output, DisplayDemo, 1
instance = comp, \LEDR[5]~output\, LEDR[5]~output, DisplayDemo, 1
instance = comp, \LEDR[4]~output\, LEDR[4]~output, DisplayDemo, 1
instance = comp, \LEDR[3]~output\, LEDR[3]~output, DisplayDemo, 1
instance = comp, \LEDR[2]~output\, LEDR[2]~output, DisplayDemo, 1
instance = comp, \LEDR[1]~output\, LEDR[1]~output, DisplayDemo, 1
instance = comp, \LEDR[0]~output\, LEDR[0]~output, DisplayDemo, 1
instance = comp, \KEY[0]~input\, KEY[0]~input, DisplayDemo, 1
instance = comp, \SW[3]~input\, SW[3]~input, DisplayDemo, 1
instance = comp, \SW[0]~input\, SW[0]~input, DisplayDemo, 1
instance = comp, \SW[1]~input\, SW[1]~input, DisplayDemo, 1
instance = comp, \SW[2]~input\, SW[2]~input, DisplayDemo, 1
instance = comp, \inst|decOut_n[6]~0\, inst|decOut_n[6]~0, DisplayDemo, 1
instance = comp, \inst|decOut_n[6]~1\, inst|decOut_n[6]~1, DisplayDemo, 1
instance = comp, \inst|decOut_n~2\, inst|decOut_n~2, DisplayDemo, 1
instance = comp, \inst|decOut_n~3\, inst|decOut_n~3, DisplayDemo, 1
instance = comp, \inst|decOut_n~4\, inst|decOut_n~4, DisplayDemo, 1
instance = comp, \inst|decOut_n~5\, inst|decOut_n~5, DisplayDemo, 1
instance = comp, \inst|decOut_n[3]~6\, inst|decOut_n[3]~6, DisplayDemo, 1
instance = comp, \inst|decOut_n[3]~7\, inst|decOut_n[3]~7, DisplayDemo, 1
instance = comp, \inst|decOut_n~8\, inst|decOut_n~8, DisplayDemo, 1
instance = comp, \inst|decOut_n~9\, inst|decOut_n~9, DisplayDemo, 1
instance = comp, \inst|decOut_n~10\, inst|decOut_n~10, DisplayDemo, 1
instance = comp, \inst|decOut_n~11\, inst|decOut_n~11, DisplayDemo, 1
instance = comp, \inst|decOut_n~12\, inst|decOut_n~12, DisplayDemo, 1
instance = comp, \inst|decOut_n~13\, inst|decOut_n~13, DisplayDemo, 1