|ALU4
a[0] => Mult0.IN3
a[0] => Add0.IN4
a[0] => Add1.IN8
a[0] => Div0.IN3
a[0] => Mod0.IN3
a[0] => RESULT.IN0
a[0] => RESULT.IN0
a[0] => RESULT.IN0
a[1] => Mult0.IN2
a[1] => Add0.IN3
a[1] => Add1.IN7
a[1] => Div0.IN2
a[1] => Mod0.IN2
a[1] => RESULT.IN0
a[1] => RESULT.IN0
a[1] => RESULT.IN0
a[2] => Mult0.IN1
a[2] => Add0.IN2
a[2] => Add1.IN6
a[2] => Div0.IN1
a[2] => Mod0.IN1
a[2] => RESULT.IN0
a[2] => RESULT.IN0
a[2] => RESULT.IN0
a[3] => Mult0.IN0
a[3] => Add0.IN1
a[3] => Add1.IN5
a[3] => Div0.IN0
a[3] => Mod0.IN0
a[3] => RESULT.IN0
a[3] => RESULT.IN0
a[3] => RESULT.IN0
b[0] => Mult0.IN7
b[0] => Add0.IN8
b[0] => Div0.IN7
b[0] => Mod0.IN7
b[0] => RESULT.IN1
b[0] => RESULT.IN1
b[0] => RESULT.IN1
b[0] => Add1.IN4
b[1] => Mult0.IN6
b[1] => Add0.IN7
b[1] => Div0.IN6
b[1] => Mod0.IN6
b[1] => RESULT.IN1
b[1] => RESULT.IN1
b[1] => RESULT.IN1
b[1] => Add1.IN3
b[2] => Mult0.IN5
b[2] => Add0.IN6
b[2] => Div0.IN5
b[2] => Mod0.IN5
b[2] => RESULT.IN1
b[2] => RESULT.IN1
b[2] => RESULT.IN1
b[2] => Add1.IN2
b[3] => Mult0.IN4
b[3] => Add0.IN5
b[3] => Div0.IN4
b[3] => Mod0.IN4
b[3] => RESULT.IN1
b[3] => RESULT.IN1
b[3] => RESULT.IN1
b[3] => Add1.IN1
op[0] => Mux0.IN9
op[0] => Mux1.IN9
op[0] => Mux2.IN9
op[0] => Mux3.IN9
op[0] => Equal0.IN1
op[1] => Mux0.IN8
op[1] => Mux1.IN8
op[1] => Mux2.IN8
op[1] => Mux3.IN8
op[1] => Equal0.IN2
op[2] => Mux0.IN7
op[2] => Mux1.IN7
op[2] => Mux2.IN7
op[2] => Mux3.IN7
op[2] => Equal0.IN0
r[0] << Mux3.DB_MAX_OUTPUT_PORT_TYPE
r[1] << Mux2.DB_MAX_OUTPUT_PORT_TYPE
r[2] << Mux1.DB_MAX_OUTPUT_PORT_TYPE
r[3] << Mux0.DB_MAX_OUTPUT_PORT_TYPE
m[0] << m.DB_MAX_OUTPUT_PORT_TYPE
m[1] << m.DB_MAX_OUTPUT_PORT_TYPE
m[2] << m.DB_MAX_OUTPUT_PORT_TYPE
m[3] << m.DB_MAX_OUTPUT_PORT_TYPE