$comment
	File created using the following command:
		vcd file LogicDemo.msim.vcd -direction
$end
$date
	Tue Mar  7 20:45:48 2023
$end
$version
	ModelSim Version 2020.1
$end
$timescale
	1ps
$end

$scope module logictop_vhd_vec_tst $end
$var wire 1 ! LEDR [5] $end
$var wire 1 " LEDR [4] $end
$var wire 1 # LEDR [3] $end
$var wire 1 $ LEDR [2] $end
$var wire 1 % LEDR [1] $end
$var wire 1 & LEDR [0] $end
$var wire 1 ' SW [1] $end
$var wire 1 ( SW [0] $end

$scope module i1 $end
$var wire 1 ) gnd $end
$var wire 1 * vcc $end
$var wire 1 + unknown $end
$var wire 1 , devoe $end
$var wire 1 - devclrn $end
$var wire 1 . devpor $end
$var wire 1 / ww_devoe $end
$var wire 1 0 ww_devclrn $end
$var wire 1 1 ww_devpor $end
$var wire 1 2 ww_LEDR [5] $end
$var wire 1 3 ww_LEDR [4] $end
$var wire 1 4 ww_LEDR [3] $end
$var wire 1 5 ww_LEDR [2] $end
$var wire 1 6 ww_LEDR [1] $end
$var wire 1 7 ww_LEDR [0] $end
$var wire 1 8 ww_SW [1] $end
$var wire 1 9 ww_SW [0] $end
$var wire 1 : \LEDR[5]~output_o\ $end
$var wire 1 ; \LEDR[4]~output_o\ $end
$var wire 1 < \LEDR[3]~output_o\ $end
$var wire 1 = \LEDR[2]~output_o\ $end
$var wire 1 > \LEDR[1]~output_o\ $end
$var wire 1 ? \LEDR[0]~output_o\ $end
$var wire 1 @ \SW[1]~input_o\ $end
$var wire 1 A \SW[0]~input_o\ $end
$var wire 1 B \inst|norOut~0_combout\ $end
$var wire 1 C \inst|nandOut~0_combout\ $end
$var wire 1 D \inst|xorOut~combout\ $end
$var wire 1 E \ALT_INV_SW[0]~input_o\ $end
$var wire 1 F \inst|ALT_INV_nandOut~0_combout\ $end
$var wire 1 G \inst|ALT_INV_norOut~0_combout\ $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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$end
#200000
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#1000000