{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678984391496 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678984391496 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 16 16:33:11 2023 " "Processing started: Thu Mar 16 16:33:11 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678984391496 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984391496 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ALUDemo -c ALUDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off ALUDemo -c ALUDemo" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984391497 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678984391632 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678984391632 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALU4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ALU4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ALU4-Behavioral " "Found design unit 1: ALU4-Behavioral" {  } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 14 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397129 ""} { "Info" "ISGN_ENTITY_NAME" "1 ALU4 " "Found entity 1: ALU4" {  } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 5 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397129 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397129 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ALUDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ALUDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 ALUDemo " "Found entity 1: ALUDemo" {  } { { "ALUDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALUDemo.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397130 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397130 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "ALU4 " "Elaborating entity \"ALU4\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678984397199 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "3 " "Inferred 3 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Mod0\"" {  } { { "ALU4.vhd" "Mod0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 28 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1678984397492 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"Mult0\"" {  } { { "ALU4.vhd" "Mult0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1678984397492 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"Div0\"" {  } { { "ALU4.vhd" "Div0" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 27 -1 0 } }  } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1678984397492 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1678984397492 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Mod0 " "Elaborated megafunction instantiation \"lpm_divide:Mod0\"" {  } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 28 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678984397531 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Mod0 " "Instantiated megafunction \"lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 4 " "Parameter \"LPM_WIDTHN\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397531 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397531 ""}  } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 28 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678984397531 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_i9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_i9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_i9m " "Found entity 1: lpm_divide_i9m" {  } { { "db/lpm_divide_i9m.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_i9m.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397551 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397551 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_7kh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_7kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_7kh " "Found entity 1: sign_div_unsign_7kh" {  } { { "db/sign_div_unsign_7kh.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/sign_div_unsign_7kh.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397553 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397553 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_24f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_24f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_24f " "Found entity 1: alt_u_div_24f" {  } { { "db/alt_u_div_24f.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/alt_u_div_24f.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397555 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397555 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7pc " "Found entity 1: add_sub_7pc" {  } { { "db/add_sub_7pc.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_7pc.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397575 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397575 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8pc " "Found entity 1: add_sub_8pc" {  } { { "db/add_sub_8pc.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/add_sub_8pc.tdf" 23 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397596 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397596 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mult:Mult0 " "Elaborated megafunction instantiation \"lpm_mult:Mult0\"" {  } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678984397622 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mult:Mult0 " "Instantiated megafunction \"lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 4 " "Parameter \"LPM_WIDTHA\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 4 " "Parameter \"LPM_WIDTHB\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 8 " "Parameter \"LPM_WIDTHP\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 8 " "Parameter \"LPM_WIDTHR\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 5 " "Parameter \"MAXIMIZE_SPEED\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397622 ""}  } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678984397622 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_j8t.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_j8t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_j8t " "Found entity 1: mult_j8t" {  } { { "db/mult_j8t.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf" 29 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397642 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397642 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Div0 " "Elaborated megafunction instantiation \"lpm_divide:Div0\"" {  } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 27 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678984397645 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_divide:Div0 " "Instantiated megafunction \"lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 4 " "Parameter \"LPM_WIDTHN\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397645 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397645 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397645 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1678984397645 ""}  } { { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 27 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1678984397645 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_fhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_fhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_fhm " "Found entity 1: lpm_divide_fhm" {  } { { "db/lpm_divide_fhm.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/lpm_divide_fhm.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678984397663 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984397663 ""}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "lpm_mult:Mult0\|mult_j8t:auto_generated\|le5a\[4\] " "Synthesized away node \"lpm_mult:Mult0\|mult_j8t:auto_generated\|le5a\[4\]\"" {  } { { "db/mult_j8t.tdf" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf" 43 6 0 } } { "lpm_mult.tdf" "" { Text "/home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_mult.tdf" 377 4 0 } } { "ALU4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/ALU4.vhd" 21 -1 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1678984397689 "|ALU4|lpm_mult:Mult0|mult_j8t:auto_generated|le5a[4]"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1678984397689 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1678984397689 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "48 " "Ignored 48 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_CARRY_SUM" "4 " "Ignored 4 CARRY_SUM buffer(s)" {  } {  } 0 13016 "Ignored %1!d! CARRY_SUM buffer(s)" 0 0 "Design Software" 0 -1 1678984397817 ""} { "Info" "IMLS_MLS_IGNORED_SOFT" "44 " "Ignored 44 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Design Software" 0 -1 1678984397817 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Analysis & Synthesis" 0 -1 1678984397817 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678984397906 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "lpm_mult:Mult0\|mult_j8t:auto_generated\|le3a\[5\] " "Logic cell \"lpm_mult:Mult0\|mult_j8t:auto_generated\|le3a\[5\]\"" {  } { { "db/mult_j8t.tdf" "le3a\[5\]" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica03/ALUDemo/db/mult_j8t.tdf" 41 6 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1678984398272 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1678984398272 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678984398362 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678984398362 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "117 " "Implemented 117 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Implemented 11 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678984398564 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678984398564 ""} { "Info" "ICUT_CUT_TM_LCELLS" "98 " "Implemented 98 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678984398564 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678984398564 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "439 " "Peak virtual memory: 439 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678984398569 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 16 16:33:18 2023 " "Processing ended: Thu Mar 16 16:33:18 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678984398569 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678984398569 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678984398569 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678984398569 ""}