{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678382513352 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678382513352 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar  9 17:21:53 2023 " "Processing started: Thu Mar  9 17:21:53 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678382513352 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678382513352 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off MuxDemo -c MuxDemo" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678382513352 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678382513490 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678382513490 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux16_1.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Mux16_1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Mux16_1 " "Found entity 1: Mux16_1" {  } { { "Mux16_1.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/Mux16_1.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678382519004 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678382519004 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MuxDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file MuxDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 MuxDemo " "Found entity 1: MuxDemo" {  } { { "MuxDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678382519005 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678382519005 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "MuxDemo " "Elaborating entity \"MuxDemo\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678382519037 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Mux16_1 Mux16_1:inst " "Elaborating entity \"Mux16_1\" for hierarchy \"Mux16_1:inst\"" {  } { { "MuxDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/MuxDemo.bdf" { { 72 488 584 456 "inst" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678382519040 ""}
{ "Warning" "WSGN_SEARCH_FILE" "Mux2_1.bdf 1 1 " "Using design file Mux2_1.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Mux2_1 " "Found entity 1: Mux2_1" {  } { { "Mux2_1.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/Mux2_1.bdf" { } } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678382519043 ""}  } {  } 0 12125 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "Analysis & Synthesis" 0 -1 1678382519043 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Mux2_1 Mux16_1:inst\|Mux2_1:inst14 " "Elaborating entity \"Mux2_1\" for hierarchy \"Mux16_1:inst\|Mux2_1:inst14\"" {  } { { "Mux16_1.bdf" "inst14" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/1semestre/isd/quartus-projects/MuxDemo/Mux16_1.bdf" { { 328 688 784 424 "inst14" "" } } } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678382519043 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678382519976 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678382520229 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678382520229 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "31 " "Implemented 31 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678382520254 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678382520254 ""} { "Info" "ICUT_CUT_TM_LCELLS" "10 " "Implemented 10 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678382520254 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678382520254 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "400 " "Peak virtual memory: 400 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678382520258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar  9 17:22:00 2023 " "Processing ended: Thu Mar  9 17:22:00 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678382520258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678382520258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678382520258 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678382520258 ""}