$comment
	File created using the following command:
		vcd file VHDLDemo.msim.vcd -direction
$end
$date
	Sat Feb 18 15:33:50 2023
$end
$version
	ModelSim Version 2020.1
$end
$timescale
	1ps
$end

$scope module and2gate_vhd_vec_tst $end
$var wire 1 ! inPort0 $end
$var wire 1 " inPort1 $end
$var wire 1 # outPort $end

$scope module i1 $end
$var wire 1 $ gnd $end
$var wire 1 % vcc $end
$var wire 1 & unknown $end
$var wire 1 ' devoe $end
$var wire 1 ( devclrn $end
$var wire 1 ) devpor $end
$var wire 1 * ww_devoe $end
$var wire 1 + ww_devclrn $end
$var wire 1 , ww_devpor $end
$var wire 1 - ww_inPort0 $end
$var wire 1 . ww_inPort1 $end
$var wire 1 / ww_outPort $end
$var wire 1 0 \outPort~output_o\ $end
$var wire 1 1 \inPort0~input_o\ $end
$var wire 1 2 \inPort1~input_o\ $end
$var wire 1 3 \outPort~0_combout\ $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0!
0"
0#
0$
1%
x&
1'
1(
1)
1*
1+
1,
0-
0.
0/
00
01
02
03
$end
#40000
1!
1-
11
#220000
0!
0-
01
#280000
1"
1.
12
#360000
0"
0.
02
#440000
1!
1-
11
#500000
1"
1.
12
13
10
1/
1#
#620000
0"
0.
02
03
00
0/
0#
#660000
0!
0-
01
#720000
1"
1.
12
#780000
1!
1-
11
13
10
1/
1#
#900000
0!
0-
01
03
00
0/
0#
#940000
0"
0.
02
#1000000