|CounterDemo HEX0[0] <= Bin7SegDecoder:hex.decOut_n[0] HEX0[1] <= Bin7SegDecoder:hex.decOut_n[1] HEX0[2] <= Bin7SegDecoder:hex.decOut_n[2] HEX0[3] <= Bin7SegDecoder:hex.decOut_n[3] HEX0[4] <= Bin7SegDecoder:hex.decOut_n[4] HEX0[5] <= Bin7SegDecoder:hex.decOut_n[5] HEX0[6] <= Bin7SegDecoder:hex.decOut_n[6] CLOCK_50 => FreqDivider:inst1.clkIn KEY[1] => inst3.IN0 SW[0] => CounterUpDown4:inst.upDown |CounterDemo|Bin7SegDecoder:hex binInput[0] => Equal0.IN3 binInput[0] => Equal1.IN0 binInput[0] => Equal2.IN3 binInput[0] => Equal3.IN1 binInput[0] => Equal4.IN3 binInput[0] => Equal5.IN1 binInput[0] => Equal6.IN3 binInput[0] => Equal7.IN2 binInput[0] => Equal8.IN3 binInput[0] => Equal9.IN1 binInput[0] => Equal10.IN3 binInput[0] => Equal11.IN2 binInput[0] => Equal12.IN3 binInput[0] => Equal13.IN2 binInput[0] => Equal14.IN3 binInput[1] => Equal0.IN2 binInput[1] => Equal1.IN3 binInput[1] => Equal2.IN0 binInput[1] => Equal3.IN0 binInput[1] => Equal4.IN2 binInput[1] => Equal5.IN3 binInput[1] => Equal6.IN1 binInput[1] => Equal7.IN1 binInput[1] => Equal8.IN2 binInput[1] => Equal9.IN3 binInput[1] => Equal10.IN1 binInput[1] => Equal11.IN1 binInput[1] => Equal12.IN2 binInput[1] => Equal13.IN3 binInput[1] => Equal14.IN2 binInput[2] => Equal0.IN1 binInput[2] => Equal1.IN2 binInput[2] => Equal2.IN2 binInput[2] => Equal3.IN3 binInput[2] => Equal4.IN0 binInput[2] => Equal5.IN0 binInput[2] => Equal6.IN0 binInput[2] => Equal7.IN0 binInput[2] => Equal8.IN1 binInput[2] => Equal9.IN2 binInput[2] => Equal10.IN2 binInput[2] => Equal11.IN3 binInput[2] => Equal12.IN1 binInput[2] => Equal13.IN1 binInput[2] => Equal14.IN1 binInput[3] => Equal0.IN0 binInput[3] => Equal1.IN1 binInput[3] => Equal2.IN1 binInput[3] => Equal3.IN2 binInput[3] => Equal4.IN1 binInput[3] => Equal5.IN2 binInput[3] => Equal6.IN2 binInput[3] => Equal7.IN3 binInput[3] => Equal8.IN0 binInput[3] => Equal9.IN0 binInput[3] => Equal10.IN0 binInput[3] => Equal11.IN0 binInput[3] => Equal12.IN0 binInput[3] => Equal13.IN0 binInput[3] => Equal14.IN0 decOut_n[0] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE decOut_n[1] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE decOut_n[2] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE decOut_n[3] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE decOut_n[4] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE decOut_n[5] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE decOut_n[6] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE |CounterDemo|CounterUpDown4:inst clock => s_count[0].CLK clock => s_count[1].CLK clock => s_count[2].CLK clock => s_count[3].CLK reset => s_count[0].ACLR reset => s_count[1].ACLR reset => s_count[2].ACLR reset => s_count[3].ACLR upDown => s_count.OUTPUTSELECT upDown => s_count.OUTPUTSELECT upDown => s_count.OUTPUTSELECT upDown => s_count.OUTPUTSELECT count[0] <= s_count[0].DB_MAX_OUTPUT_PORT_TYPE count[1] <= s_count[1].DB_MAX_OUTPUT_PORT_TYPE count[2] <= s_count[2].DB_MAX_OUTPUT_PORT_TYPE count[3] <= s_count[3].DB_MAX_OUTPUT_PORT_TYPE |CounterDemo|FreqDivider:inst1 clkIn => s_counter[0].CLK clkIn => s_counter[1].CLK clkIn => s_counter[2].CLK clkIn => s_counter[3].CLK clkIn => s_counter[4].CLK clkIn => s_counter[5].CLK clkIn => s_counter[6].CLK clkIn => s_counter[7].CLK clkIn => s_counter[8].CLK clkIn => s_counter[9].CLK clkIn => s_counter[10].CLK clkIn => s_counter[11].CLK clkIn => s_counter[12].CLK clkIn => s_counter[13].CLK clkIn => s_counter[14].CLK clkIn => s_counter[15].CLK clkIn => s_counter[16].CLK clkIn => s_counter[17].CLK clkIn => s_counter[18].CLK clkIn => s_counter[19].CLK clkIn => s_counter[20].CLK clkIn => s_counter[21].CLK clkIn => s_counter[22].CLK clkIn => s_counter[23].CLK clkIn => s_counter[24].CLK clkIn => s_counter[25].CLK clkIn => s_counter[26].CLK clkIn => s_counter[27].CLK clkIn => s_counter[28].CLK clkIn => s_counter[29].CLK clkIn => s_counter[30].CLK clkIn => s_counter[31].CLK clkIn => clkOut~reg0.CLK clkOut <= clkOut~reg0.DB_MAX_OUTPUT_PORT_TYPE