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296 Commits

Author SHA1 Message Date
TiagoRG 469cc51a11
[POO] removed regex for names 2023-03-21 19:00:48 +00:00
TiagoRG 1adbd66679
[POO] aula06 ex2 added 2023-03-21 18:46:03 +00:00
TiagoRG 17c01703db
[POO] created validations 2023-03-21 13:13:25 +00:00
TiagoRG 1b5f81a875
[POO] aula06 guide added 2023-03-21 10:13:41 +00:00
TiagoRG 5d47ce98fb
[POO] aula06 ex1 added 2023-03-21 10:13:22 +00:00
TiagoRG cdcd19114f
[POO] added DateYMD to utils 2023-03-21 09:58:15 +00:00
TiagoRG 3dfc6b9bcd
[POO] aula05 DateYMD update 2023-03-21 09:54:14 +00:00
TiagoRG d3dccdc72e
[LSD] pratica03 part2 finished (in theory at least 💀) 2023-03-16 16:36:47 +00:00
TiagoRG 5e9f9cd52e
[POO] README update 2023-03-16 15:21:37 +00:00
TiagoRG 303b5c1eef
[LSD] pratica03 part1 fix 2023-03-16 14:49:40 +00:00
TiagoRG b5db4e5e9d
[MD] setup update 2023-03-16 14:48:51 +00:00
TiagoRG e75b9e9712
[MD] logica-1a-ordem added (super incomplete tho 💀) 2023-03-16 14:48:27 +00:00
TiagoRG 21c2c127f2
[POO] aula05 finished 2023-03-14 20:02:31 +00:00
TiagoRG dbb7dba377
[POO] aula05 ex2 added 2023-03-14 10:42:35 +00:00
TiagoRG 77a2672b7b
[POO] aula05 guide update 2023-03-14 10:41:23 +00:00
TiagoRG 0bd456bbc1
[POO] aula05 ex1 added 2023-03-11 17:59:41 +00:00
TiagoRG b4aed4c1e4
[POO] material for aula05 added 2023-03-11 00:24:17 +00:00
TiagoRG a40b632749
[ISD] MuxDemo update 2023-03-09 17:44:51 +00:00
TiagoRG e33fa6e665
[POO/LABI] README.md 2023-03-09 17:44:13 +00:00
TiagoRG 274daab483
[LSD] pratica03 part1 concluded 2023-03-09 17:08:58 +00:00
TiagoRG 924442d473
[LSD] pratica02 parts 1,2,3 concluded 2023-03-09 10:18:38 +00:00
TiagoRG 6c665de0bb
[LABI] tema03 material added 2023-03-08 21:09:05 +00:00
TiagoRG 9c7e38b027
[POO] Created the menu for Shapes.java 2023-03-08 21:01:36 +00:00
TiagoRG c898fde23b
[LSD] DisplayDemo using VHDL finished 2023-03-08 20:58:26 +00:00
TiagoRG 778d02ed50
[LSD] slides for TP04 added 2023-03-08 20:53:22 +00:00
TiagoRG ae62913362
[LSD] DisplayDemo using block diagram finished 2023-03-08 20:52:48 +00:00
TiagoRG 522822d101
[LSD] DisplayDemo using block diagram finished 2023-03-08 20:07:34 +00:00
TiagoRG ed0bce3fcd
[LSD] Mux2_1 finished 2023-03-08 19:52:17 +00:00
TiagoRG a6161c4c88
[POO] Changed from asserts to IllegalArgumentExceptions 2023-03-07 23:28:03 +00:00
TiagoRG 1a9a67ec3c
[LSD] pratica02 part2 added (untested) 2023-03-07 23:07:36 +00:00
TiagoRG 97f66db455
[LSD] Compiled pratica01 part2 2023-03-07 23:07:02 +00:00
TiagoRG b21fbe3205
[LSD] Removed unnecessary master.qsf files 2023-03-07 23:05:32 +00:00
TiagoRG 02f164d691
[LSD] Recreated master.qsf at lsd root 2023-03-07 23:00:18 +00:00
TiagoRG 4f5615bf9c
[LSD] pratica01 part2 block diagram version of NAND2Gate 2023-03-07 21:00:18 +00:00
TiagoRG 3ea15be20e
[LSD] pratica01 part3 simulation waveform created 2023-03-07 20:59:42 +00:00
TiagoRG 7f9314657a
[LSD] pratica01 part4 finished (untested) 2023-03-07 20:59:22 +00:00
TiagoRG 527ccb8a50
[LSD] pratica01 part4 finished 2023-03-07 19:02:31 +00:00
TiagoRG 1ccff15a34
[LSD] Removed master.qsf from lsd root 2023-03-07 18:04:24 +00:00
TiagoRG 590132f8c4
[MD] apontamentos/setup update 2023-03-07 15:58:13 +00:00
TiagoRG a07d28abc7
[MD] apontamentos/setup update 2023-03-07 15:57:06 +00:00
TiagoRG ad3a37f337
[MD] 'Logica de 1ª ordem' initial commit 2023-03-07 15:52:40 +00:00
TiagoRG ad3c0ce8d2
[MD] apontamentos readded 2023-03-07 15:45:49 +00:00
TiagoRG f0450842ce
[POO] README for aula04 added 2023-03-07 13:21:48 +00:00
TiagoRG fda8623e6d
[POO] Removed unnecessary parenthesis 2023-03-07 11:53:37 +00:00
TiagoRG 4d628f539d
[POO] aula04 finished 2023-03-07 11:49:43 +00:00
TiagoRG ec6ffca1f2
[LSD] pratica01 part3 added 2023-03-06 15:31:27 +00:00
TiagoRG 5297ca6829
[POO] aula04 ex3 added 2023-03-06 15:20:46 +00:00
TiagoRG 2f8ec9d8b1
[POO] Shapes.java asserts 2023-03-06 15:20:20 +00:00
TiagoRG 1c74cbb006
[POO] aula04 ex1, ex2 added 2023-03-06 10:25:51 +00:00
TiagoRG 639eeba129
[POO] guide for aula04 added 2023-03-04 20:27:18 +00:00
TiagoRG fec773193a
[POO] aula03 extras added 2023-03-04 20:26:54 +00:00
TiagoRG a6c02e82e0
[POO] UserInput.input() update 2023-03-04 20:25:05 +00:00
TiagoRG e7e71964ea
[1.2:c2] more study material added 2023-03-02 20:38:10 +00:00
TiagoRG 2d08192137
LSD refactor: aulaX to praticaX 2023-03-02 19:08:05 +00:00
TiagoRG 6913c77103
LSD aula02 part1 finished 2023-03-01 12:50:07 +00:00
TiagoRG edcbab25c0
Labi: tema02 material added 2023-03-01 12:22:38 +00:00
TiagoRG 249f4fb0d1
LSD README update 2023-03-01 12:19:44 +00:00
TiagoRG 3959d4c1f2
LSD aula01 slide moved 2023-03-01 12:18:19 +00:00
TiagoRG 651502a8df
LSD: aula01 part2 finished 2023-03-01 12:17:08 +00:00
TiagoRG e70760a978
LSD: aula01 part1 finished 2023-03-01 12:13:35 +00:00
TiagoRG 317d91f0e9
Removed stream ciphers 2023-02-28 18:40:23 +00:00
TiagoRG 7cea1f379e
AES cipher done (working for now at least) 2023-02-28 18:36:12 +00:00
TiagoRG 70d6b50b4b
MD material added 2023-02-28 15:56:04 +00:00
TiagoRG 90f9d373b3
C2 material added 2023-02-28 15:54:26 +00:00
TiagoRG 9ec002e29d
Created a new version for grades to be random 2023-02-27 17:41:01 +00:00
TiagoRG d07c95409e
POO TP3 added 2023-02-27 16:08:45 +00:00
TiagoRG 5c5752c890
Refactored to utils method 2023-02-26 16:49:59 +00:00
TiagoRG eb84595809
Converted the switch case to an array 2023-02-26 14:03:12 +00:00
TiagoRG 006a7e3a22
Converted to double 2023-02-25 19:22:53 +00:00
TiagoRG 3cd0a089ac
LSD material for aula02 and aula03 2023-02-25 17:54:37 +00:00
TiagoRG b2d73e9775
Moved isNumPrime to MathTools and made Student static 2023-02-25 17:53:42 +00:00
TiagoRG 4ccbd6855b
Removed project config 2023-02-25 16:13:07 +00:00
TiagoRG d2a4a91520
Switch from 'while' loop to 'do..while' 2023-02-25 15:27:14 +00:00
TiagoRG 9abee3f273
POO aula03 finished 2023-02-25 15:26:39 +00:00
TiagoRG e8ad075602
POO: aula03 ex1-3 added 2023-02-25 12:18:54 +00:00
TiagoRG b2074d9a73
LSD slides added 2023-02-25 11:46:28 +00:00
TiagoRG 42a708feb3
README update 2023-02-25 11:43:18 +00:00
TiagoRG e9cf7af65d
FP: isPrime update 2023-02-25 11:41:27 +00:00
TiagoRG bd1271c3d3
Removed datafiles;out 2023-02-25 11:39:54 +00:00
TiagoRG d50af5dd27
POO material added 2023-02-24 21:49:24 +00:00
TiagoRG 66d43cfa2c
MD avaliacoes material 2023-02-23 15:58:20 +00:00
TiagoRG 6585c4deb9
Screw this 2023-02-23 15:20:45 +00:00
TiagoRG 88124f1294
Quick fix cuz me be dumb 💀 2023-02-21 23:45:07 +00:00
TiagoRG cb16f172d4
README update 2023-02-21 23:44:25 +00:00
TiagoRG 4d23ebbdc1
LSD aula01 initial commit, base VHDL files, to be finished along the hardware 2023-02-20 22:37:38 +00:00
TiagoRG cef84de042
POO dates format 2023-02-20 22:33:02 +00:00
TiagoRG d167f7bb9a
Added new lines to the end of execution 2023-02-20 14:25:36 +00:00
TiagoRG b1e7352bfc
Added references to utils package on aula02 classes 2023-02-20 14:20:27 +00:00
TiagoRG f533593adc
Moved Python-Java-Comparison.pdf to slides 2023-02-20 14:17:23 +00:00
TiagoRG 3a8fb8d317
README update 2023-02-20 13:47:57 +00:00
TiagoRG 7ccf231244
POO tp_codecheck finished 2023-02-20 13:45:49 +00:00
TiagoRG 05a04d0717
POO tp_codecheck added 2023-02-20 12:03:10 +00:00
TiagoRG 21e5176c03
Floats reformat 2023-02-20 10:14:11 +00:00
TiagoRG 8987a4afde
More study material 2023-02-18 20:47:21 +00:00
TiagoRG 6a8e7a786d
Python-like input method and README update 2023-02-18 20:46:55 +00:00
TiagoRG 114305d602
FPGA master.qsf config file added 2023-02-18 16:06:47 +00:00
TiagoRG 21e4106f57
README update 2023-02-18 16:05:13 +00:00
TiagoRG 76aa0c9336
LABI: tema01 added 2023-02-18 14:35:57 +00:00
TiagoRG 8c970f94a4
README update 2023-02-18 14:16:30 +00:00
TiagoRG aaab8cf288
POO output directory added 2023-02-18 14:10:38 +00:00