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[LSD] changed the timer value

This commit is contained in:
TiagoRG 2023-03-28 15:25:43 +01:00
parent 613a3e6adb
commit fe6d5d17bb
Signed by untrusted user who does not match committer: TiagoRG
GPG Key ID: DFCD48E3F420DB42
61 changed files with 1902 additions and 1936 deletions
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1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd
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@ -13,7 +13,7 @@ architecture Behavioral of FreqDivider is
signal s_halfWay : unsigned(31 downto 0);
signal k : std_logic_vector(31 downto 0);
begin
k <= x"01AD7840";
k <= x"02AD7840";
s_halfWay <= unsigned(k);
process(clkIn)

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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679489466896 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1680013329245 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1680013330690 ""}
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@ -1,3 +1,3 @@
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Wed Mar 22 12:53:16 2023
Creation_Time = Tue Mar 28 15:21:18 2023

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@ -1,6 +1,6 @@
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679489470445 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 12:51:10 2023 " "Processing started: Wed Mar 22 12:51:10 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679489470445 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679489470445 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679489470445 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1679489470596 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "AccN_Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/ simulation " "Generated file AccN_Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1679489470629 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679489470641 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 12:51:10 2023 " "Processing ended: Wed Mar 22 12:51:10 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679489470641 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679489470641 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679489470641 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1679489470641 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013333031 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013333031 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:22:12 2023 " "Processing started: Tue Mar 28 15:22:12 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013333031 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1680013333031 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1680013333031 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1680013333182 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "AccN_Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/ simulation " "Generated file AccN_Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1680013333223 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013333233 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:22:13 2023 " "Processing ended: Tue Mar 28 15:22:13 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013333233 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013333233 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013333233 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1680013333233 ""}

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@ -1,19 +1,19 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679489452339 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679489452339 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 12:50:52 2023 " "Processing started: Wed Mar 22 12:50:52 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679489452339 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489452339 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489452339 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679489452467 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679489452467 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FreqDivider.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FreqDivider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FreqDivider-Behavioral " "Found design unit 1: FreqDivider-Behavioral" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457065 ""} { "Info" "ISGN_ENTITY_NAME" "1 FreqDivider " "Found entity 1: FreqDivider" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457065 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457065 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AccN_Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file AccN_Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AccN_Demo " "Found entity 1: AccN_Demo" { } { { "AccN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457065 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457065 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AccN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AccN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AccN-Behavioral " "Found design unit 1: AccN-Behavioral" { } { { "AccN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457065 ""} { "Info" "ISGN_ENTITY_NAME" "1 AccN " "Found entity 1: AccN" { } { { "AccN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457065 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457065 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RegN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file RegN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RegN-Behavioral " "Found design unit 1: RegN-Behavioral" { } { { "RegN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457066 ""} { "Info" "ISGN_ENTITY_NAME" "1 RegN " "Found entity 1: RegN" { } { { "RegN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457066 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AdderN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AdderN-Behavioral " "Found design unit 1: AdderN-Behavioral" { } { { "AdderN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457066 ""} { "Info" "ISGN_ENTITY_NAME" "1 AdderN " "Found entity 1: AdderN" { } { { "AdderN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457066 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "AccN_Demo " "Elaborating entity \"AccN_Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679489457092 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AccN AccN:inst " "Elaborating entity \"AccN\" for hierarchy \"AccN:inst\"" { } { { "AccN_Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 216 512 720 328 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679489457095 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AdderN AccN:inst\|AdderN:adder A:behavioral " "Elaborating entity \"AdderN\" using architecture \"A:behavioral\" for hierarchy \"AccN:inst\|AdderN:adder\"" { } { { "AccN.vhd" "adder" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 18 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679489457096 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "RegN AccN:inst\|RegN:reg A:behavioral " "Elaborating entity \"RegN\" using architecture \"A:behavioral\" for hierarchy \"AccN:inst\|RegN:reg\"" { } { { "AccN.vhd" "reg" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 27 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679489457096 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FreqDivider FreqDivider:inst2 " "Elaborating entity \"FreqDivider\" for hierarchy \"FreqDivider:inst2\"" { } { { "AccN_Demo.bdf" "inst2" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 288 304 448 368 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679489457097 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1679489457435 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1679489457750 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679489457750 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "114 " "Implemented 114 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679489457767 ""} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Implemented 17 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679489457767 ""} { "Info" "ICUT_CUT_TM_LCELLS" "77 " "Implemented 77 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679489457767 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679489457767 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "456 " "Peak virtual memory: 456 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679489457770 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 12:50:57 2023 " "Processing ended: Wed Mar 22 12:50:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679489457770 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679489457770 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679489457770 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457770 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013313781 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013313781 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:21:53 2023 " "Processing started: Tue Mar 28 15:21:53 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013313781 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013313781 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013313781 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1680013313918 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1680013313918 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FreqDivider.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FreqDivider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FreqDivider-Behavioral " "Found design unit 1: FreqDivider-Behavioral" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318577 ""} { "Info" "ISGN_ENTITY_NAME" "1 FreqDivider " "Found entity 1: FreqDivider" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318577 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318577 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AccN_Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file AccN_Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AccN_Demo " "Found entity 1: AccN_Demo" { } { { "AccN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AccN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AccN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AccN-Behavioral " "Found design unit 1: AccN-Behavioral" { } { { "AccN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} { "Info" "ISGN_ENTITY_NAME" "1 AccN " "Found entity 1: AccN" { } { { "AccN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RegN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file RegN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RegN-Behavioral " "Found design unit 1: RegN-Behavioral" { } { { "RegN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} { "Info" "ISGN_ENTITY_NAME" "1 RegN " "Found entity 1: RegN" { } { { "RegN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AdderN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AdderN-Behavioral " "Found design unit 1: AdderN-Behavioral" { } { { "AdderN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} { "Info" "ISGN_ENTITY_NAME" "1 AdderN " "Found entity 1: AdderN" { } { { "AdderN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "AccN_Demo " "Elaborating entity \"AccN_Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1680013318605 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AccN AccN:inst " "Elaborating entity \"AccN\" for hierarchy \"AccN:inst\"" { } { { "AccN_Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 216 512 720 328 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318607 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AdderN AccN:inst\|AdderN:adder A:behavioral " "Elaborating entity \"AdderN\" using architecture \"A:behavioral\" for hierarchy \"AccN:inst\|AdderN:adder\"" { } { { "AccN.vhd" "adder" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 18 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318608 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "RegN AccN:inst\|RegN:reg A:behavioral " "Elaborating entity \"RegN\" using architecture \"A:behavioral\" for hierarchy \"AccN:inst\|RegN:reg\"" { } { { "AccN.vhd" "reg" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 27 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318608 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FreqDivider FreqDivider:inst2 " "Elaborating entity \"FreqDivider\" for hierarchy \"FreqDivider:inst2\"" { } { { "AccN_Demo.bdf" "inst2" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 288 304 448 368 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318609 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1680013318992 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1680013319320 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013319320 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "112 " "Implemented 112 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1680013319375 ""} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Implemented 17 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1680013319375 ""} { "Info" "ICUT_CUT_TM_LCELLS" "75 " "Implemented 75 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1680013319375 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1680013319375 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "453 " "Peak virtual memory: 453 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013319378 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:21:59 2023 " "Processing ended: Tue Mar 28 15:21:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013319378 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013319378 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013319378 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013319378 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679489469028 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679489469028 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 12:51:08 2023 " "Processing started: Wed Mar 22 12:51:08 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679489469028 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469028 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta AccN_Demo -c AccN_Demo " "Command: quartus_sta AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469028 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679489469048 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679489469105 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679489469105 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469147 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469147 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AccN_Demo.sdc " "Synopsys Design Constraints File file not found: 'AccN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1679489469438 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469439 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name FreqDivider:inst2\|clkOut FreqDivider:inst2\|clkOut " "create_clock -period 1.000 -name FreqDivider:inst2\|clkOut FreqDivider:inst2\|clkOut" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1679489469439 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1679489469439 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469439 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469440 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469440 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679489469440 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1679489469443 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679489469449 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679489469449 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.190 " "Worst-case setup slack is -4.190" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.190 -78.512 CLOCK_50 " " -4.190 -78.512 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.348 -17.156 FreqDivider:inst2\|clkOut " " -1.348 -17.156 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469450 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.548 " "Worst-case hold slack is 0.548" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.548 0.000 FreqDivider:inst2\|clkOut " " 0.548 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.654 0.000 CLOCK_50 " " 0.654 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469450 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469451 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469451 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469452 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469452 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469452 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -21.845 FreqDivider:inst2\|clkOut " " -1.285 -21.845 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469452 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469452 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679489469467 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679489469479 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679489469637 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469651 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679489469653 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679489469653 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.751 " "Worst-case setup slack is -3.751" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.751 -67.496 CLOCK_50 " " -3.751 -67.496 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.082 -13.558 FreqDivider:inst2\|clkOut " " -1.082 -13.558 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469654 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469654 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.494 " "Worst-case hold slack is 0.494" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.494 0.000 FreqDivider:inst2\|clkOut " " 0.494 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.597 0.000 CLOCK_50 " " 0.597 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469655 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469655 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469656 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469657 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -21.845 FreqDivider:inst2\|clkOut " " -1.285 -21.845 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469658 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469658 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679489469674 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469714 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679489469714 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679489469714 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.596 " "Worst-case setup slack is -1.596" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469716 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469716 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.596 -21.945 CLOCK_50 " " -1.596 -21.945 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469716 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.171 -0.699 FreqDivider:inst2\|clkOut " " -0.171 -0.699 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469716 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469716 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.247 " "Worst-case hold slack is 0.247" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469718 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469718 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.247 0.000 FreqDivider:inst2\|clkOut " " 0.247 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469718 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 CLOCK_50 " " 0.298 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469718 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469718 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469719 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469720 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.002 CLOCK_50 " " -3.000 -38.002 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -17.000 FreqDivider:inst2\|clkOut " " -1.000 -17.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469722 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679489469957 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679489469957 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "537 " "Peak virtual memory: 537 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679489469981 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 12:51:09 2023 " "Processing ended: Wed Mar 22 12:51:09 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679489469981 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679489469981 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679489469981 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679489469981 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013331463 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013331463 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:22:11 2023 " "Processing started: Tue Mar 28 15:22:11 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013331463 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331463 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta AccN_Demo -c AccN_Demo " "Command: quartus_sta AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331463 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1680013331484 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1680013331541 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1680013331541 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331582 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331582 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AccN_Demo.sdc " "Synopsys Design Constraints File file not found: 'AccN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1680013331871 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331871 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name FreqDivider:inst2\|clkOut FreqDivider:inst2\|clkOut " "create_clock -period 1.000 -name FreqDivider:inst2\|clkOut FreqDivider:inst2\|clkOut" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1680013331871 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1680013331871 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331871 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331872 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331872 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1680013331873 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1680013331876 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1680013331883 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1680013331883 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.308 " "Worst-case setup slack is -4.308" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.308 -65.920 CLOCK_50 " " -4.308 -65.920 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.349 -16.351 FreqDivider:inst2\|clkOut " " -1.349 -16.351 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331883 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.543 " "Worst-case hold slack is 0.543" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.543 0.000 FreqDivider:inst2\|clkOut " " 0.543 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.653 0.000 CLOCK_50 " " 0.653 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331884 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013331885 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013331885 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -21.845 FreqDivider:inst2\|clkOut " " -1.285 -21.845 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331885 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1680013331901 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1680013331913 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1680013332202 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013332217 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1680013332219 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1680013332219 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.850 " "Worst-case setup slack is -3.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.850 -55.792 CLOCK_50 " " -3.850 -55.792 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.081 -12.785 FreqDivider:inst2\|clkOut " " -1.081 -12.785 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332220 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.489 " "Worst-case hold slack is 0.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.489 0.000 FreqDivider:inst2\|clkOut " " 0.489 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.598 0.000 CLOCK_50 " " 0.598 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332221 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332223 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332224 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -21.845 FreqDivider:inst2\|clkOut " " -1.285 -21.845 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332225 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1680013332250 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013332290 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1680013332290 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1680013332290 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.676 " "Worst-case setup slack is -1.676" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.676 -16.763 CLOCK_50 " " -1.676 -16.763 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.170 -0.504 FreqDivider:inst2\|clkOut " " -0.170 -0.504 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332292 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.244 " "Worst-case hold slack is 0.244" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.244 0.000 FreqDivider:inst2\|clkOut " " 0.244 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.297 0.000 CLOCK_50 " " 0.297 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332294 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332295 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332296 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.036 CLOCK_50 " " -3.000 -38.036 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -17.000 FreqDivider:inst2\|clkOut " " -1.000 -17.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332298 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1680013332526 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1680013332526 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "537 " "Peak virtual memory: 537 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013332549 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:22:12 2023 " "Processing ended: Tue Mar 28 15:22:12 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013332549 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013332549 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013332549 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1680013332549 ""}

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11
1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tmw_info
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@ -1,4 +1,7 @@
start_full_compilation:s
start_assembler:s-start_full_compilation
start_timing_analyzer:s-start_full_compilation
start_eda_netlist_writer:s-start_full_compilation
start_full_compilation:s:00:00:20
start_analysis_synthesis:s:00:00:06-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:09-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:02-start_full_compilation
start_eda_netlist_writer:s:00:00:01-start_full_compilation

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14
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for AccN_Demo
Wed Mar 22 12:51:08 2023
Tue Mar 28 15:22:10 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Mar 22 12:51:08 2023 ;
; Assembler Status ; Successful - Tue Mar 28 15:22:10 2023 ;
; Revision Name ; AccN_Demo ;
; Top-level Entity Name ; AccN_Demo ;
; Family ; Cyclone IV E ;
@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
+----------------+------------------------+
; Option ; Setting ;
+----------------+------------------------+
; JTAG usercode ; 0x0056F0F9 ;
; Checksum ; 0x0056F0F9 ;
; JTAG usercode ; 0x0056E597 ;
; Checksum ; 0x0056E597 ;
+----------------+------------------------+
@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula.
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Wed Mar 22 12:51:06 2023
Info: Processing started: Tue Mar 28 15:22:09 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 367 megabytes
Info: Processing ended: Wed Mar 22 12:51:08 2023
Info: Elapsed time: 00:00:02
Info: Processing ended: Tue Mar 28 15:22:10 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:02

2
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.done
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@ -1 +1 @@
Wed Mar 22 12:51:10 2023
Tue Mar 28 15:22:13 2023

10
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.eda.rpt
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@ -1,5 +1,5 @@
EDA Netlist Writer report for AccN_Demo
Wed Mar 22 12:51:10 2023
Tue Mar 28 15:22:13 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Mar 22 12:51:10 2023 ;
; EDA Netlist Writer Status ; Successful - Tue Mar 28 15:22:13 2023 ;
; Revision Name ; AccN_Demo ;
; Top-level Entity Name ; AccN_Demo ;
; Family ; Cyclone IV E ;
@ -81,14 +81,14 @@ https://fpgasoftware.intel.com/eula.
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Wed Mar 22 12:51:10 2023
Info: Processing started: Tue Mar 28 15:22:12 2023
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file AccN_Demo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 612 megabytes
Info: Processing ended: Wed Mar 22 12:51:10 2023
Info: Elapsed time: 00:00:00
Info: Processing ended: Tue Mar 28 15:22:13 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00

198
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.rpt
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@ -1,5 +1,5 @@
Fitter report for AccN_Demo
Wed Mar 22 12:51:06 2023
Tue Mar 28 15:22:08 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -69,15 +69,15 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+---------------------------------------------+
; Fitter Status ; Successful - Wed Mar 22 12:51:06 2023 ;
; Fitter Status ; Successful - Tue Mar 28 15:22:08 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; AccN_Demo ;
; Top-level Entity Name ; AccN_Demo ;
; Family ; Cyclone IV E ;
; Device ; EP4CE115F29C7 ;
; Timing Models ; Final ;
; Total logic elements ; 78 / 114,480 ( < 1 % ) ;
; Total combinational functions ; 77 / 114,480 ( < 1 % ) ;
; Total logic elements ; 76 / 114,480 ( < 1 % ) ;
; Total combinational functions ; 75 / 114,480 ( < 1 % ) ;
; Dedicated logic registers ; 50 / 114,480 ( < 1 % ) ;
; Total registers ; 50 ;
; Total pins ; 37 / 529 ( 7 % ) ;
@ -662,8 +662,8 @@ https://fpgasoftware.intel.com/eula.
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+--------------------+----------------------------+--------------------------+
; Placement (by node) ; ; ; ;
; -- Requested ; 0.00 % ( 0 / 214 ) ; 0.00 % ( 0 / 214 ) ; 0.00 % ( 0 / 214 ) ;
; -- Achieved ; 0.00 % ( 0 / 214 ) ; 0.00 % ( 0 / 214 ) ; 0.00 % ( 0 / 214 ) ;
; -- Requested ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ;
; -- Achieved ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ;
; ; ; ; ;
; Routing (by net) ; ; ; ;
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
@ -686,7 +686,7 @@ https://fpgasoftware.intel.com/eula.
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Top ; 0.00 % ( 0 / 204 ) ; N/A ; Source File ; N/A ; ;
; Top ; 0.00 % ( 0 / 202 ) ; N/A ; Source File ; N/A ; ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
@ -702,19 +702,19 @@ The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre
+---------------------------------------------+------------------------+
; Resource ; Usage ;
+---------------------------------------------+------------------------+
; Total logic elements ; 78 / 114,480 ( < 1 % ) ;
; -- Combinational with no register ; 28 ;
; Total logic elements ; 76 / 114,480 ( < 1 % ) ;
; -- Combinational with no register ; 26 ;
; -- Register only ; 1 ;
; -- Combinational with a register ; 49 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 12 ;
; -- 3 input functions ; 21 ;
; -- <=2 input functions ; 44 ;
; -- 4 input functions ; 15 ;
; -- 3 input functions ; 27 ;
; -- <=2 input functions ; 33 ;
; -- Register only ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 30 ;
; -- normal mode ; 28 ;
; -- arithmetic mode ; 47 ;
; ; ;
; Total registers* ; 50 / 117,053 ( < 1 % ) ;
@ -743,8 +743,8 @@ The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre
; Peak interconnect usage (total/H/V) ; 1.2% / 0.9% / 1.7% ;
; Maximum fan-out ; 33 ;
; Highest non-global fan-out ; 17 ;
; Total fan-out ; 394 ;
; Average fan-out ; 1.84 ;
; Total fan-out ; 401 ;
; Average fan-out ; 1.90 ;
+---------------------------------------------+------------------------+
* Register count does not include registers inside RAM blocks or DSP blocks.
@ -757,19 +757,19 @@ The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre
+---------------------------------------------+-----------------------+--------------------------------+
; Difficulty Clustering Region ; Low ; Low ;
; ; ; ;
; Total logic elements ; 78 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
; -- Combinational with no register ; 28 ; 0 ;
; Total logic elements ; 76 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ;
; -- Combinational with no register ; 26 ; 0 ;
; -- Register only ; 1 ; 0 ;
; -- Combinational with a register ; 49 ; 0 ;
; ; ; ;
; Logic element usage by number of LUT inputs ; ; ;
; -- 4 input functions ; 12 ; 0 ;
; -- 3 input functions ; 21 ; 0 ;
; -- <=2 input functions ; 44 ; 0 ;
; -- 4 input functions ; 15 ; 0 ;
; -- 3 input functions ; 27 ; 0 ;
; -- <=2 input functions ; 33 ; 0 ;
; -- Register only ; 1 ; 0 ;
; ; ; ;
; Logic elements by mode ; ; ;
; -- normal mode ; 30 ; 0 ;
; -- normal mode ; 28 ; 0 ;
; -- arithmetic mode ; 47 ; 0 ;
; ; ; ;
; Total registers ; 50 ; 0 ;
@ -792,8 +792,8 @@ The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
; -- Total Connections ; 389 ; 5 ;
; -- Registered Connections ; 112 ; 0 ;
; -- Total Connections ; 396 ; 5 ;
; -- Registered Connections ; 113 ; 0 ;
; ; ; ;
; External Connections ; ; ;
; -- Top ; 0 ; 0 ;
@ -1749,10 +1749,10 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------+-------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------+-------------+--------------+
; |AccN_Demo ; 78 (0) ; 50 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; 28 (0) ; 1 (0) ; 49 (0) ; |AccN_Demo ; AccN_Demo ; work ;
; |AccN_Demo ; 76 (0) ; 50 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; 26 (0) ; 1 (0) ; 49 (0) ; |AccN_Demo ; AccN_Demo ; work ;
; |AccN:inst| ; 17 (0) ; 17 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 17 (0) ; |AccN_Demo|AccN:inst ; AccN ; work ;
; |RegN:reg| ; 17 (17) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 17 (17) ; |AccN_Demo|AccN:inst|RegN:reg ; RegN ; work ;
; |FreqDivider:inst2| ; 61 (61) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 1 (1) ; 32 (32) ; |AccN_Demo|FreqDivider:inst2 ; FreqDivider ; work ;
; |FreqDivider:inst2| ; 59 (59) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 (26) ; 1 (1) ; 32 (32) ; |AccN_Demo|FreqDivider:inst2 ; FreqDivider ; work ;
+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -1881,48 +1881,48 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------------------+-------------------+---------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+--------------------------+---------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+--------------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+--------------------------+---------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+--------------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+
; CLOCK_50 ; PIN_Y2 ; 33 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ;
; FreqDivider:inst2|clkOut ; FF_X23_Y36_N3 ; 17 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ;
; FreqDivider:inst2|clkOut ; FF_X56_Y71_N23 ; 17 ; Clock ; yes ; Global Clock ; GCLK12 ; -- ;
; KEY[1] ; PIN_M21 ; 17 ; Async. clear ; no ; -- ; -- ; -- ;
; SW[17] ; PIN_Y23 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
+--------------------------+---------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+--------------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals ;
+--------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+--------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+--------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; CLOCK_50 ; PIN_Y2 ; 33 ; 1 ; Global Clock ; GCLK4 ; -- ;
; FreqDivider:inst2|clkOut ; FF_X23_Y36_N3 ; 17 ; 7 ; Global Clock ; GCLK0 ; -- ;
+--------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+--------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
; CLOCK_50 ; PIN_Y2 ; 33 ; 0 ; Global Clock ; GCLK4 ; -- ;
; FreqDivider:inst2|clkOut ; FF_X56_Y71_N23 ; 17 ; 9 ; Global Clock ; GCLK12 ; -- ;
+--------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+------------------------------------------------+
+-------------------------------------------------+
; Routing Usage Summary ;
+-----------------------+------------------------+
+-----------------------+-------------------------+
; Routing Resource Type ; Usage ;
+-----------------------+------------------------+
; Block interconnects ; 92 / 342,891 ( < 1 % ) ;
; C16 interconnects ; 66 / 10,120 ( < 1 % ) ;
; C4 interconnects ; 99 / 209,544 ( < 1 % ) ;
; Direct links ; 27 / 342,891 ( < 1 % ) ;
+-----------------------+-------------------------+
; Block interconnects ; 89 / 342,891 ( < 1 % ) ;
; C16 interconnects ; 65 / 10,120 ( < 1 % ) ;
; C4 interconnects ; 104 / 209,544 ( < 1 % ) ;
; Direct links ; 29 / 342,891 ( < 1 % ) ;
; Global clocks ; 2 / 20 ( 10 % ) ;
; Local interconnects ; 62 / 119,088 ( < 1 % ) ;
; R24 interconnects ; 42 / 9,963 ( < 1 % ) ;
; R4 interconnects ; 94 / 289,782 ( < 1 % ) ;
+-----------------------+------------------------+
; Local interconnects ; 61 / 119,088 ( < 1 % ) ;
; R24 interconnects ; 40 / 9,963 ( < 1 % ) ;
; R4 interconnects ; 92 / 289,782 ( < 1 % ) ;
+-----------------------+-------------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+---------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 13.00) ; Number of LABs (Total = 6) ;
; Number of Logic Elements (Average = 12.67) ; Number of LABs (Total = 6) ;
+---------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
@ -1934,12 +1934,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 1 ;
; 15 ; 1 ;
; 16 ; 2 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 3 ;
+---------------------------------------------+-----------------------------+
@ -1957,7 +1957,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 21.33) ; Number of LABs (Total = 6) ;
; Number of Signals Sourced (Average = 20.83) ; Number of LABs (Total = 6) ;
+----------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@ -1975,10 +1975,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
; 16 ; 2 ;
; 17 ; 0 ;
; 18 ; 1 ;
; 19 ; 1 ;
; 19 ; 0 ;
; 20 ; 0 ;
; 21 ; 0 ;
; 22 ; 1 ;
@ -1993,7 +1993,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+--------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 10.83) ; Number of LABs (Total = 6) ;
; Number of Signals Sourced Out (Average = 10.50) ; Number of LABs (Total = 6) ;
+--------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@ -2001,9 +2001,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 0 ;
@ -2018,7 +2018,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 12.67) ; Number of LABs (Total = 6) ;
; Number of Distinct Inputs (Average = 12.33) ; Number of LABs (Total = 6) ;
+----------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@ -2035,9 +2035,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 12 ; 0 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 15 ; 1 ;
; 16 ; 0 ;
; 17 ; 1 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 0 ;
; 20 ; 0 ;
@ -2198,39 +2198,39 @@ This will disable optimization of problematic paths and expose them for further
+---------------------------------+--------------------------+-------------------+
; Source Register ; Destination Register ; Delay Added in ns ;
+---------------------------------+--------------------------+-------------------+
; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 4.200 ;
; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; 1.751 ;
; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 4.173 ;
; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; 1.574 ;
; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; 1.574 ;
+---------------------------------+--------------------------+-------------------+
Note: This table only shows the top 33 path(s) that have the largest delay added for hold.
@ -2765,7 +2765,7 @@ Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
Info (170192): Fitter placement operations ending: elapsed time is 00:00:03
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48
@ -2777,13 +2777,13 @@ Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 488 warnings
Info: Peak virtual memory: 1158 megabytes
Info: Processing ended: Wed Mar 22 12:51:06 2023
Info: Elapsed time: 00:00:08
Info: Peak virtual memory: 1160 megabytes
Info: Processing ended: Tue Mar 28 15:22:08 2023
Info: Elapsed time: 00:00:09
Info: Total CPU time (on all processors): 00:00:14

6
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.summary
View File

@ -1,12 +1,12 @@
Fitter Status : Successful - Wed Mar 22 12:51:06 2023
Fitter Status : Successful - Tue Mar 28 15:22:08 2023
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : AccN_Demo
Top-level Entity Name : AccN_Demo
Family : Cyclone IV E
Device : EP4CE115F29C7
Timing Models : Final
Total logic elements : 78 / 114,480 ( < 1 % )
Total combinational functions : 77 / 114,480 ( < 1 % )
Total logic elements : 76 / 114,480 ( < 1 % )
Total combinational functions : 75 / 114,480 ( < 1 % )
Dedicated logic registers : 50 / 114,480 ( < 1 % )
Total registers : 50
Total pins : 37 / 529 ( 7 % )

22
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.flow.rpt
View File

@ -1,5 +1,5 @@
Flow report for AccN_Demo
Wed Mar 22 12:51:10 2023
Tue Mar 28 15:22:13 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -41,15 +41,15 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Wed Mar 22 12:51:10 2023 ;
; Flow Status ; Successful - Tue Mar 28 15:22:13 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; AccN_Demo ;
; Top-level Entity Name ; AccN_Demo ;
; Family ; Cyclone IV E ;
; Device ; EP4CE115F29C7 ;
; Timing Models ; Final ;
; Total logic elements ; 78 / 114,480 ( < 1 % ) ;
; Total combinational functions ; 77 / 114,480 ( < 1 % ) ;
; Total logic elements ; 76 / 114,480 ( < 1 % ) ;
; Total combinational functions ; 75 / 114,480 ( < 1 % ) ;
; Dedicated logic registers ; 50 / 114,480 ( < 1 % ) ;
; Total registers ; 50 ;
; Total pins ; 37 / 529 ( 7 % ) ;
@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 03/22/2023 12:50:52 ;
; Start date & time ; 03/28/2023 15:21:53 ;
; Main task ; Compilation ;
; Revision Name ; AccN_Demo ;
+-------------------+---------------------+
@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 198516037997543.167948945207130 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 198516037997543.168001331303800 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@ -101,12 +101,12 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 451 MB ; 00:00:13 ;
; Fitter ; 00:00:08 ; 1.0 ; 1158 MB ; 00:00:13 ;
; Assembler ; 00:00:02 ; 1.0 ; 367 MB ; 00:00:02 ;
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 447 MB ; 00:00:13 ;
; Fitter ; 00:00:09 ; 1.0 ; 1160 MB ; 00:00:14 ;
; Assembler ; 00:00:01 ; 1.0 ; 367 MB ; 00:00:02 ;
; Timing Analyzer ; 00:00:01 ; 1.0 ; 537 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:00 ;
; Total ; 00:00:16 ; -- ; -- ; 00:00:29 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:00 ;
; Total ; 00:00:18 ; -- ; -- ; 00:00:30 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+

54
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for AccN_Demo
Wed Mar 22 12:50:57 2023
Tue Mar 28 15:21:59 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -46,13 +46,13 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 22 12:50:57 2023 ;
; Analysis & Synthesis Status ; Successful - Tue Mar 28 15:21:59 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; AccN_Demo ;
; Top-level Entity Name ; AccN_Demo ;
; Family ; Cyclone IV E ;
; Total logic elements ; 77 ;
; Total combinational functions ; 77 ;
; Total logic elements ; 75 ;
; Total combinational functions ; 75 ;
; Dedicated logic registers ; 50 ;
; Total registers ; 50 ;
; Total pins ; 37 ;
@ -185,16 +185,16 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimated Total logic elements ; 77 ;
; Estimated Total logic elements ; 75 ;
; ; ;
; Total combinational functions ; 77 ;
; Total combinational functions ; 75 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 12 ;
; -- 3 input functions ; 21 ;
; -- <=2 input functions ; 44 ;
; -- 4 input functions ; 15 ;
; -- 3 input functions ; 27 ;
; -- <=2 input functions ; 33 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 30 ;
; -- normal mode ; 28 ;
; -- arithmetic mode ; 47 ;
; ; ;
; Total registers ; 50 ;
@ -207,8 +207,8 @@ https://fpgasoftware.intel.com/eula.
; ; ;
; Maximum fan-out node ; CLOCK_50~input ;
; Maximum fan-out ; 33 ;
; Total fan-out ; 386 ;
; Average fan-out ; 1.92 ;
; Total fan-out ; 394 ;
; Average fan-out ; 1.98 ;
+---------------------------------------------+----------------+
@ -217,10 +217,10 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+-------------+--------------+
; |AccN_Demo ; 77 (0) ; 50 (0) ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; |AccN_Demo ; AccN_Demo ; work ;
; |AccN_Demo ; 75 (0) ; 50 (0) ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; |AccN_Demo ; AccN_Demo ; work ;
; |AccN:inst| ; 17 (0) ; 17 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|AccN:inst ; AccN ; work ;
; |RegN:reg| ; 17 (17) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|AccN:inst|RegN:reg ; RegN ; work ;
; |FreqDivider:inst2| ; 60 (60) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|FreqDivider:inst2 ; FreqDivider ; work ;
; |FreqDivider:inst2| ; 58 (58) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|FreqDivider:inst2 ; FreqDivider ; work ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -279,18 +279,18 @@ Note: In order to hide this table in the UI and the text report file, please set
; cycloneiii_ff ; 50 ;
; ENA CLR ; 17 ;
; plain ; 33 ;
; cycloneiii_lcell_comb ; 77 ;
; cycloneiii_lcell_comb ; 75 ;
; arith ; 47 ;
; 2 data inputs ; 31 ;
; 3 data inputs ; 16 ;
; normal ; 30 ;
; normal ; 28 ;
; 1 data inputs ; 1 ;
; 2 data inputs ; 12 ;
; 3 data inputs ; 5 ;
; 4 data inputs ; 12 ;
; 2 data inputs ; 1 ;
; 3 data inputs ; 11 ;
; 4 data inputs ; 15 ;
; ; ;
; Max LUT depth ; 4.40 ;
; Average LUT depth ; 3.08 ;
; Max LUT depth ; 4.50 ;
; Average LUT depth ; 3.02 ;
+-----------------------+-----------------------------+
@ -309,7 +309,7 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Wed Mar 22 12:50:52 2023
Info: Processing started: Tue Mar 28 15:21:53 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
@ -335,14 +335,14 @@ Info (12128): Elaborating entity "FreqDivider" for hierarchy "FreqDivider:inst2"
Info (286030): Timing-Driven Synthesis is running
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Info (21057): Implemented 114 device resources after synthesis - the final resource count might be different
Info (21057): Implemented 112 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 20 input pins
Info (21059): Implemented 17 output pins
Info (21061): Implemented 77 logic cells
Info (21061): Implemented 75 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 456 megabytes
Info: Processing ended: Wed Mar 22 12:50:57 2023
Info: Elapsed time: 00:00:05
Info: Peak virtual memory: 453 megabytes
Info: Processing ended: Tue Mar 28 15:21:59 2023
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:13

6
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.summary
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@ -1,10 +1,10 @@
Analysis & Synthesis Status : Successful - Wed Mar 22 12:50:57 2023
Analysis & Synthesis Status : Successful - Tue Mar 28 15:21:59 2023
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : AccN_Demo
Top-level Entity Name : AccN_Demo
Family : Cyclone IV E
Total logic elements : 77
Total combinational functions : 77
Total logic elements : 75
Total combinational functions : 75
Dedicated logic registers : 50
Total registers : 50
Total pins : 37

BIN
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof
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2232
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.rpt
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38
1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.summary
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@ -3,19 +3,19 @@ Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'CLOCK_50'
Slack : -4.190
TNS : -78.512
Slack : -4.308
TNS : -65.920
Type : Slow 1200mV 85C Model Setup 'FreqDivider:inst2|clkOut'
Slack : -1.348
TNS : -17.156
Slack : -1.349
TNS : -16.351
Type : Slow 1200mV 85C Model Hold 'FreqDivider:inst2|clkOut'
Slack : 0.548
Slack : 0.543
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'CLOCK_50'
Slack : 0.654
Slack : 0.653
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50'
@ -27,19 +27,19 @@ Slack : -1.285
TNS : -21.845
Type : Slow 1200mV 0C Model Setup 'CLOCK_50'
Slack : -3.751
TNS : -67.496
Slack : -3.850
TNS : -55.792
Type : Slow 1200mV 0C Model Setup 'FreqDivider:inst2|clkOut'
Slack : -1.082
TNS : -13.558
Slack : -1.081
TNS : -12.785
Type : Slow 1200mV 0C Model Hold 'FreqDivider:inst2|clkOut'
Slack : 0.494
Slack : 0.489
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.597
Slack : 0.598
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
@ -51,24 +51,24 @@ Slack : -1.285
TNS : -21.845
Type : Fast 1200mV 0C Model Setup 'CLOCK_50'
Slack : -1.596
TNS : -21.945
Slack : -1.676
TNS : -16.763
Type : Fast 1200mV 0C Model Setup 'FreqDivider:inst2|clkOut'
Slack : -0.171
TNS : -0.699
Slack : -0.170
TNS : -0.504
Type : Fast 1200mV 0C Model Hold 'FreqDivider:inst2|clkOut'
Slack : 0.247
Slack : 0.244
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'CLOCK_50'
Slack : 0.298
Slack : 0.297
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50'
Slack : -3.000
TNS : -38.002
TNS : -38.036
Type : Fast 1200mV 0C Model Minimum Pulse Width 'FreqDivider:inst2|clkOut'
Slack : -1.000

936
1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.vho
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41
1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo_modelsim.xrf
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@ -40,7 +40,6 @@ instance = comp, \inst2|Add2~6\, inst2|Add2~6, AccN_Demo, 1
instance = comp, \inst2|s_counter[3]\, inst2|s_counter[3], AccN_Demo, 1
instance = comp, \inst2|Add2~8\, inst2|Add2~8, AccN_Demo, 1
instance = comp, \inst2|s_counter[4]\, inst2|s_counter[4], AccN_Demo, 1
instance = comp, \inst2|Equal0~5\, inst2|Equal0~5, AccN_Demo, 1
instance = comp, \inst2|Add2~10\, inst2|Add2~10, AccN_Demo, 1
instance = comp, \inst2|s_counter[5]\, inst2|s_counter[5], AccN_Demo, 1
instance = comp, \inst2|Add2~12\, inst2|Add2~12, AccN_Demo, 1
@ -48,6 +47,7 @@ instance = comp, \inst2|s_counter~10\, inst2|s_counter~10, AccN_Demo, 1
instance = comp, \inst2|s_counter[6]\, inst2|s_counter[6], AccN_Demo, 1
instance = comp, \inst2|Add2~14\, inst2|Add2~14, AccN_Demo, 1
instance = comp, \inst2|s_counter[7]\, inst2|s_counter[7], AccN_Demo, 1
instance = comp, \inst2|Equal0~3\, inst2|Equal0~3, AccN_Demo, 1
instance = comp, \inst2|Add2~16\, inst2|Add2~16, AccN_Demo, 1
instance = comp, \inst2|s_counter[8]\, inst2|s_counter[8], AccN_Demo, 1
instance = comp, \inst2|Add2~18\, inst2|Add2~18, AccN_Demo, 1
@ -60,44 +60,37 @@ instance = comp, \inst2|s_counter[11]\, inst2|s_counter[11], AccN_Demo, 1
instance = comp, \inst2|Add2~24\, inst2|Add2~24, AccN_Demo, 1
instance = comp, \inst2|s_counter~8\, inst2|s_counter~8, AccN_Demo, 1
instance = comp, \inst2|s_counter[12]\, inst2|s_counter[12], AccN_Demo, 1
instance = comp, \inst2|Equal0~2\, inst2|Equal0~2, AccN_Demo, 1
instance = comp, \inst2|Add2~26\, inst2|Add2~26, AccN_Demo, 1
instance = comp, \inst2|s_counter~7\, inst2|s_counter~7, AccN_Demo, 1
instance = comp, \inst2|s_counter[13]\, inst2|s_counter[13], AccN_Demo, 1
instance = comp, \inst2|Add2~28\, inst2|Add2~28, AccN_Demo, 1
instance = comp, \inst2|s_counter~4\, inst2|s_counter~4, AccN_Demo, 1
instance = comp, \inst2|s_counter~5\, inst2|s_counter~5, AccN_Demo, 1
instance = comp, \inst2|s_counter[14]\, inst2|s_counter[14], AccN_Demo, 1
instance = comp, \inst2|Add2~30\, inst2|Add2~30, AccN_Demo, 1
instance = comp, \inst2|s_counter[15]\, inst2|s_counter[15], AccN_Demo, 1
instance = comp, \inst2|Add2~32\, inst2|Add2~32, AccN_Demo, 1
instance = comp, \inst2|s_counter~3\, inst2|s_counter~3, AccN_Demo, 1
instance = comp, \inst2|s_counter~4\, inst2|s_counter~4, AccN_Demo, 1
instance = comp, \inst2|s_counter[16]\, inst2|s_counter[16], AccN_Demo, 1
instance = comp, \inst2|Add2~34\, inst2|Add2~34, AccN_Demo, 1
instance = comp, \inst2|s_counter[17]\, inst2|s_counter[17], AccN_Demo, 1
instance = comp, \inst2|Add2~36\, inst2|Add2~36, AccN_Demo, 1
instance = comp, \inst2|s_counter~6\, inst2|s_counter~6, AccN_Demo, 1
instance = comp, \inst2|s_counter[18]\, inst2|s_counter[18], AccN_Demo, 1
instance = comp, \inst2|Equal0~2\, inst2|Equal0~2, AccN_Demo, 1
instance = comp, \inst2|Equal0~3\, inst2|Equal0~3, AccN_Demo, 1
instance = comp, \inst2|Add2~38\, inst2|Add2~38, AccN_Demo, 1
instance = comp, \inst2|s_counter~2\, inst2|s_counter~2, AccN_Demo, 1
instance = comp, \inst2|s_counter[19]\, inst2|s_counter[19], AccN_Demo, 1
instance = comp, \inst2|Add2~40\, inst2|Add2~40, AccN_Demo, 1
instance = comp, \inst2|s_counter[20]\, inst2|s_counter[20], AccN_Demo, 1
instance = comp, \inst2|Add2~42\, inst2|Add2~42, AccN_Demo, 1
instance = comp, \inst2|Add2~44\, inst2|Add2~44, AccN_Demo, 1
instance = comp, \inst2|s_counter[22]\, inst2|s_counter[22], AccN_Demo, 1
instance = comp, \inst2|Add2~46\, inst2|Add2~46, AccN_Demo, 1
instance = comp, \inst2|s_counter~5\, inst2|s_counter~5, AccN_Demo, 1
instance = comp, \inst2|s_counter~1\, inst2|s_counter~1, AccN_Demo, 1
instance = comp, \inst2|s_counter[23]\, inst2|s_counter[23], AccN_Demo, 1
instance = comp, \inst2|Add2~48\, inst2|Add2~48, AccN_Demo, 1
instance = comp, \inst2|s_counter~0\, inst2|s_counter~0, AccN_Demo, 1
instance = comp, \inst2|s_counter[24]\, inst2|s_counter[24], AccN_Demo, 1
instance = comp, \inst2|Add2~50\, inst2|Add2~50, AccN_Demo, 1
instance = comp, \inst2|s_counter~0\, inst2|s_counter~0, AccN_Demo, 1
instance = comp, \inst2|s_counter[25]\, inst2|s_counter[25], AccN_Demo, 1
instance = comp, \inst2|Add2~52\, inst2|Add2~52, AccN_Demo, 1
instance = comp, \inst2|s_counter[26]\, inst2|s_counter[26], AccN_Demo, 1
instance = comp, \inst2|Add2~54\, inst2|Add2~54, AccN_Demo, 1
instance = comp, \inst2|s_counter[27]\, inst2|s_counter[27], AccN_Demo, 1
instance = comp, \inst2|Equal0~1\, inst2|Equal0~1, AccN_Demo, 1
instance = comp, \inst2|Add2~56\, inst2|Add2~56, AccN_Demo, 1
instance = comp, \inst2|s_counter[28]\, inst2|s_counter[28], AccN_Demo, 1
instance = comp, \inst2|Add2~58\, inst2|Add2~58, AccN_Demo, 1
@ -107,22 +100,26 @@ instance = comp, \inst2|s_counter[30]\, inst2|s_counter[30], AccN_Demo, 1
instance = comp, \inst2|Add2~62\, inst2|Add2~62, AccN_Demo, 1
instance = comp, \inst2|s_counter[31]\, inst2|s_counter[31], AccN_Demo, 1
instance = comp, \inst2|Equal0~0\, inst2|Equal0~0, AccN_Demo, 1
instance = comp, \inst2|Equal0~1\, inst2|Equal0~1, AccN_Demo, 1
instance = comp, \inst2|Equal0~4\, inst2|Equal0~4, AccN_Demo, 1
instance = comp, \inst2|Equal0~11\, inst2|Equal0~11, AccN_Demo, 1
instance = comp, \inst2|s_counter~1\, inst2|s_counter~1, AccN_Demo, 1
instance = comp, \inst2|Equal0~5\, inst2|Equal0~5, AccN_Demo, 1
instance = comp, \inst2|Add2~38\, inst2|Add2~38, AccN_Demo, 1
instance = comp, \inst2|Add2~40\, inst2|Add2~40, AccN_Demo, 1
instance = comp, \inst2|s_counter[20]\, inst2|s_counter[20], AccN_Demo, 1
instance = comp, \inst2|Add2~42\, inst2|Add2~42, AccN_Demo, 1
instance = comp, \inst2|s_counter~2\, inst2|s_counter~2, AccN_Demo, 1
instance = comp, \inst2|s_counter[21]\, inst2|s_counter[21], AccN_Demo, 1
instance = comp, \inst2|s_counter[22]\, inst2|s_counter[22], AccN_Demo, 1
instance = comp, \inst2|Equal0~6\, inst2|Equal0~6, AccN_Demo, 1
instance = comp, \inst2|Equal0~7\, inst2|Equal0~7, AccN_Demo, 1
instance = comp, \inst2|Equal0~8\, inst2|Equal0~8, AccN_Demo, 1
instance = comp, \inst2|Equal0~9\, inst2|Equal0~9, AccN_Demo, 1
instance = comp, \inst2|Equal0~10\, inst2|Equal0~10, AccN_Demo, 1
instance = comp, \inst2|clkOut~0\, inst2|clkOut~0, AccN_Demo, 1
instance = comp, \inst2|clkOut~2\, inst2|clkOut~2, AccN_Demo, 1
instance = comp, \inst2|s_counter~3\, inst2|s_counter~3, AccN_Demo, 1
instance = comp, \inst2|s_counter[19]\, inst2|s_counter[19], AccN_Demo, 1
instance = comp, \inst2|clkOut~1\, inst2|clkOut~1, AccN_Demo, 1
instance = comp, \inst2|clkOut~2\, inst2|clkOut~2, AccN_Demo, 1
instance = comp, \inst2|clkOut~0\, inst2|clkOut~0, AccN_Demo, 1
instance = comp, \inst2|clkOut~3\, inst2|clkOut~3, AccN_Demo, 1
instance = comp, \inst2|Equal0~6\, inst2|Equal0~6, AccN_Demo, 1
instance = comp, \inst2|clkOut~4\, inst2|clkOut~4, AccN_Demo, 1
instance = comp, \inst2|clkOut~feeder\, inst2|clkOut~feeder, AccN_Demo, 1
instance = comp, \inst2|clkOut\, inst2|clkOut, AccN_Demo, 1
instance = comp, \inst2|clkOut~clkctrl\, inst2|clkOut~clkctrl, AccN_Demo, 1
instance = comp, \SW[16]~input\, SW[16]~input, AccN_Demo, 1