[LSD] pratica05 part3 added
This commit is contained in:
TiagoRG
parent
622f3b0eb1
commit
fd54e7341d
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@ -0,0 +1,50 @@
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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||||||
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editor if you plan to continue editing the block that represents it in
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||||||
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the Block Editor! File corruption is VERY likely to occur.
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||||||
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*/
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||||||
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/*
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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||||||
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Your use of Intel Corporation's design tools, logic functions
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||||||
|
and other software and tools, and any partner logic
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||||||
|
functions, and any output files from any of the foregoing
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||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
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||||||
|
to the terms and conditions of the Intel Program License
|
||||||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
agreement, including, without limitation, that your use is for
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||||||
|
the sole purpose of programming logic devices manufactured by
|
||||||
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Intel and sold by Intel or its authorized distributors. Please
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||||||
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 160 96)
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(text "FreqDivider" (rect 5 0 52 12)(font "Arial" ))
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(text "inst" (rect 8 64 20 76)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clkIn" (rect 0 0 17 12)(font "Arial" ))
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(text "clkIn" (rect 21 27 38 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 144 32)
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(output)
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(text "clkOut" (rect 0 0 24 12)(font "Arial" ))
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(text "clkOut" (rect 99 27 123 39)(font "Arial" ))
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(line (pt 144 32)(pt 128 32)(line_width 1))
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)
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(parameter
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"divFactor"
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"10"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(drawing
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(rectangle (rect 16 16 128 64)(line_width 1))
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)
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(annotation_block (parameter)(rect 160 -64 260 16))
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)
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@ -0,0 +1,33 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity FreqDivider is
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generic(divFactor : positive := 10);
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port
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(
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clkIn : in std_logic;
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clkOut : out std_logic
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);
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end FreqDivider;
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architecture Behavioral of FreqDivider is
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subtype TCounter is natural range 0 to divFactor - 1;
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signal s_divCounter : TCounter := 0;
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begin
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assert(divFactor >= 2);
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process(clkIn)
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begin
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if (rising_edge(clkIn)) then
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if (s_divCounter >= (divFactor - 1)) then
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clkOut <= '0';
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s_divCounter <= 0;
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else
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if (s_divCounter = (divFactor / 2 - 1)) then
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clkOut <= '1';
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end if;
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s_divCounter <= s_divCounter + 1;
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end if;
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end if;
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end process;
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end Behavioral;
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@ -0,0 +1,71 @@
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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||||||
|
editor if you plan to continue editing the block that represents it in
|
||||||
|
the Block Editor! File corruption is VERY likely to occur.
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||||||
|
*/
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||||||
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/*
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Copyright (C) 2020 Intel Corporation. All rights reserved.
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||||||
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and any partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Intel Program License
|
||||||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
agreement, including, without limitation, that your use is for
|
||||||
|
the sole purpose of programming logic devices manufactured by
|
||||||
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
refer to the applicable agreement for further details, at
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||||||
|
https://fpgasoftware.intel.com/eula.
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||||||
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 176 128)
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(text "TimerN" (rect 5 0 35 12)(font "Arial" ))
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(text "inst" (rect 8 96 20 108)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clk" (rect 0 0 10 12)(font "Arial" ))
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(text "clk" (rect 21 27 31 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 0 48)
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(input)
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(text "enable" (rect 0 0 24 12)(font "Arial" ))
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(text "enable" (rect 21 43 45 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 1))
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)
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(port
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(pt 0 64)
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(input)
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(text "start" (rect 0 0 17 12)(font "Arial" ))
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(text "start" (rect 21 59 38 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 1))
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)
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(port
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(pt 0 80)
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(input)
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(text "reset" (rect 0 0 20 12)(font "Arial" ))
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(text "reset" (rect 21 75 41 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80)(line_width 1))
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)
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(port
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(pt 160 32)
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(output)
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(text "timerOut" (rect 0 0 34 12)(font "Arial" ))
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(text "timerOut" (rect 105 27 139 39)(font "Arial" ))
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(line (pt 160 32)(pt 144 32)(line_width 1))
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)
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(parameter
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"N"
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"6"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(drawing
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(rectangle (rect 16 16 144 96)(line_width 1))
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)
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(annotation_block (parameter)(rect 176 -64 276 16))
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)
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@ -0,0 +1,40 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity TimerN is
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generic (N : positive := 6);
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port
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(
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clk : in std_logic;
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enable : in std_logic;
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start : in std_logic;
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reset : in std_logic;
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timerOut : out std_logic
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);
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end TimerN;
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architecture Behavioral of TimerN is
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signal s_count : std_logic_vector(31 downto 0);
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begin
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process (clk)
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begin
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if (rising_edge(clk)) then
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if (reset = '0' and enable = '1') then
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if (unsigned(s_count) < N and not (unsigned(s_count) = 0 and start = '0')) then
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s_count <= std_logic_vector(unsigned(s_count) + 1);
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else
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s_count <= (others => '0');
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end if;
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elsif (reset = '1') then
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s_count <= (others => '0');
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end if;
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if (unsigned(s_count) = 0) then
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timerOut <= '0';
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else
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timerOut <= '1';
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end if;
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end if;
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end process;
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end Behavioral;
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@ -0,0 +1,228 @@
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/*
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|
WARNING: Do NOT edit the input and output ports in this file in a text
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||||||
|
editor if you plan to continue editing the block that represents it in
|
||||||
|
the Block Editor! File corruption is VERY likely to occur.
|
||||||
|
*/
|
||||||
|
/*
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||||||
|
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||||
|
Your use of Intel Corporation's design tools, logic functions
|
||||||
|
and other software and tools, and any partner logic
|
||||||
|
functions, and any output files from any of the foregoing
|
||||||
|
(including device programming or simulation files), and any
|
||||||
|
associated documentation or information are expressly subject
|
||||||
|
to the terms and conditions of the Intel Program License
|
||||||
|
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||||
|
the Intel FPGA IP License Agreement, or other applicable license
|
||||||
|
agreement, including, without limitation, that your use is for
|
||||||
|
the sole purpose of programming logic devices manufactured by
|
||||||
|
Intel and sold by Intel or its authorized distributors. Please
|
||||||
|
refer to the applicable agreement for further details, at
|
||||||
|
https://fpgasoftware.intel.com/eula.
|
||||||
|
*/
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(header "graphic" (version "1.4"))
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(pin
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(input)
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(rect 664 304 680 472)
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(text "INPUT" (rect 0 14 10 43)(font "Arial" (font_size 6))(vertical))
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(text "SW[2]" (rect 0 133 11 163)(font "Arial" )(vertical))
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(pt 8 0)
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(drawing
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(line (pt 12 84)(pt 12 59))
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(line (pt 4 84)(pt 4 59))
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(line (pt 8 55)(pt 8 0))
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(line (pt 12 84)(pt 4 84))
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(line (pt 4 59)(pt 8 55))
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(line (pt 12 59)(pt 8 55))
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)
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(rotate90)
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(text "VCC" (rect 7 19 17 40)(font "Arial" (font_size 6))(vertical))
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(annotation_block (location)(rect 600 472 664 488))
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)
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(pin
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(input)
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(rect 648 304 664 472)
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(text "INPUT" (rect 0 14 10 43)(font "Arial" (font_size 6))(vertical))
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(text "SW[1]" (rect 0 129 13 163)(font "Intel Clear" )(vertical))
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(pt 8 0)
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(drawing
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(line (pt 12 84)(pt 12 59))
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(line (pt 4 84)(pt 4 59))
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||||||
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(line (pt 8 55)(pt 8 0))
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||||||
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(line (pt 12 84)(pt 4 84))
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(line (pt 4 59)(pt 8 55))
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(line (pt 12 59)(pt 8 55))
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)
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(rotate90)
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(text "VCC" (rect 7 19 17 40)(font "Arial" (font_size 6))(vertical))
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(annotation_block (location)(rect 584 472 648 488))
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)
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(pin
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(input)
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(rect 632 304 648 472)
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(text "INPUT" (rect 0 14 10 43)(font "Arial" (font_size 6))(vertical))
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(text "SW[0]" (rect 0 129 13 163)(font "Intel Clear" )(vertical))
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(pt 8 0)
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(drawing
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(line (pt 12 84)(pt 12 59))
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(line (pt 4 84)(pt 4 59))
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(line (pt 8 55)(pt 8 0))
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(line (pt 12 84)(pt 4 84))
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(line (pt 4 59)(pt 8 55))
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(line (pt 12 59)(pt 8 55))
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)
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(rotate90)
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(text "VCC" (rect 7 19 17 40)(font "Arial" (font_size 6))(vertical))
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(annotation_block (location)(rect 568 472 632 488))
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)
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(pin
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(input)
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(rect 472 256 488 424)
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(text "INPUT" (rect 0 14 10 43)(font "Arial" (font_size 6))(vertical))
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(text "CLOCK_50" (rect 0 105 11 163)(font "Arial" )(vertical))
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(pt 8 0)
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(drawing
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(line (pt 12 84)(pt 12 59))
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(line (pt 4 84)(pt 4 59))
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(line (pt 8 55)(pt 8 0))
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(line (pt 12 84)(pt 4 84))
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(line (pt 4 59)(pt 8 55))
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(line (pt 12 59)(pt 8 55))
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)
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(rotate90)
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(text "VCC" (rect 7 19 17 40)(font "Arial" (font_size 6))(vertical))
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(annotation_block (location)(rect 416 424 472 440))
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)
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(pin
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(output)
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(rect 848 240 1024 256)
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(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
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(text "LEDR[0]" (rect 90 0 132 11)(font "Arial" ))
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(pt 0 8)
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(drawing
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||||||
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(line (pt 0 8)(pt 52 8))
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(line (pt 52 4)(pt 78 4))
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(line (pt 52 12)(pt 78 12))
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(line (pt 52 12)(pt 52 4))
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(line (pt 78 4)(pt 82 8))
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(line (pt 82 8)(pt 78 12))
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(line (pt 78 12)(pt 82 8))
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)
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(annotation_block (location)(rect 1024 256 1088 272))
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)
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(symbol
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(rect 680 216 840 328)
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(text "TimerN" (rect 5 0 41 11)(font "Arial" ))
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(text "inst1" (rect 8 96 32 109)(font "Intel Clear" ))
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(port
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(pt 0 32)
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(input)
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(text "clk" (rect 0 0 15 11)(font "Arial" ))
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(text "clk" (rect 21 27 36 38)(font "Arial" ))
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(line (pt 0 32)(pt 16 32))
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)
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(port
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(pt 0 48)
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(input)
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(text "enable" (rect 0 0 34 11)(font "Arial" ))
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(text "enable" (rect 21 43 55 54)(font "Arial" ))
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(line (pt 0 48)(pt 16 48))
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)
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(port
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(pt 0 64)
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(input)
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(text "start" (rect 0 0 23 11)(font "Arial" ))
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(text "start" (rect 21 59 44 70)(font "Arial" ))
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(line (pt 0 64)(pt 16 64))
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)
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(port
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(pt 0 80)
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(input)
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(text "reset" (rect 0 0 25 11)(font "Arial" ))
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(text "reset" (rect 21 75 46 86)(font "Arial" ))
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(line (pt 0 80)(pt 16 80))
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)
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(port
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(pt 160 32)
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(output)
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(text "timerOut" (rect 0 0 43 11)(font "Arial" ))
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(text "timerOut" (rect 103 27 146 38)(font "Arial" ))
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(line (pt 160 32)(pt 144 32))
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)
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(parameter
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"N"
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"6"
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""
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||||||
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(type "PARAMETER_SIGNED_DEC") )
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(drawing
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(rectangle (rect 16 16 144 96))
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)
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(annotation_block (parameter)(rect 840 184 1016 216))
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)
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(symbol
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(rect 488 216 632 296)
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||||||
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(text "FreqDivider" (rect 5 0 64 11)(font "Arial" ))
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||||||
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(text "inst" (rect 8 64 26 75)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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||||||
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(text "clkIn" (rect 0 0 24 11)(font "Arial" ))
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||||||
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(text "clkIn" (rect 21 27 45 38)(font "Arial" ))
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(line (pt 0 32)(pt 16 32))
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)
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(port
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||||||
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(pt 144 32)
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(output)
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||||||
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(text "clkOut" (rect 0 0 33 11)(font "Arial" ))
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||||||
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(text "clkOut" (rect 96 27 129 38)(font "Arial" ))
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(line (pt 144 32)(pt 128 32))
|
||||||
|
)
|
||||||
|
(parameter
|
||||||
|
"divFactor"
|
||||||
|
"50000000"
|
||||||
|
""
|
||||||
|
(type "PARAMETER_SIGNED_DEC") )
|
||||||
|
(drawing
|
||||||
|
(rectangle (rect 16 16 128 64))
|
||||||
|
)
|
||||||
|
(annotation_block (parameter)(rect 632 184 826 214))
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 672 296)
|
||||||
|
(pt 672 304)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 680 296)
|
||||||
|
(pt 672 296)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 656 304)
|
||||||
|
(pt 656 280)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 656 280)
|
||||||
|
(pt 680 280)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 680 264)
|
||||||
|
(pt 640 264)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 640 264)
|
||||||
|
(pt 640 304)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 680 248)
|
||||||
|
(pt 632 248)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 488 248)
|
||||||
|
(pt 480 248)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 480 248)
|
||||||
|
(pt 480 256)
|
||||||
|
)
|
||||||
|
(connector
|
||||||
|
(pt 848 248)
|
||||||
|
(pt 840 248)
|
||||||
|
)
|
||||||
Binary file not shown.
Loading…
Reference in New Issue