diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/ALUDemo.bdf b/1ano/2semestre/lsd/pratica03/ALUDemo/ALUDemo.bdf
index 8789a97..c84eb4a 100644
--- a/1ano/2semestre/lsd/pratica03/ALUDemo/ALUDemo.bdf
+++ b/1ano/2semestre/lsd/pratica03/ALUDemo/ALUDemo.bdf
@@ -20,28 +20,11 @@ refer to the applicable agreement for further details, at
 https://fpgasoftware.intel.com/eula.
 */
 (header "graphic" (version "1.4"))
-(pin
-	(input)
-	(rect 272 144 440 160)
-	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
-	(text "SW[7..4]" (rect 5 0 47 11)(font "Arial" ))
-	(pt 168 8)
-	(drawing
-		(line (pt 84 12)(pt 109 12))
-		(line (pt 84 4)(pt 109 4))
-		(line (pt 113 8)(pt 168 8))
-		(line (pt 84 12)(pt 84 4))
-		(line (pt 109 4)(pt 113 8))
-		(line (pt 109 12)(pt 113 8))
-	)
-	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
-	(annotation_block (location)(rect 208 160 272 176))
-)
 (pin
 	(input)
 	(rect 272 160 440 176)
 	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
-	(text "SW[3..0]" (rect 5 0 48 13)(font "Intel Clear" ))
+	(text "SW[5..0]" (rect 5 0 48 13)(font "Intel Clear" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 84 12)(pt 109 12))
@@ -54,11 +37,28 @@ https://fpgasoftware.intel.com/eula.
 	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
 	(annotation_block (location)(rect 208 176 272 192))
 )
+(pin
+	(input)
+	(rect 272 144 440 160)
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+	(text "SW[11..6]" (rect 5 0 54 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 208 160 272 176))
+)
 (pin
 	(input)
 	(rect 272 176 440 192)
 	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
-	(text "SW[10..8]" (rect 5 0 54 11)(font "Arial" ))
+	(text "SW[14..12]" (rect 5 0 61 11)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 84 12)(pt 109 12))
@@ -73,9 +73,9 @@ https://fpgasoftware.intel.com/eula.
 )
 (pin
 	(output)
-	(rect 616 144 792 160)
+	(rect 624 160 800 176)
 	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
-	(text "LEDR[3..0]" (rect 90 0 144 11)(font "Arial" ))
+	(text "LEDR[11..6]" (rect 90 0 150 13)(font "Intel Clear" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 0 8)(pt 52 8))
@@ -86,13 +86,13 @@ https://fpgasoftware.intel.com/eula.
 		(line (pt 82 8)(pt 78 12))
 		(line (pt 78 12)(pt 82 8))
 	)
-	(annotation_block (location)(rect 792 160 856 176))
+	(annotation_block (location)(rect 800 176 856 192))
 )
 (pin
 	(output)
-	(rect 616 160 792 176)
+	(rect 624 144 800 160)
 	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
-	(text "LEDR[7..4]" (rect 90 0 143 13)(font "Intel Clear" ))
+	(text "LEDR[5..0]" (rect 90 0 144 11)(font "Arial" ))
 	(pt 0 8)
 	(drawing
 		(line (pt 0 8)(pt 52 8))
@@ -103,24 +103,24 @@ https://fpgasoftware.intel.com/eula.
 		(line (pt 82 8)(pt 78 12))
 		(line (pt 78 12)(pt 82 8))
 	)
-	(annotation_block (location)(rect 792 176 848 192))
+	(annotation_block (location)(rect 800 160 864 176))
 )
 (symbol
-	(rect 448 120 608 232)
-	(text "ALU4" (rect 5 0 34 11)(font "Arial" ))
+	(rect 448 120 616 232)
+	(text "ALUN" (rect 5 0 34 11)(font "Arial" ))
 	(text "inst" (rect 8 96 26 107)(font "Arial" ))
 	(port
 		(pt 0 32)
 		(input)
-		(text "a[3..0]" (rect 0 0 30 11)(font "Arial" ))
-		(text "a[3..0]" (rect 21 27 51 38)(font "Arial" ))
+		(text "a[n-1..0]" (rect 0 0 41 11)(font "Arial" ))
+		(text "a[n-1..0]" (rect 21 27 62 38)(font "Arial" ))
 		(line (pt 0 32)(pt 16 32)(line_width 3))
 	)
 	(port
 		(pt 0 48)
 		(input)
-		(text "b[3..0]" (rect 0 0 30 11)(font "Arial" ))
-		(text "b[3..0]" (rect 21 43 51 54)(font "Arial" ))
+		(text "b[n-1..0]" (rect 0 0 41 11)(font "Arial" ))
+		(text "b[n-1..0]" (rect 21 43 62 54)(font "Arial" ))
 		(line (pt 0 48)(pt 16 48)(line_width 3))
 	)
 	(port
@@ -131,22 +131,28 @@ https://fpgasoftware.intel.com/eula.
 		(line (pt 0 64)(pt 16 64)(line_width 3))
 	)
 	(port
-		(pt 160 32)
+		(pt 168 32)
 		(output)
-		(text "r[3..0]" (rect 0 0 28 11)(font "Arial" ))
-		(text "r[3..0]" (rect 116 27 144 38)(font "Arial" ))
-		(line (pt 160 32)(pt 144 32)(line_width 3))
+		(text "r[n-1..0]" (rect 0 0 38 11)(font "Arial" ))
+		(text "r[n-1..0]" (rect 115 27 153 38)(font "Arial" ))
+		(line (pt 168 32)(pt 152 32)(line_width 3))
 	)
 	(port
-		(pt 160 48)
+		(pt 168 48)
 		(output)
-		(text "m[3..0]" (rect 0 0 34 11)(font "Arial" ))
-		(text "m[3..0]" (rect 111 43 145 54)(font "Arial" ))
-		(line (pt 160 48)(pt 144 48)(line_width 3))
+		(text "m[n-1..0]" (rect 0 0 43 11)(font "Arial" ))
+		(text "m[n-1..0]" (rect 111 43 154 54)(font "Arial" ))
+		(line (pt 168 48)(pt 152 48)(line_width 3))
 	)
+	(parameter
+		"N"
+		"6"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
 	(drawing
-		(rectangle (rect 16 16 144 96))
+		(rectangle (rect 16 16 152 96))
 	)
+	(annotation_block (parameter)(rect 616 88 787 118))
 )
 (connector
 	(pt 448 152)
@@ -164,12 +170,12 @@ https://fpgasoftware.intel.com/eula.
 	(bus)
 )
 (connector
-	(pt 608 152)
 	(pt 616 152)
+	(pt 624 152)
 	(bus)
 )
 (connector
-	(pt 608 168)
 	(pt 616 168)
+	(pt 624 168)
 	(bus)
 )
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/ALUN.bsf b/1ano/2semestre/lsd/pratica03/ALUDemo/ALUN.bsf
new file mode 100644
index 0000000..1bf1ca4
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica03/ALUDemo/ALUN.bsf
@@ -0,0 +1,71 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 184 128)
+	(text "ALUN" (rect 5 0 33 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "a[n-1..0]" (rect 0 0 30 12)(font "Arial" ))
+		(text "a[n-1..0]" (rect 21 27 51 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "b[n-1..0]" (rect 0 0 30 12)(font "Arial" ))
+		(text "b[n-1..0]" (rect 21 43 51 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "op[2..0]" (rect 0 0 29 12)(font "Arial" ))
+		(text "op[2..0]" (rect 21 59 50 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 168 32)
+		(output)
+		(text "r[n-1..0]" (rect 0 0 29 12)(font "Arial" ))
+		(text "r[n-1..0]" (rect 118 27 147 39)(font "Arial" ))
+		(line (pt 168 32)(pt 152 32)(line_width 3))
+	)
+	(port
+		(pt 168 48)
+		(output)
+		(text "m[n-1..0]" (rect 0 0 34 12)(font "Arial" ))
+		(text "m[n-1..0]" (rect 113 43 147 55)(font "Arial" ))
+		(line (pt 168 48)(pt 152 48)(line_width 3))
+	)
+	(parameter
+		"N"
+		"8"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(rectangle (rect 16 16 152 96)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 184 -64 284 16))
+)
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/ALUN.vhd b/1ano/2semestre/lsd/pratica03/ALUDemo/ALUN.vhd
new file mode 100644
index 0000000..8f0ad4a
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica03/ALUDemo/ALUN.vhd
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity ALUN is
+	generic (N : positive := 8);
+	port
+	(
+		a,b  : in  std_logic_vector((N-1) downto 0);
+		op   : in  std_logic_vector(2 downto 0);
+		r, m : out std_logic_vector((N-1) downto 0)
+	);
+end ALUN;
+
+architecture Behavioral of ALUN is
+	signal s_a, s_b, s_r : unsigned((N-1) downto 0);
+	signal s_m           : unsigned(((N*2)-1) downto 0);
+begin
+	s_a <= unsigned(a);
+	s_b <= unsigned(b);
+	
+	s_m <= s_a * s_b;
+	
+	with op select
+		s_r <= s_a  +  s_b     when "000",
+				 s_a  -  s_b     when "001",
+				 s_m((N-1) downto 0) when "010",
+				 s_a  /  s_b     when "011",
+				 s_a rem s_b     when "100",
+				 s_a and s_b     when "101",
+				 s_a or  s_b     when "110",
+				 s_a xor s_b	  when "111";
+	
+	r <= std_logic_vector(s_r);
+	m <= std_logic_vector(s_m(((N*2)-1) downto N)) when (op = "010") else (others => '0');
+end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sof b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sof
index 446fe14..4c36467 100644
Binary files a/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sof and b/1ano/2semestre/lsd/pratica03/ALUDemo/output_files/ALUDemo.sof differ
diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.bsf b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.bsf
new file mode 100644
index 0000000..e7f4eaf
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.bsf
@@ -0,0 +1,65 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 176 128)
+	(text "ALU4" (rect 5 0 32 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "a[3..0]" (rect 0 0 24 12)(font "Arial" ))
+		(text "a[3..0]" (rect 21 27 45 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "b[3..0]" (rect 0 0 24 12)(font "Arial" ))
+		(text "b[3..0]" (rect 21 43 45 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "op[2..0]" (rect 0 0 29 12)(font "Arial" ))
+		(text "op[2..0]" (rect 21 59 50 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "r[3..0]" (rect 0 0 23 12)(font "Arial" ))
+		(text "r[3..0]" (rect 116 27 139 39)(font "Arial" ))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(port
+		(pt 160 48)
+		(output)
+		(text "m[3..0]" (rect 0 0 28 12)(font "Arial" ))
+		(text "m[3..0]" (rect 111 43 139 55)(font "Arial" ))
+		(line (pt 160 48)(pt 144 48)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 144 96)(line_width 1))
+	)
+)
diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.vhd b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.vhd
new file mode 100644
index 0000000..64977d2
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.vhd
@@ -0,0 +1,35 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity ALU4 is
+	port
+	(
+		a,b  : in  std_logic_vector(3 downto 0);
+		op   : in  std_logic_vector(2 downto 0);
+		r, m : out std_logic_vector(3 downto 0)
+	);
+end ALU4;
+
+architecture Behavioral of ALU4 is
+	signal s_a, s_b, s_r : unsigned(3 downto 0);
+	signal s_m           : unsigned(7 downto 0);
+begin
+	s_a <= unsigned(a);
+	s_b <= unsigned(b);
+	
+	s_m <= s_a * s_b;
+	
+	with op select
+		s_r <= s_a  +  s_b     when "000",
+				 s_a  -  s_b     when "001",
+				 s_m(3 downto 0) when "010",
+				 s_a  /  s_b     when "011",
+				 s_a rem s_b     when "100",
+				 s_a and s_b     when "101",
+				 s_a or  s_b     when "110",
+				 s_a xor s_b	  when "111";
+	
+	r <= std_logic_vector(s_r);
+	m <= std_logic_vector(s_m(7 downto 4)) when (op = "010") else (others => '0');
+end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALUDemo.bdf b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALUDemo.bdf
new file mode 100644
index 0000000..ed4ab56
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALUDemo.bdf
@@ -0,0 +1,285 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 272 144 440 160)
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+	(text "SW[3..0]" (rect 5 0 48 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 208 160 272 176))
+)
+(pin
+	(input)
+	(rect 272 160 440 176)
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+	(text "SW[7..4]" (rect 5 0 49 13)(font "Intel Clear" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 208 176 272 192))
+)
+(pin
+	(input)
+	(rect 272 176 440 192)
+	(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
+	(text "SW[10..8]" (rect 5 0 54 11)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 84 12)(pt 109 12))
+		(line (pt 84 4)(pt 109 4))
+		(line (pt 113 8)(pt 168 8))
+		(line (pt 84 12)(pt 84 4))
+		(line (pt 109 4)(pt 113 8))
+		(line (pt 109 12)(pt 113 8))
+	)
+	(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 208 192 272 208))
+)
+(pin
+	(output)
+	(rect 856 144 1032 160)
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
+	(text "HEX0[6..0]" (rect 90 0 144 11)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1032 160 1096 176))
+)
+(pin
+	(output)
+	(rect 856 224 1032 240)
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
+	(text "HEX1[6..0]" (rect 90 0 144 13)(font "Intel Clear" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1032 240 1096 256))
+)
+(symbol
+	(rect 448 120 608 232)
+	(text "ALU4" (rect 5 0 34 11)(font "Arial" ))
+	(text "inst" (rect 8 96 26 107)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "a[3..0]" (rect 0 0 30 11)(font "Arial" ))
+		(text "a[3..0]" (rect 21 27 51 38)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "b[3..0]" (rect 0 0 30 11)(font "Arial" ))
+		(text "b[3..0]" (rect 21 43 51 54)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "op[2..0]" (rect 0 0 37 11)(font "Arial" ))
+		(text "op[2..0]" (rect 21 59 58 70)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "r[3..0]" (rect 0 0 28 11)(font "Arial" ))
+		(text "r[3..0]" (rect 116 27 144 38)(font "Arial" ))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(port
+		(pt 160 48)
+		(output)
+		(text "m[3..0]" (rect 0 0 34 11)(font "Arial" ))
+		(text "m[3..0]" (rect 111 43 145 54)(font "Arial" ))
+		(line (pt 160 48)(pt 144 48)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 144 96))
+	)
+)
+(symbol
+	(rect 640 120 848 200)
+	(text "Bin7SegDecoder" (rect 5 0 89 11)(font "Arial" ))
+	(text "inst1" (rect 8 64 32 77)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "binInput[3..0]" (rect 0 0 63 11)(font "Arial" ))
+		(text "binInput[3..0]" (rect 21 27 84 38)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "enable" (rect 0 0 34 11)(font "Arial" ))
+		(text "enable" (rect 21 43 55 54)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 208 32)
+		(output)
+		(text "decOut_n[6..0]" (rect 0 0 73 11)(font "Arial" ))
+		(text "decOut_n[6..0]" (rect 126 27 199 38)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 192 64))
+	)
+)
+(symbol
+	(rect 640 200 848 280)
+	(text "Bin7SegDecoder" (rect 5 0 89 11)(font "Arial" ))
+	(text "inst2" (rect 8 64 32 77)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "binInput[3..0]" (rect 0 0 63 11)(font "Arial" ))
+		(text "binInput[3..0]" (rect 21 27 84 38)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "enable" (rect 0 0 34 11)(font "Arial" ))
+		(text "enable" (rect 21 43 55 54)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 208 32)
+		(output)
+		(text "decOut_n[6..0]" (rect 0 0 73 11)(font "Arial" ))
+		(text "decOut_n[6..0]" (rect 126 27 199 38)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 192 64))
+	)
+)
+(symbol
+	(rect 608 128 640 144)
+	(text "VCC" (rect 7 0 28 10)(font "Arial" (font_size 6)))
+	(text "inst3" (rect 3 5 27 18)(font "Intel Clear" )(invisible))
+	(port
+		(pt 16 16)
+		(output)
+		(text "1" (rect 19 7 27 18)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 19 7 27 18)(font "Courier New" (bold))(invisible))
+		(line (pt 16 16)(pt 16 8))
+	)
+	(drawing
+		(line (pt 8 8)(pt 24 8))
+	)
+)
+(connector
+	(pt 448 152)
+	(pt 440 152)
+	(bus)
+)
+(connector
+	(pt 448 168)
+	(pt 440 168)
+	(bus)
+)
+(connector
+	(pt 448 184)
+	(pt 440 184)
+	(bus)
+)
+(connector
+	(pt 608 168)
+	(pt 616 168)
+	(bus)
+)
+(connector
+	(pt 608 152)
+	(pt 640 152)
+	(bus)
+)
+(connector
+	(pt 624 168)
+	(pt 640 168)
+)
+(connector
+	(pt 616 168)
+	(pt 616 232)
+	(bus)
+)
+(connector
+	(pt 616 232)
+	(pt 640 232)
+	(bus)
+)
+(connector
+	(pt 624 248)
+	(pt 640 248)
+)
+(connector
+	(pt 624 144)
+	(pt 624 168)
+)
+(connector
+	(pt 624 168)
+	(pt 624 248)
+)
+(connector
+	(pt 856 232)
+	(pt 848 232)
+	(bus)
+)
+(connector
+	(pt 848 152)
+	(pt 856 152)
+	(bus)
+)
+(junction (pt 624 168))
diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.bsf b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.bsf
new file mode 100644
index 0000000..2cc9938
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.bsf
@@ -0,0 +1,51 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 224 96)
+	(text "Bin7SegDecoder" (rect 5 0 71 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "binInput[3..0]" (rect 0 0 49 12)(font "Arial" ))
+		(text "binInput[3..0]" (rect 21 27 70 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "enable" (rect 0 0 24 12)(font "Arial" ))
+		(text "enable" (rect 21 43 45 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 208 32)
+		(output)
+		(text "decOut_n[6..0]" (rect 0 0 59 12)(font "Arial" ))
+		(text "decOut_n[6..0]" (rect 128 27 187 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 192 64)(line_width 1))
+	)
+)
diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.vhd b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.vhd
new file mode 100644
index 0000000..96f7b6b
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.vhd
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity Bin7SegDecoder is
+	port
+	(
+		binInput : in  std_logic_vector(3 downto 0);
+		enable   : in  std_logic;
+		decOut_n : out std_logic_vector(6 downto 0)
+	);
+end Bin7SegDecoder;
+
+architecture Behavioral of Bin7SegDecoder is
+begin
+	decOut_n <= "1111111" when (enable   = '0'   ) else -- disabled
+	            "1111001" when (binInput = "0001") else --1
+					"0100100" when (binInput = "0010") else --2
+					"0110000" when (binInput = "0011") else --3
+					"0011001" when (binInput = "0100") else --4
+					"0010010" when (binInput = "0101") else --5
+					"0000010" when (binInput = "0110") else --6
+					"1111000" when (binInput = "0111") else --7
+					"0000000" when (binInput = "1000") else --8
+					"0010000" when (binInput = "1001") else --9
+					"0001000" when (binInput = "1010") else --A
+					"0000011" when (binInput = "1011") else --b
+					"1000110" when (binInput = "1100") else --C
+					"0100001" when (binInput = "1101") else --d
+					"0000110" when (binInput = "1110") else --E
+					"0001110" when (binInput = "1111") else --F
+					"1000000"; --0
+end Behavioral;
diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/output_files/ALUDisplayDemo.sof b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/output_files/ALUDisplayDemo.sof
new file mode 100644
index 0000000..8651d79
Binary files /dev/null and b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/output_files/ALUDisplayDemo.sof differ
diff --git a/1ano/2semestre/lsd/pratica05/BasicWatch/BasicWatch.vhd b/1ano/2semestre/lsd/pratica05/BasicWatch/BasicWatch.vhd
new file mode 100644
index 0000000..f6a0723
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica05/BasicWatch/BasicWatch.vhd
@@ -0,0 +1,176 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity BasicWatch is
+	port(SW        : in  std_logic_vector(0 downto 0);
+		  CLOCK_50	: in  std_logic;
+		  KEY			: in  std_logic_vector(3 downto 0);
+		  HEX2		: out std_logic_vector(6 downto 0);
+		  HEX3		: out std_logic_vector(6 downto 0);
+		  HEX4		: out std_logic_vector(6 downto 0);
+		  HEX5		: out std_logic_vector(6 downto 0);
+		  HEX6		: out std_logic_vector(6 downto 0);
+		  HEX7		: out std_logic_vector(6 downto 0);
+		  LEDG		: out std_logic_vector(8 downto 8));
+end BasicWatch;
+
+architecture Structural of BasicWatch is
+
+	-- Global enable signal
+	signal s_enable : std_logic;
+
+	-- Global reset signal 
+	signal s_globalRst : std_logic;
+	
+	-- Individual reset for the seconds counters ('1' while setting min/hours)
+	signal s_sReset : std_logic;
+	
+	-- Control signals
+	signal s_mode : std_logic; -- s_mode='0'-normal operation; s_mode='1'-set min/hours
+	signal s_hSet : std_logic; -- s_hSet='1'-set (fast increment) hours
+	signal s_mSet : std_logic; -- s_mSet='1'-set (fast increment) minutes
+	
+	-- Base 4 Hz clock signal
+	signal s_clk4Hz : std_logic;
+	
+	-- Global enable (always '1' while setting min/hours;
+	-- otherwise always repeating '1', '0', '0', '0')
+	signal s_globalEnb : std_logic;
+
+	-- Binary values of each counter
+	signal s_sUnitsBin, s_sTensBin	: std_logic_vector(3 downto 0);
+	signal s_mUnitsBin, s_mTensBin	: std_logic_vector(3 downto 0);
+	signal s_hUnitsBin, s_hTensBin	: std_logic_vector(3 downto 0);
+	signal s_hUnitsMax : natural := 9;
+
+	-- Terminal count flags of each counter
+	signal s_sUnitsTerm, s_sTensTerm	: std_logic;
+	signal s_mUnitsTerm, s_mTensTerm	: std_logic;
+	signal s_hUnitsTerm					: std_logic;
+
+	-- Enable signals of each counter
+	signal s_sUnitsEnb, s_sTensEnb	: std_logic;
+	signal s_mUnitsEnb, s_mTensEnb	: std_logic;
+	signal s_hUnitsEnb, s_hTensEnb	: std_logic;
+
+begin
+	s_globalRst	<= not KEY(3);
+	s_sReset		<= s_globalRst or s_mode;
+	s_enable    <= SW(0);
+	
+	s_mode <= not KEY(2); 
+	s_hSet <= not KEY(1);
+	s_mSet <= not KEY(0);
+										
+	clk_div_4hz : entity work.ClkDividerN(RTL)
+							generic map(k			=> 12500000)
+							port map(clkIn			=> CLOCK_50,
+										clkOut		=> s_clk4Hz);
+
+	clk_enb_gen : entity work.ClkEnableGenerator(RTL)
+							port map(clkIn4Hz		=> s_clk4Hz,
+										mode			=> s_mode,
+										clkEnable	=> s_globalEnb,
+										tick1Hz		=> LEDG(8));
+
+	s_sUnitsEnb	<= '1'; 
+
+	s_units_cnt : entity work.Counter4Bits(RTL)
+							port map(MAX	=> 9,
+										reset		=> s_sReset,
+										clk		=> s_clk4Hz,
+										enable1	=> s_globalEnb,
+										enable2	=> s_sUnitsEnb,
+										valOut	=> s_sUnitsBin,
+										termCnt	=> s_sUnitsTerm);
+
+	s_sTensEnb <= s_sUnitsTerm;
+
+	s_tens_cnt : entity work.Counter4Bits(RTL)
+							port map(MAX	=> 5,
+										reset		=> s_sReset,
+										clk		=> s_clk4Hz,
+										enable1	=> s_globalEnb,
+										enable2	=> s_sTensEnb,
+										valOut	=> s_sTensBin,
+										termCnt	=> s_sTensTerm);
+
+	s_mUnitsEnb <= ((s_sTensTerm and s_sUnitsTerm) and not s_mode) or
+						(s_mode and s_mSet);
+
+	m_units_cnt : entity work.Counter4Bits(RTL)
+							port map(MAX => 9,
+										reset		=> s_globalRst,
+										clk		=> s_clk4Hz,
+										enable1	=> s_globalEnb,
+										enable2	=> s_mUnitsEnb,
+										valOut	=> s_mUnitsBin,
+										termCnt	=> s_mUnitsTerm);
+
+	s_mTensEnb <= (s_mUnitsTerm and s_mUnitsEnb);
+
+	m_tens_cnt : entity work.Counter4Bits(RTL)
+							port map(MAX	=> 5,
+										reset		=> s_globalRst,
+										clk		=> s_clk4Hz,
+										enable1	=> s_globalEnb,
+										enable2	=> s_mTensEnb,
+										valOut	=> s_mTensBin,
+										termCnt	=> s_mTensTerm);
+
+	s_hUnitsEnb <= ((s_mTensTerm and s_mTensEnb) and not s_mode) or
+						(s_mode and s_hSet);
+						
+	s_hUnitsMax <= 3 when (s_hTensBin = "0010") else 9;
+
+	h_units_cnt : entity work.Counter4Bits(RTL)
+							port map(MAX	=> s_hUnitsMax,
+										reset		=> s_globalRst,
+										clk		=> s_clk4Hz,
+										enable1	=> s_globalEnb,
+										enable2	=> s_hUnitsEnb,
+										valOut	=> s_hUnitsBin,
+										termCnt	=> s_hUnitsTerm);
+
+	s_hTensEnb <= (s_hUnitsTerm and s_hUnitsEnb);
+
+	h_tens_cnt : entity work.Counter4Bits(RTL)
+							port map(MAX	=> 2,
+										reset		=> s_globalRst,
+										clk		=> s_clk4Hz,
+										enable1	=> s_globalEnb,
+										enable2	=> s_hTensEnb,
+										valOut	=> s_hTensBin,
+										termCnt	=> open);
+
+	s_units_decod : entity work.Bin7SegDecoder(RTL)
+							port map(enable	=> s_enable,
+										binInput	=> s_sUnitsBin,
+										decOut_n	=> HEX2);
+
+	s_tens_decod : entity work.Bin7SegDecoder(RTL)
+							port map(enable	=> s_enable,
+										binInput	=> s_sTensBin,
+										decOut_n	=> HEX3);
+
+	m_units_decod : entity work.Bin7SegDecoder(RTL)
+							port map(enable	=> s_enable,
+										binInput	=> s_mUnitsBin,
+										decOut_n	=> HEX4);
+
+	m_tens_decod : entity work.Bin7SegDecoder(RTL)
+							port map(enable	=> s_enable,
+										binInput	=> s_mTensBin,
+										decOut_n	=> HEX5);
+
+	h_units_decod : entity work.Bin7SegDecoder(RTL)
+							port map(enable	=> s_enable,
+										binInput	=> s_hUnitsBin,
+										decOut_n	=> HEX6);
+
+	h_tens_decod : entity work.Bin7SegDecoder(RTL)
+							port map(enable	=> s_enable,
+										binInput	=> s_hTensBin,
+										decOut_n	=> HEX7);
+end Structural;
diff --git a/1ano/2semestre/lsd/pratica05/BasicWatch/Bin7SegDecoder.vhd b/1ano/2semestre/lsd/pratica05/BasicWatch/Bin7SegDecoder.vhd
new file mode 100644
index 0000000..bf0c9c4
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica05/BasicWatch/Bin7SegDecoder.vhd
@@ -0,0 +1,35 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity Bin7SegDecoder is
+	port(enable		: in  std_logic;
+		 binInput	: in  std_logic_vector(3 downto 0);
+		 decOut_n	: out std_logic_vector(6 downto 0));
+end Bin7SegDecoder;
+
+architecture RTL of Bin7SegDecoder is
+
+	signal s_decOut_n : std_logic_vector(6 downto 0);
+
+begin
+	with binInput select
+		s_decOut_n <= "1111001" when "0001",   --1
+						  "0100100" when "0010",   --2
+						  "0110000" when "0011",   --3
+						  "0011001" when "0100",   --4
+						  "0010010" when "0101",   --5
+						  "0000010" when "0110",   --6
+						  "1111000" when "0111",   --7
+						  "0000000" when "1000",   --8
+						  "0010000" when "1001",   --9
+						  "0001000" when "1010",   --A
+						  "0000011" when "1011",   --b
+						  "1000110" when "1100",   --C
+						  "0100001" when "1101",   --d
+						  "0000110" when "1110",   --E
+						  "0001110" when "1111",   --F
+						  "1000000" when others;   --0
+
+	decOut_n <= s_decOut_n when (enable = '1') else
+				"0111111";
+end RTL;
diff --git a/1ano/2semestre/lsd/pratica05/BasicWatch/ClkDividerN.vhd b/1ano/2semestre/lsd/pratica05/BasicWatch/ClkDividerN.vhd
new file mode 100644
index 0000000..00cd9d6
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica05/BasicWatch/ClkDividerN.vhd
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity ClkDividerN is
+	generic(k 	: natural);
+	port(clkIn	: in  std_logic;
+		  clkOut	: out std_logic);
+end ClkDividerN;
+
+architecture RTL of ClkDividerN is
+
+	signal s_divCounter : natural;
+
+begin
+	assert(K >= 2);
+	
+	process(clkIn)
+	begin
+		if (rising_edge(clkIn)) then
+			if (s_divCounter = k - 1) then
+				clkOut		 <= '0';
+				s_divCounter <= 0;
+			else
+				if (s_divCounter = (k / 2 - 1)) then
+					clkOut	 <= '1';
+				end if;
+				s_divCounter <= s_divCounter + 1;
+			end if;
+		end if;
+	end process;
+end RTL;
diff --git a/1ano/2semestre/lsd/pratica05/BasicWatch/ClkEnableGenerator.vhd b/1ano/2semestre/lsd/pratica05/BasicWatch/ClkEnableGenerator.vhd
new file mode 100644
index 0000000..2c0d307
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica05/BasicWatch/ClkEnableGenerator.vhd
@@ -0,0 +1,29 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity ClkEnableGenerator is
+	port(clkIn4Hz	: in  std_logic;
+		  mode		: in  std_logic;
+		  clkEnable	: out std_logic;
+		  tick1Hz	: out std_logic);
+end ClkEnableGenerator;
+
+architecture RTL of ClkEnableGenerator is
+
+	signal s_counter : unsigned(1 downto 0);
+
+begin
+	process(clkIn4Hz)
+	begin
+		if (rising_edge(clkIn4Hz)) then
+			s_counter <= s_counter + 1;
+		end if;
+	end process;
+	
+	clkEnable <= '1' when (mode ='1') else
+					 '1' when (mode ='0') and (s_counter = "00") else
+					 '0';
+
+	tick1Hz	<= s_counter(1);
+end RTL;
diff --git a/1ano/2semestre/lsd/pratica05/BasicWatch/Counter4Bits.vhd b/1ano/2semestre/lsd/pratica05/BasicWatch/Counter4Bits.vhd
new file mode 100644
index 0000000..45bd67a
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica05/BasicWatch/Counter4Bits.vhd
@@ -0,0 +1,43 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity Counter4Bits is
+	port(MAX		: natural := 9;
+		  reset		: in  std_logic;
+		  clk			: in  std_logic;
+		  enable1	: in  std_logic;
+		  enable2	: in  std_logic;
+		  valOut		: out std_logic_vector(3 downto 0);
+		  termCnt	: out std_logic);
+end Counter4Bits;
+
+architecture RTL of Counter4Bits is
+
+	signal s_value : unsigned(3 downto 0);
+
+begin
+	process(reset, clk)
+	begin	
+		if (rising_edge(clk)) then
+			if (reset = '1') then
+				s_value <= (others => '0');
+				termCnt <= '0';
+			elsif ((enable1 = '1') and (enable2 = '1')) then
+				if (to_integer(s_value) = MAX) then
+					s_value <= (others => '0');
+					termCnt <= '0';
+				else
+					s_value <= s_value + 1;
+					if (to_integer(s_value) = MAX - 1) then
+						termCnt <= '1';
+					else
+						termCnt <= '0';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	valOut <= std_logic_vector(s_value);
+end RTL;
diff --git a/1ano/2semestre/lsd/pratica05/BasicWatch/output_files/BasicWatch.sof b/1ano/2semestre/lsd/pratica05/BasicWatch/output_files/BasicWatch.sof
new file mode 100644
index 0000000..ba81490
Binary files /dev/null and b/1ano/2semestre/lsd/pratica05/BasicWatch/output_files/BasicWatch.sof differ
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.bsf b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.bsf
new file mode 100644
index 0000000..b3344f5
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.bsf
@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 160 96)
+	(text "FreqDivider" (rect 5 0 52 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clkIn" (rect 0 0 17 12)(font "Arial" ))
+		(text "clkIn" (rect 21 27 38 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "clkOut" (rect 0 0 24 12)(font "Arial" ))
+		(text "clkOut" (rect 99 27 123 39)(font "Arial" ))
+		(line (pt 144 32)(pt 128 32)(line_width 1))
+	)
+	(parameter
+		"divFactor"
+		"10"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(rectangle (rect 16 16 128 64)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 160 -64 260 16))
+)
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.vhd b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.vhd
new file mode 100644
index 0000000..e79de6d
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.vhd
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity FreqDivider is
+	generic(divFactor : positive := 10);
+	port
+	(
+		clkIn  : in  std_logic;
+		clkOut : out std_logic
+	);
+end FreqDivider;
+
+architecture Behavioral of FreqDivider is
+	subtype TCounter is natural range 0 to divFactor - 1;
+	signal s_divCounter : TCounter := 0;
+begin
+    assert(divFactor >= 2);
+	process(clkIn)
+	begin
+		if (rising_edge(clkIn)) then
+			if (s_divCounter >= (divFactor - 1)) then
+				clkOut <= '0';
+				s_divCounter <= 0;
+			else
+				if (s_divCounter = (divFactor / 2 - 1)) then
+					clkOut <= '1';
+				end if;
+				s_divCounter <= s_divCounter + 1;
+			end if;
+		end if;
+	end process;
+end Behavioral;
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.bsf b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.bsf
new file mode 100644
index 0000000..a6512c6
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.bsf
@@ -0,0 +1,93 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 208 192)
+	(text "SeqShiftUnit" (rect 5 0 53 12)(font "Arial" ))
+	(text "inst" (rect 8 160 20 172)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "dataIn[7..0]" (rect 0 0 43 12)(font "Arial" ))
+		(text "dataIn[7..0]" (rect 21 43 64 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "siLeft" (rect 0 0 22 12)(font "Arial" ))
+		(text "siLeft" (rect 21 59 43 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "siRight" (rect 0 0 27 12)(font "Arial" ))
+		(text "siRight" (rect 21 75 48 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "loadEn" (rect 0 0 27 12)(font "Arial" ))
+		(text "loadEn" (rect 21 91 48 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "rotate" (rect 0 0 22 12)(font "Arial" ))
+		(text "rotate" (rect 21 107 43 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 1))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "dirLeft" (rect 0 0 25 12)(font "Arial" ))
+		(text "dirLeft" (rect 21 123 46 135)(font "Arial" ))
+		(line (pt 0 128)(pt 16 128)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "shArith" (rect 0 0 29 12)(font "Arial" ))
+		(text "shArith" (rect 21 139 50 151)(font "Arial" ))
+		(line (pt 0 144)(pt 16 144)(line_width 1))
+	)
+	(port
+		(pt 192 32)
+		(output)
+		(text "dataOut[7..0]" (rect 0 0 50 12)(font "Arial" ))
+		(text "dataOut[7..0]" (rect 121 27 171 39)(font "Arial" ))
+		(line (pt 192 32)(pt 176 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 176 160)(line_width 1))
+	)
+)
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vhd b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vhd
new file mode 100644
index 0000000..457132f
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vhd
@@ -0,0 +1,52 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity SeqShiftUnit is
+	port
+	(
+		clk     : in  std_logic;
+		dataIn  : in  std_logic_vector(7 downto 0);
+		siLeft  : in  std_logic;
+		siRight : in  std_logic;
+		loadEn  : in  std_logic;
+		rotate  : in  std_logic;
+		dirLeft : in  std_logic;
+		shArith : in  std_logic;
+		dataOut : out std_logic_vector(7 downto 0)
+	);
+end SeqShiftUnit;
+
+architecture Behavioral of SeqShiftUnit is
+	signal s_shiftReg : std_logic_vector(7 downto 0);
+begin
+	process (clk)
+	begin
+		if (falling_edge(clk)) then
+			if (loadEn = '1') then
+				s_shiftReg <= dataIn;
+			
+			elsif (rotate = '1') then
+				if (dirLeft = '1') then
+					s_shiftReg <= s_shiftReg(6 downto 0) & s_shiftReg(7);
+				else
+					s_shiftReg <= s_shiftReg(0) & s_shiftReg(7 downto 1);
+				end if;
+				
+			elsif (shArith = '1') then
+				if (dirLeft = '1') then 
+					s_shiftReg <= s_shiftReg(6 downto 0) & '0'; 
+				else
+					s_shiftReg <= s_shiftReg(7) & s_shiftReg(7 downto 1); 
+				end if;
+			
+			else
+				if (dirLeft = '1') then
+					s_shiftReg <= s_shiftReg(6 downto 0) & siLeft;
+				else
+					s_shiftReg <= siRight & s_shiftReg(7 downto 1);
+				end if;
+			end if;
+		end if;
+	end process;
+	dataOut <= s_ShiftReg;
+end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf
new file mode 100644
index 0000000..5a6f4b5
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf
@@ -0,0 +1,872 @@
+/*<simulation_settings>
+<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off SeqShiftUnit_Demo -c SeqShiftUnit_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/SeqShiftUnit.vwf.vht"</ftestbench_cmd>
+<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off SeqShiftUnit_Demo -c SeqShiftUnit_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/SeqShiftUnit.vwf.vht"</ttestbench_cmd>
+<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/" SeqShiftUnit_Demo -c SeqShiftUnit_Demo</fnetlist_cmd>
+<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/" SeqShiftUnit_Demo -c SeqShiftUnit_Demo</tnetlist_cmd>
+<modelsim_script>onerror {exit -code 1}
+vlib work
+vcom -work work SeqShiftUnit_Demo.vho
+vcom -work work SeqShiftUnit.vwf.vht
+vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.SeqShiftUnit_vhd_vec_tst
+vcd file -direction SeqShiftUnit_Demo.msim.vcd
+vcd add -internal SeqShiftUnit_vhd_vec_tst/*
+vcd add -internal SeqShiftUnit_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+    echo "Simulation time: $::now ps"
+    if { [string equal running [runStatus]] } {
+        after 2500 simTimestamp
+    }
+}
+after 2500 simTimestamp
+run -all
+quit -f
+
+</modelsim_script>
+<modelsim_script_timing>onerror {exit -code 1}
+vlib work
+vcom -work work SeqShiftUnit_Demo.vho
+vcom -work work SeqShiftUnit.vwf.vht
+vsim -novopt -c -t 1ps -sdfmax SeqShiftUnit_vhd_vec_tst/i1=SeqShiftUnit_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.SeqShiftUnit_vhd_vec_tst
+vcd file -direction SeqShiftUnit_Demo.msim.vcd
+vcd add -internal SeqShiftUnit_vhd_vec_tst/*
+vcd add -internal SeqShiftUnit_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+    echo "Simulation time: $::now ps"
+    if { [string equal running [runStatus]] } {
+        after 2500 simTimestamp
+    }
+}
+after 2500 simTimestamp
+run -all
+quit -f
+
+</modelsim_script_timing>
+<hdl_lang>vhdl</hdl_lang>
+</simulation_settings>*/
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+
+HEADER
+{
+	VERSION = 1;
+	TIME_UNIT = ns;
+	DATA_OFFSET = 0.0;
+	DATA_DURATION = 1000.0;
+	SIMULATION_TIME = 0.0;
+	GRID_PHASE = 0.0;
+	GRID_PERIOD = 10.0;
+	GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("clk")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("dataIn")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 8;
+	LSB_INDEX = 0;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("dataIn[7]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[6]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "dataIn";
+}
+
+SIGNAL("dirLeft")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("loadEn")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("rotate")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("shArith")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("siLeft")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("siRight")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = INPUT;
+	PARENT = "";
+}
+
+SIGNAL("dataOut")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = BUS;
+	WIDTH = 8;
+	LSB_INDEX = 0;
+	DIRECTION = OUTPUT;
+	PARENT = "";
+}
+
+SIGNAL("dataOut[7]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[6]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[5]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[4]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[3]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[2]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[1]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[0]")
+{
+	VALUE_TYPE = NINE_LEVEL_BIT;
+	SIGNAL_TYPE = SINGLE_BIT;
+	WIDTH = 1;
+	LSB_INDEX = -1;
+	DIRECTION = OUTPUT;
+	PARENT = "dataOut";
+}
+
+TRANSITION_LIST("clk")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 100;
+			LEVEL 0 FOR 5.0;
+			LEVEL 1 FOR 5.0;
+		}
+	}
+}
+
+TRANSITION_LIST("dataIn[7]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("dataIn[6]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("dataIn[5]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("dataIn[4]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("dataIn[3]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("dataIn[2]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("dataIn[1]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("dataIn[0]")
+{
+	NODE
+	{
+		REPEAT = 1;
+		LEVEL 0 FOR 1000.0;
+	}
+}
+
+TRANSITION_LIST("dirLeft")
+{
+	NODE
+	{
+		REPEAT = 1;
+		NODE
+		{
+			REPEAT = 25;
+			LEVEL 0 FOR 20.0;
+			LEVEL 1 FOR 20.0;
+		}
+	}
+}
+
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diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit_Demo.bdf b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit_Demo.bdf
new file mode 100644
index 0000000..e202bfb
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit_Demo.bdf
@@ -0,0 +1,350 @@
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+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
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+	(pt 264 248)
+)
+(connector
+	(pt 424 264)
+	(pt 264 264)
+)
+(connector
+	(pt 424 280)
+	(pt 264 280)
+)
+(connector
+	(pt 424 296)
+	(pt 264 296)
+)
+(connector
+	(pt 424 312)
+	(pt 264 312)
+)
+(connector
+	(pt 424 328)
+	(pt 264 328)
+)
+(connector
+	(pt 616 216)
+	(pt 624 216)
+	(bus)
+)
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/output_files/SeqShiftUnit_Demo.sof b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/output_files/SeqShiftUnit_Demo.sof
new file mode 100644
index 0000000..b2b8648
Binary files /dev/null and b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/output_files/SeqShiftUnit_Demo.sof differ
diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Bin7SegDecoder.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Bin7SegDecoder.vhd
new file mode 100644
index 0000000..96f7b6b
--- /dev/null
+++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Bin7SegDecoder.vhd
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity Bin7SegDecoder is
+	port
+	(
+		binInput : in  std_logic_vector(3 downto 0);
+		enable   : in  std_logic;
+		decOut_n : out std_logic_vector(6 downto 0)
+	);
+end Bin7SegDecoder;
+
+architecture Behavioral of Bin7SegDecoder is
+begin
+	decOut_n <= "1111111" when (enable   = '0'   ) else -- disabled
+	            "1111001" when (binInput = "0001") else --1
+					"0100100" when (binInput = "0010") else --2
+					"0110000" when (binInput = "0011") else --3
+					"0011001" when (binInput = "0100") else --4
+					"0010010" when (binInput = "0101") else --5
+					"0000010" when (binInput = "0110") else --6
+					"1111000" when (binInput = "0111") else --7
+					"0000000" when (binInput = "1000") else --8
+					"0010000" when (binInput = "1001") else --9
+					"0001000" when (binInput = "1010") else --A
+					"0000011" when (binInput = "1011") else --b
+					"1000110" when (binInput = "1100") else --C
+					"0100001" when (binInput = "1101") else --d
+					"0000110" when (binInput = "1110") else --E
+					"0001110" when (binInput = "1111") else --F
+					"1000000"; --0
+end Behavioral;
diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Counter.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Counter.vhd
new file mode 100644
index 0000000..467fcc4
--- /dev/null
+++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Counter.vhd
@@ -0,0 +1,42 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity Counter is
+	port
+	(
+		clk   : in  std_logic;
+		reset : in  std_logic;
+		count : out std_logic_vector(3 downto 0)
+	);
+end Counter;
+
+architecture Behavioral of Counter is
+	signal up : std_logic := '1';
+	signal s_count : unsigned(3 downto 0) := to_unsigned(0, 4);
+begin
+	process(clk, reset)
+	begin
+		if (reset = '1') then
+			s_count <= to_unsigned(0, 4);
+			up <= '1';
+		elsif (rising_edge(clk)) then
+			if (up = '1') then
+				if (std_logic_vector(s_count) = "1111") then
+					s_count <= s_count - 1;
+					up <= '0';
+				else
+					s_count <= s_count + 1;
+				end if;
+			else
+				if (std_logic_vector(s_count) = "0000") then
+					s_count <= s_count + 1;
+					up <= '1';
+				else
+					s_count <= s_count - 1;
+				end if;
+			end if;
+		end if;
+	end process;
+	count <= std_logic_vector(s_count);
+end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/FreqDivider.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/FreqDivider.vhd
new file mode 100644
index 0000000..a0b77ec
--- /dev/null
+++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/FreqDivider.vhd
@@ -0,0 +1,36 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity FreqDivider is
+	generic(divFactor : positive := 10);
+	port
+	(
+		clkIn  : in  std_logic;
+		multi  : in  positive := 1;
+		clkOut : out std_logic
+	);
+end FreqDivider;
+
+architecture Behavioral of FreqDivider is
+	subtype TCounter is natural range 0 to divFactor - 1;
+	signal s_divFactor  : positive := 10;
+	signal s_divCounter : TCounter := 0;
+begin
+	s_divFactor <= divFactor / multi;
+   assert(divFactor >= 2);
+	process(clkIn)
+	begin
+		if (rising_edge(clkIn)) then
+			if (s_divCounter >= (s_divFactor - 1)) then
+				clkOut <= '0';
+				s_divCounter <= 0;
+			else
+				if (s_divCounter = (s_divFactor / 2 - 1)) then
+					clkOut <= '1';
+				end if;
+				s_divCounter <= s_divCounter + 1;
+			end if;
+		end if;
+	end process;
+end Behavioral;
diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/HexToDec4Bit.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/HexToDec4Bit.vhd
new file mode 100644
index 0000000..c0f8f1a
--- /dev/null
+++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/HexToDec4Bit.vhd
@@ -0,0 +1,80 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity HexToDec4Bit is
+	port
+	(
+		hexIn   : in  std_logic_vector(3 downto 0);
+		cin     : in  std_logic;
+		decOut0 : out std_logic_vector(3 downto 0);
+		decOut1 : out std_logic_vector(3 downto 0)
+	);
+end HexToDec4Bit;
+
+architecture Behavioral of HexToDec4Bit is
+begin
+	process (hexIn, cin) is
+	begin
+		if cin = '1' then
+			if hexIn = "0000" then
+				decOut0 <= "0110";
+			elsif hexIn = "0001" then
+				decOut0 <= "0111";
+			elsif hexIn = "0010" then
+				decOut0 <= "1000";
+			elsif hexIn = "0011" then
+				decOut0 <= "1001";
+			elsif hexIn = "0100" then
+				decOut0 <= "0000";
+			elsif hexIn = "0101" then
+				decOut0 <= "0001";
+			elsif hexIn = "0110" then
+				decOut0 <= "0010";
+			elsif hexIn = "0111" then
+				decOut0 <= "0011";
+			elsif hexIn = "1000" then
+				decOut0 <= "0100";
+			elsif hexIn = "1001" then
+				decOut0 <= "0101";
+			elsif hexIn = "1010" then
+				decOut0 <= "0110";
+			elsif hexIn = "1011" then
+				decOut0 <= "0111";
+			elsif hexIn = "1100" then
+				decOut0 <= "1000";
+			elsif hexIn = "1101" then
+				decOut0 <= "1001";
+			else
+				decOut0 <= "0000";
+			end if;
+			
+			if hexIn < "0100" then
+				decOut1 <= "0001";
+			elsif hexIn < "1110" then
+				decOut1 <= "0010";
+			else
+				decOut1 <= "0011";
+			end if;
+		else
+			if hexIn < "1010" then
+				decOut0 <= hexIn;
+				decOut1 <= "0000";
+			else
+				if hexIn = "1010" then
+					decOut0 <= "0000";
+				elsif hexIn = "1011" then
+					decOut0 <= "0001";
+				elsif hexIn = "1100" then
+					decOut0 <= "0010";
+				elsif hexIn = "1101" then
+					decOut0 <= "0011";
+				elsif hexIn = "1110" then
+					decOut0 <= "0100";
+				else
+					decOut0 <= "0101";
+				end if;
+				decOut1 <= "0001";
+			end if;
+		end if;
+	end process;
+end Behavioral;
diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/LedDisplayer.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/LedDisplayer.vhd
new file mode 100644
index 0000000..02788c8
--- /dev/null
+++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/LedDisplayer.vhd
@@ -0,0 +1,31 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity LedDisplayer is
+	port
+	(
+		count  : in  std_logic_vector(3  downto 0);
+		ledOut : out std_logic_vector(14 downto 0)
+	);
+end LedDisplayer;
+
+architecture Behavioral of LedDisplayer is
+begin
+	with count select
+		ledOut <= "000000000000000" when "0000",
+					 "000000000000001" when "0001",
+					 "000000000000011" when "0010",
+					 "000000000000111" when "0011",
+					 "000000000001111" when "0100",
+					 "000000000011111" when "0101",
+					 "000000000111111" when "0110",
+					 "000000001111111" when "0111",
+					 "000000011111111" when "1000",
+					 "000000111111111" when "1001",
+					 "000001111111111" when "1010",
+					 "000011111111111" when "1011",
+					 "000111111111111" when "1100",
+					 "001111111111111" when "1101",
+					 "011111111111111" when "1110",
+					 "111111111111111" when "1111";
+end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/MiniProj_Demo.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/MiniProj_Demo.vhd
new file mode 100644
index 0000000..b5669ef
--- /dev/null
+++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/MiniProj_Demo.vhd
@@ -0,0 +1,84 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity MiniProj_Demo is
+	port
+	(
+		CLOCK_50 : in  std_logic;
+		KEY      : in  std_logic_vector(1  downto 0);
+		LEDR     : out std_logic_vector(14 downto 0);
+		HEX0     : out std_logic_vector(6  downto 0);
+		HEX1     : out std_logic_vector(6  downto 0)
+	);
+end MiniProj_Demo;
+
+architecture Shell of MiniProj_Demo is
+	signal s_clk_def, s_clk_div : std_logic;
+	signal s_speed : positive := 4;
+	signal s_reset : std_logic;
+
+	signal s_count : std_logic_vector(3 downto 0);
+	
+	signal s_display0, s_display1 : std_logic_vector(3 downto 0);
+begin
+	s_clk_def <= CLOCK_50;
+	s_reset   <= not KEY(0);
+
+	speed_select : entity work.SpeedSelect(Behavioral)
+	port map
+	(
+		toggle => not KEY(1),
+		reset  => s_reset,
+		speed  => s_speed
+	);
+	
+	freq_divider : entity work.FreqDivider(Behavioral)
+	generic map (divFactor => 50_000_000)
+	port map
+	(
+		clkIn  => s_clk_def,
+		multi  => s_speed,
+		clkOut => s_clk_div
+	);
+	
+	counter : entity work.Counter(Behavioral)
+	port map
+	(
+		clk   => s_clk_div,
+		reset => s_reset,
+		count => s_count
+	);
+	
+	led_display : entity work.LedDisplayer(Behavioral)
+	port map
+	(
+		count  => s_count,
+		ledOut => LEDR
+	);
+
+	hex_to_dec : entity work.HexToDec4Bit(Behavioral)
+	port map
+	(
+		hexIn   => s_count,
+		cin     => '0',
+		decOut0 => s_display0,
+		decOut1 => s_display1
+	);
+	
+	display0 : entity work.Bin7SegDecoder(Behavioral)
+	port map
+	(
+		enable   => '1',
+		binInput => s_display0,
+		decOut_n => HEX0
+	);
+	
+	display1 : entity work.Bin7SegDecoder(Behavioral)
+	port map
+	(
+		enable   => '1',
+		binInput => s_display1,
+		decOut_n => HEX1
+	);
+	
+end Shell;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/SpeedSelect.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/SpeedSelect.vhd
new file mode 100644
index 0000000..3377c4b
--- /dev/null
+++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/SpeedSelect.vhd
@@ -0,0 +1,31 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity SpeedSelect is
+	port
+	(
+		toggle : in  std_logic;
+		reset  : in  std_logic;
+		speed  : out positive := 4
+	);
+end SpeedSelect;
+
+architecture Behavioral of SpeedSelect is
+	signal current_speed : positive := 4;
+begin
+	process(toggle, reset)
+	begin
+		if (reset = '1') then
+			current_speed <= 4;
+		else
+			if (toggle = '1') then
+				if (current_speed = 1) then
+					current_speed <= 4;
+				else
+					current_speed <= 1;
+				end if;
+			end if;
+		end if;
+	end process;
+	speed <= current_speed;
+end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/output_files/MiniProj_Demo.sof b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/output_files/MiniProj_Demo.sof
new file mode 100644
index 0000000..ba44e70
Binary files /dev/null and b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/output_files/MiniProj_Demo.sof differ