From f47c2ef9b7afab116089e8cc77db9757e28e2539 Mon Sep 17 00:00:00 2001 From: TiagoRG <35657250+TiagoRG@users.noreply.github.com> Date: Tue, 21 Mar 2023 22:41:33 +0000 Subject: [PATCH] [LSD] pratica05 part1 added --- .../lsd/pratica05/CmpN_Demo/Cmp8.vwf | 733 +++++ .../lsd/pratica05/CmpN_Demo/CmpN.bsf | 78 + .../lsd/pratica05/CmpN_Demo/CmpN.vhd | 24 + .../lsd/pratica05/CmpN_Demo/CmpN.vhd.bak | 21 + .../lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf | 390 +++ .../lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf | 31 + .../lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf | 585 ++++ .../lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak | 585 ++++ .../lsd/pratica05/CmpN_Demo/CmpN_Demo.qws | Bin 0 -> 2491 bytes .../CmpN_Demo/db/CmpN_Demo.(0).cnf.cdb | Bin 0 -> 1298 bytes .../CmpN_Demo/db/CmpN_Demo.(0).cnf.hdb | Bin 0 -> 859 bytes .../CmpN_Demo/db/CmpN_Demo.(1).cnf.cdb | Bin 0 -> 1333 bytes .../CmpN_Demo/db/CmpN_Demo.(1).cnf.hdb | Bin 0 -> 765 bytes .../CmpN_Demo/db/CmpN_Demo.(2).cnf.cdb | Bin 0 -> 1328 bytes .../CmpN_Demo/db/CmpN_Demo.(2).cnf.hdb | Bin 0 -> 868 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.asm.qmsg | 7 + .../pratica05/CmpN_Demo/db/CmpN_Demo.asm.rdb | Bin 0 -> 824 bytes .../CmpN_Demo/db/CmpN_Demo.asm_labs.ddb | Bin 0 -> 89331 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml | 5 + .../pratica05/CmpN_Demo/db/CmpN_Demo.cmp.bpm | Bin 0 -> 836 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.cmp.cdb | Bin 0 -> 8229 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.cmp.hdb | Bin 0 -> 27249 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.cmp.idb | Bin 0 -> 1325 bytes .../CmpN_Demo/db/CmpN_Demo.cmp.logdb | 68 + .../pratica05/CmpN_Demo/db/CmpN_Demo.cmp.rdb | Bin 0 -> 32374 bytes .../CmpN_Demo/db/CmpN_Demo.cmp_merge.kpt | Bin 0 -> 208 bytes ...ve_io_sim_cache.45um_ff_1200mv_0c_fast.hsd | Bin 0 -> 746429 bytes ...ve_io_sim_cache.45um_ii_1200mv_0c_slow.hsd | Bin 0 -> 749613 bytes ...e_io_sim_cache.45um_ii_1200mv_85c_slow.hsd | Bin 0 -> 749512 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.db_info | 3 + .../pratica05/CmpN_Demo/db/CmpN_Demo.eda.qmsg | 6 + .../pratica05/CmpN_Demo/db/CmpN_Demo.fit.qmsg | 48 + .../CmpN_Demo/db/CmpN_Demo.hier_info | 97 + .../lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hif | Bin 0 -> 509 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.lpc.html | 50 + .../pratica05/CmpN_Demo/db/CmpN_Demo.lpc.rdb | Bin 0 -> 466 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.lpc.txt | 8 + .../CmpN_Demo/db/CmpN_Demo.map.ammdb | Bin 0 -> 129 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.map.bpm | Bin 0 -> 811 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.map.cdb | Bin 0 -> 3970 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.map.hdb | Bin 0 -> 26344 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.map.kpt | Bin 0 -> 207 bytes .../CmpN_Demo/db/CmpN_Demo.map.logdb | 1 + .../pratica05/CmpN_Demo/db/CmpN_Demo.map.qmsg | 14 + .../pratica05/CmpN_Demo/db/CmpN_Demo.map.rdb | Bin 0 -> 1336 bytes .../CmpN_Demo/db/CmpN_Demo.map_bb.cdb | Bin 0 -> 2178 bytes .../CmpN_Demo/db/CmpN_Demo.map_bb.hdb | Bin 0 -> 24948 bytes .../CmpN_Demo/db/CmpN_Demo.map_bb.logdb | 1 + .../CmpN_Demo/db/CmpN_Demo.pre_map.hdb | Bin 0 -> 25909 bytes .../CmpN_Demo.root_partition.map.reg_db.cdb | Bin 0 -> 223 bytes .../CmpN_Demo/db/CmpN_Demo.routing.rdb | Bin 0 -> 31584 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.rtlv.hdb | Bin 0 -> 25766 bytes .../CmpN_Demo/db/CmpN_Demo.rtlv_sg.cdb | Bin 0 -> 2359 bytes .../CmpN_Demo/db/CmpN_Demo.rtlv_sg_swap.cdb | Bin 0 -> 835 bytes .../db/CmpN_Demo.sld_design_entry.sci | Bin 0 -> 225 bytes .../db/CmpN_Demo.sld_design_entry_dsc.sci | Bin 0 -> 225 bytes .../CmpN_Demo/db/CmpN_Demo.smart_action.txt | 1 + .../pratica05/CmpN_Demo/db/CmpN_Demo.sta.qmsg | 49 + .../pratica05/CmpN_Demo/db/CmpN_Demo.sta.rdb | Bin 0 -> 6693 bytes .../CmpN_Demo.sta_cmp.7_slow_1200mv_85c.tdb | Bin 0 -> 6914 bytes .../CmpN_Demo/db/CmpN_Demo.tis_db_list.ddb | Bin 0 -> 294 bytes .../db/CmpN_Demo.tiscmp.fast_1200mv_0c.ddb | Bin 0 -> 120861 bytes .../db/CmpN_Demo.tiscmp.slow_1200mv_0c.ddb | Bin 0 -> 121280 bytes .../db/CmpN_Demo.tiscmp.slow_1200mv_85c.ddb | Bin 0 -> 120936 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.tmw_info | 7 + .../CmpN_Demo/db/CmpN_Demo.vpr.ammdb | Bin 0 -> 313 bytes .../db/CmpN_Demo_partition_pins.json | 113 + .../CmpN_Demo/db/prev_cmp_CmpN_Demo.qmsg | 140 + .../pratica05/CmpN_Demo/incremental_db/README | 11 + .../compiled_partitions/CmpN_Demo.db_info | 3 + .../CmpN_Demo.root_partition.cmp.ammdb | Bin 0 -> 275 bytes .../CmpN_Demo.root_partition.cmp.cdb | Bin 0 -> 5106 bytes .../CmpN_Demo.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../CmpN_Demo.root_partition.cmp.hdb | Bin 0 -> 25906 bytes .../CmpN_Demo.root_partition.cmp.logdb | 1 + .../CmpN_Demo.root_partition.cmp.rcfdb | Bin 0 -> 3950 bytes .../CmpN_Demo.root_partition.map.cdb | Bin 0 -> 3551 bytes .../CmpN_Demo.root_partition.map.dpi | Bin 0 -> 865 bytes .../CmpN_Demo.root_partition.map.hbdb.cdb | Bin 0 -> 1597 bytes .../CmpN_Demo.root_partition.map.hbdb.hb_info | Bin 0 -> 46 bytes .../CmpN_Demo.root_partition.map.hbdb.hdb | Bin 0 -> 25197 bytes .../CmpN_Demo.root_partition.map.hbdb.sig | 1 + .../CmpN_Demo.root_partition.map.hdb | Bin 0 -> 24883 bytes .../CmpN_Demo.root_partition.map.kpt | Bin 0 -> 209 bytes .../compiled_partitions/CmpN_Demo.rrp.hdb | Bin 0 -> 27183 bytes .../CmpN_Demo/output_files/CmpN_Demo.asm.rpt | 92 + .../CmpN_Demo/output_files/CmpN_Demo.cdf | 13 + .../CmpN_Demo/output_files/CmpN_Demo.done | 1 + .../CmpN_Demo/output_files/CmpN_Demo.eda.rpt | 94 + .../CmpN_Demo/output_files/CmpN_Demo.fit.rpt | 2622 +++++++++++++++++ .../CmpN_Demo/output_files/CmpN_Demo.fit.smsg | 8 + .../output_files/CmpN_Demo.fit.summary | 16 + .../CmpN_Demo/output_files/CmpN_Demo.flow.rpt | 136 + .../CmpN_Demo/output_files/CmpN_Demo.jdi | 8 + .../CmpN_Demo/output_files/CmpN_Demo.map.rpt | 314 ++ .../output_files/CmpN_Demo.map.summary | 14 + .../CmpN_Demo/output_files/CmpN_Demo.pin | 851 ++++++ .../CmpN_Demo/output_files/CmpN_Demo.sld | 1 + .../CmpN_Demo/output_files/CmpN_Demo.sof | Bin 0 -> 3541729 bytes .../CmpN_Demo/output_files/CmpN_Demo.sta.rpt | 521 ++++ .../output_files/CmpN_Demo.sta.summary | 5 + .../simulation/modelsim/CmpN_Demo.sft | 1 + .../simulation/modelsim/CmpN_Demo.vho | 773 +++++ .../modelsim/CmpN_Demo_modelsim.xrf | 53 + .../CmpN_Demo/simulation/qsim/Cmp8.vwf.vht | 226 ++ .../CmpN_Demo/simulation/qsim/CmpN_Demo.do | 17 + .../CmpN_Demo/simulation/qsim/CmpN_Demo.sft | 1 + .../CmpN_Demo/simulation/qsim/CmpN_Demo.vho | 663 +++++ .../simulation/qsim/CmpN_Demo_modelsim.xrf | 50 + .../CmpN_Demo/simulation/qsim/transcript | 23 + .../CmpN_Demo/simulation/qsim/work/_info | 60 + .../CmpN_Demo/simulation/qsim/work/_lib.qdb | Bin 0 -> 49152 bytes .../simulation/qsim/work/_lib1_0.qdb | Bin 0 -> 32768 bytes .../simulation/qsim/work/_lib1_0.qpg | Bin 0 -> 237568 bytes .../simulation/qsim/work/_lib1_0.qtl | Bin 0 -> 8549 bytes .../CmpN_Demo/simulation/qsim/work/_vmake | 4 + 116 files changed, 9648 insertions(+) create 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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.pre_map.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.root_partition.map.reg_db.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.routing.rdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.rtlv.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.rtlv_sg.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.rtlv_sg_swap.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sld_design_entry.sci create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sld_design_entry_dsc.sci create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.smart_action.txt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta.qmsg create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta.rdb create mode 100644 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1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.pin create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sld create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sof create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sta.rpt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sta.summary create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.sft create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.vho create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo_modelsim.xrf create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.do create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.sft create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.vho create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo_modelsim.xrf create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/transcript create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_info create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_lib.qdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_lib1_0.qdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_lib1_0.qpg create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_lib1_0.qtl create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_vmake diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf new file mode 100644 index 0000000..4cf750b --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf @@ -0,0 +1,733 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CmpN_Demo -c CmpN_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht" +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CmpN_Demo -c CmpN_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/" CmpN_Demo -c CmpN_Demo +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/" CmpN_Demo -c CmpN_Demo +onerror {exit -code 1} +vlib work +vcom -work work CmpN_Demo.vho +vcom work Cmp8.vwf.vht +vsim -novopt -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CmpN_vhd_vec_tst +vcd file -direction CmpN_Demo.msim.vcd +vcd add -internal CmpN_vhd_vec_tst/* +vcd add -internal CmpN_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vcom -work work CmpN_Demo.vho +vcom -work work Cmp8.vwf.vht +vsim -novopt -c -t 1ps -sdfmax CmpN_vhd_vec_tst/i1=CmpN_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CmpN_vhd_vec_tst +vcd file -direction CmpN_Demo.msim.vcd +vcd add -internal CmpN_vhd_vec_tst/* +vcd add -internal CmpN_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +vhdl +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("equal") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("input0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("input0[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("input1[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("ltSigned") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("ltUnsigned") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("notEqual") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("equal") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("input0[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 840.0; + } +} + +TRANSITION_LIST("input0[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input1[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input1[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("ltSigned") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("ltUnsigned") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("notEqual") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "input0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; + CHILDREN = 10, 11, 12, 13, 14, 15, 16, 17; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "equal"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "notEqual"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ltSigned"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ltUnsigned"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.bsf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.bsf new file mode 100644 index 0000000..d3a6149 --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.bsf @@ -0,0 +1,78 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 208 128) + (text "CmpN" (rect 5 0 32 12)(font "Arial" )) + (text "inst" (rect 8 96 20 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "input0[n-1..0]" (rect 0 0 48 12)(font "Arial" )) + (text "input0[n-1..0]" (rect 21 27 69 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "input1[n-1..0]" (rect 0 0 47 12)(font "Arial" )) + (text "input1[n-1..0]" (rect 21 43 68 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 192 32) + (output) + (text "equal" (rect 0 0 20 12)(font "Arial" )) + (text "equal" (rect 151 27 171 39)(font "Arial" )) + (line (pt 192 32)(pt 176 32)(line_width 1)) + ) + (port + (pt 192 48) + (output) + (text "notEqual" (rect 0 0 34 12)(font "Arial" )) + (text "notEqual" (rect 137 43 171 55)(font "Arial" )) + (line (pt 192 48)(pt 176 48)(line_width 1)) + ) + (port + (pt 192 64) + (output) + (text "ltSigned" (rect 0 0 29 12)(font "Arial" )) + (text "ltSigned" (rect 142 59 171 71)(font "Arial" )) + (line (pt 192 64)(pt 176 64)(line_width 1)) + ) + (port + (pt 192 80) + (output) + (text "ltUnsigned" (rect 0 0 40 12)(font "Arial" )) + (text "ltUnsigned" (rect 131 75 171 87)(font "Arial" )) + (line (pt 192 80)(pt 176 80)(line_width 1)) + ) + (parameter + "N" + "4" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 176 96)(line_width 1)) + ) + (annotation_block (parameter)(rect 208 -64 308 16)) +) diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd new file mode 100644 index 0000000..deed67d --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd @@ -0,0 +1,24 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity CmpN is + generic (N : positive := 4); + port + ( + input0 : in std_logic_vector((N-1) downto 0); + input1 : in std_logic_vector((N-1) downto 0); + equal : out std_logic; + notEqual : out std_logic; + ltSigned : out std_logic; + ltUnsigned : out std_logic + ); +end CmpN; + +architecture Behavioral of CmpN is +begin + equal <= '1' when (input0 = input1) else '0'; + notEqual <= '1' when (input0 /= input1) else '0'; + ltSigned <= '1' when (signed(input0) < signed(input1)) else '0'; + ltUnsigned <= '1' when (unsigned(input0) < unsigned(input1)) else '0'; +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd.bak b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd.bak new file mode 100644 index 0000000..1193ba4 --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd.bak @@ -0,0 +1,21 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity Cmp4 is + port( + input0 : in std_logic_vector(3 downto 0); + input1 : in std_logic_vector(3 downto 0); + equal : out std_logic; + notEqual : out std_logic; + ltSigned : out std_logic; + ltUnsigned : out std_logic); +end Cmp4; + +architecture Behavioral of Cmp4 is +begin + equal <= '1' when (input0 = input1) else '0'; + notEqual <= '1' when (input0 /= input1) else '0'; + ltSigned <= '1' when (signed(input0) < signed(input1)) else '0'; + ltUnsigned <= '1' when (unsigned(input0) < unsigned(input1)) else '0'; +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf new file mode 100644 index 0000000..7ef32f1 --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf @@ -0,0 +1,390 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 424 240 592 256) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[7..4]" (rect 5 0 47 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 360 256 424 272)) +) +(pin + (input) + (rect 424 256 592 272) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[3..0]" (rect 5 0 48 13)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 360 272 424 288)) +) +(pin + (input) + (rect 424 408 592 424) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[17..13]" (rect 5 0 62 13)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 232 472 296 488)) +) +(pin + (input) + (rect 424 424 592 440) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[12..8]" (rect 5 0 56 13)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 232 488 296 504)) +) +(pin + (output) + (rect 800 240 976 256) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDG[0]" (rect 90 0 132 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 984 256 1048 272)) +) +(pin + (output) + (rect 800 256 976 272) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDG[1]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 976 272 1032 288)) +) +(pin + (output) + (rect 800 272 976 288) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDG[2]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 976 288 1032 304)) +) +(pin + (output) + (rect 800 288 976 304) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDG[3]" (rect 90 0 132 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 976 304 1032 320)) +) +(pin + (output) + (rect 800 408 976 424) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDR[0]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 856 472 920 488)) +) +(pin + (output) + (rect 800 424 976 440) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDR[1]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 848 488 904 504)) +) +(pin + (output) + (rect 800 440 976 456) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDR[2]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 848 504 904 520)) +) +(pin + (output) + (rect 800 456 976 472) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDR[3]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 848 520 904 536)) +) +(symbol + (rect 600 216 792 328) + (text "CmpN" (rect 5 0 36 11)(font "Arial" )) + (text "inst" (rect 8 96 26 107)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "input0[n-1..0]" (rect 0 0 64 11)(font "Arial" )) + (text "input0[n-1..0]" (rect 21 27 85 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "input1[n-1..0]" (rect 0 0 64 11)(font "Arial" )) + (text "input1[n-1..0]" (rect 21 43 85 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 192 32) + (output) + (text "equal" (rect 0 0 28 11)(font "Arial" )) + (text "equal" (rect 148 27 176 38)(font "Arial" )) + (line (pt 192 32)(pt 176 32)) + ) + (port + (pt 192 48) + (output) + (text "notEqual" (rect 0 0 44 11)(font "Arial" )) + (text "notEqual" (rect 134 43 178 54)(font "Arial" )) + (line (pt 192 48)(pt 176 48)) + ) + (port + (pt 192 64) + (output) + (text "ltSigned" (rect 0 0 41 11)(font "Arial" )) + (text "ltSigned" (rect 137 59 178 70)(font "Arial" )) + (line (pt 192 64)(pt 176 64)) + ) + (port + (pt 192 80) + (output) + (text "ltUnsigned" (rect 0 0 54 11)(font "Arial" )) + (text "ltUnsigned" (rect 126 75 180 86)(font "Arial" )) + (line (pt 192 80)(pt 176 80)) + ) + (parameter + "N" + "4" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 176 96)) + ) + (annotation_block (parameter)(rect 792 184 963 214)) +) +(symbol + (rect 600 384 792 496) + (text "CmpN" (rect 5 0 36 11)(font "Arial" )) + (text "inst3" (rect 8 96 32 109)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "input0[n-1..0]" (rect 0 0 64 11)(font "Arial" )) + (text "input0[n-1..0]" (rect 21 27 85 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "input1[n-1..0]" (rect 0 0 64 11)(font "Arial" )) + (text "input1[n-1..0]" (rect 21 43 85 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 192 32) + (output) + (text "equal" (rect 0 0 28 11)(font "Arial" )) + (text "equal" (rect 148 27 176 38)(font "Arial" )) + (line (pt 192 32)(pt 176 32)) + ) + (port + (pt 192 48) + (output) + (text "notEqual" (rect 0 0 44 11)(font "Arial" )) + (text "notEqual" (rect 134 43 178 54)(font "Arial" )) + (line (pt 192 48)(pt 176 48)) + ) + (port + (pt 192 64) + (output) + (text "ltSigned" (rect 0 0 41 11)(font "Arial" )) + (text "ltSigned" (rect 137 59 178 70)(font "Arial" )) + (line (pt 192 64)(pt 176 64)) + ) + (port + (pt 192 80) + (output) + (text "ltUnsigned" (rect 0 0 54 11)(font "Arial" )) + (text "ltUnsigned" (rect 126 75 180 86)(font "Arial" )) + (line (pt 192 80)(pt 176 80)) + ) + (parameter + "N" + "5" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 176 96)) + ) + (annotation_block (parameter)(rect 792 352 963 382)) +) +(connector + (pt 600 248) + (pt 592 248) + (bus) +) +(connector + (pt 600 264) + (pt 592 264) + (bus) +) +(connector + (pt 792 264) + (pt 800 264) +) +(connector + (pt 792 280) + (pt 800 280) +) +(connector + (pt 792 296) + (pt 800 296) +) +(connector + (pt 792 248) + (pt 800 248) +) +(connector + (pt 600 416) + (pt 592 416) + (bus) +) +(connector + (pt 600 432) + (pt 592 432) + (bus) +) +(connector + (pt 792 432) + (pt 800 432) +) +(connector + (pt 792 448) + (pt 800 448) +) +(connector + (pt 792 464) + (pt 800 464) +) +(connector + (pt 792 416) + (pt 800 416) +) diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf new file mode 100644 index 0000000..e3f2c0d --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 11:22:49 March 17, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "20.1" +DATE = "11:22:49 March 17, 2023" + +# Revisions + +PROJECT_REVISION = "CmpN_Demo" diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf new file mode 100644 index 0000000..646af9b --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf @@ -0,0 +1,585 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 11:22:49 March 17, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# CmpN_Demo_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name TOP_LEVEL_ENTITY CmpN_Demo +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:22:49 MARCH 17, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name VECTOR_WAVEFORM_FILE Cmp8.vwf +set_global_assignment -name VHDL_FILE CmpN.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name BDF_FILE CmpN_Demo.bdf +set_location_assignment PIN_Y2 -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_location_assignment PIN_M23 -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_location_assignment PIN_AB28 -to SW[0] +set_location_assignment PIN_AC28 -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_location_assignment PIN_AB26 -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_location_assignment PIN_G19 -to LEDR[0] +set_location_assignment PIN_F19 -to LEDR[1] +set_location_assignment PIN_E19 -to LEDR[2] +set_location_assignment PIN_F21 -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_location_assignment PIN_E21 -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_location_assignment PIN_G18 -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_location_assignment PIN_E17 -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_location_assignment PIN_M24 -to HEX1[0] +set_location_assignment PIN_Y22 -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_location_assignment PIN_AA25 -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_location_assignment PIN_W27 -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_location_assignment PIN_V21 -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_location_assignment PIN_AB19 -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_location_assignment PIN_AG17 -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_location_assignment PIN_L6 -to LCD_BLON +set_location_assignment PIN_M1 -to LCD_RW +set_location_assignment PIN_L4 -to LCD_EN +set_location_assignment PIN_M2 -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_location_assignment PIN_G9 -to UART_TXD +set_location_assignment PIN_G12 -to UART_RXD +set_location_assignment PIN_G14 -to UART_CTS +set_location_assignment PIN_J13 -to UART_RTS +set_location_assignment PIN_G6 -to PS2_CLK +set_location_assignment PIN_H5 -to PS2_DAT +set_location_assignment PIN_G5 -to PS2_CLK2 +set_location_assignment PIN_F5 -to PS2_DAT2 +set_location_assignment PIN_AE13 -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_location_assignment PIN_AF14 -to SD_WP_N +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_location_assignment PIN_G13 -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_A12 -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_location_assignment PIN_E12 -to VGA_R[0] +set_location_assignment PIN_E11 -to VGA_R[1] +set_location_assignment PIN_D10 -to VGA_R[2] +set_location_assignment PIN_F12 -to VGA_R[3] +set_location_assignment PIN_G10 -to VGA_R[4] +set_location_assignment PIN_J12 -to VGA_R[5] +set_location_assignment PIN_H8 -to VGA_R[6] +set_location_assignment PIN_H10 -to VGA_R[7] +set_location_assignment PIN_G8 -to VGA_G[0] +set_location_assignment PIN_G11 -to VGA_G[1] +set_location_assignment PIN_F8 -to VGA_G[2] +set_location_assignment PIN_H12 -to VGA_G[3] +set_location_assignment PIN_C8 -to VGA_G[4] +set_location_assignment PIN_B8 -to VGA_G[5] +set_location_assignment PIN_F10 -to VGA_G[6] +set_location_assignment PIN_C9 -to VGA_G[7] +set_location_assignment PIN_B10 -to VGA_B[0] +set_location_assignment PIN_A10 -to VGA_B[1] +set_location_assignment PIN_C11 -to VGA_B[2] +set_location_assignment PIN_B11 -to VGA_B[3] +set_location_assignment PIN_A11 -to VGA_B[4] +set_location_assignment PIN_C12 -to VGA_B[5] +set_location_assignment PIN_D11 -to VGA_B[6] +set_location_assignment PIN_D12 -to VGA_B[7] +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_location_assignment PIN_D1 -to AUD_DACDAT +set_location_assignment PIN_E1 -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_location_assignment PIN_B7 -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_location_assignment PIN_A14 -to ENETCLK_25 +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_location_assignment PIN_C19 -to ENET0_RST_N +set_location_assignment PIN_C20 -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_location_assignment PIN_A21 -to ENET0_INT_N +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_location_assignment PIN_D22 -to ENET1_RST_N +set_location_assignment PIN_D23 -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_location_assignment PIN_D24 -to ENET1_INT_N +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_location_assignment PIN_E5 -to TD_HS +set_location_assignment PIN_E4 -to TD_VS +set_location_assignment PIN_B14 -to TD_CLK27 +set_location_assignment PIN_G7 -to TD_RESET_N +set_location_assignment PIN_E8 -to TD_DATA[0] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_location_assignment PIN_F7 -to TD_DATA[7] +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_location_assignment PIN_A3 -to OTG_CS_N +set_location_assignment PIN_A4 -to OTG_WR_N +set_location_assignment PIN_B3 -to OTG_RD_N +set_location_assignment PIN_D5 -to OTG_INT +set_location_assignment PIN_C5 -to OTG_RST_N +set_location_assignment PIN_Y15 -to IRDA_RXD +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_location_assignment PIN_AE5 -to DRAM_CLK +set_location_assignment PIN_V6 -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_location_assignment PIN_AG7 -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_location_assignment PIN_Y1 -to FL_RY +set_location_assignment PIN_AC10 -to FL_WE_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_location_assignment PIN_AB22 -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_location_assignment PIN_AD15 -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_location_assignment PIN_AC19 -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_location_assignment PIN_AH23 -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_location_assignment PIN_J10 -to EX_IO[0] +set_location_assignment PIN_J14 -to EX_IO[1] +set_location_assignment PIN_H13 -to EX_IO[2] +set_location_assignment PIN_H14 -to EX_IO[3] +set_location_assignment PIN_F14 -to EX_IO[4] +set_location_assignment PIN_E10 -to EX_IO[5] +set_location_assignment PIN_D9 -to EX_IO[6] +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak new file mode 100644 index 0000000..646af9b --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak @@ -0,0 +1,585 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 11:22:49 March 17, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# CmpN_Demo_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name TOP_LEVEL_ENTITY CmpN_Demo +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:22:49 MARCH 17, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name VECTOR_WAVEFORM_FILE Cmp8.vwf +set_global_assignment -name VHDL_FILE CmpN.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name BDF_FILE CmpN_Demo.bdf +set_location_assignment PIN_Y2 -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_location_assignment PIN_M23 -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_location_assignment PIN_AB28 -to SW[0] +set_location_assignment PIN_AC28 -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_location_assignment PIN_AB26 -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_location_assignment PIN_G19 -to LEDR[0] +set_location_assignment PIN_F19 -to LEDR[1] +set_location_assignment PIN_E19 -to LEDR[2] +set_location_assignment PIN_F21 -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_location_assignment PIN_E21 -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_location_assignment PIN_G18 -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_location_assignment PIN_E17 -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_location_assignment PIN_M24 -to HEX1[0] +set_location_assignment PIN_Y22 -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_location_assignment PIN_AA25 -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_location_assignment PIN_W27 -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_location_assignment PIN_V21 -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_location_assignment PIN_AB19 -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_location_assignment PIN_AG17 -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_location_assignment PIN_L6 -to LCD_BLON +set_location_assignment PIN_M1 -to LCD_RW +set_location_assignment PIN_L4 -to LCD_EN +set_location_assignment PIN_M2 -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_location_assignment PIN_G9 -to UART_TXD +set_location_assignment PIN_G12 -to UART_RXD +set_location_assignment PIN_G14 -to UART_CTS +set_location_assignment PIN_J13 -to UART_RTS +set_location_assignment PIN_G6 -to PS2_CLK +set_location_assignment PIN_H5 -to PS2_DAT +set_location_assignment PIN_G5 -to PS2_CLK2 +set_location_assignment PIN_F5 -to PS2_DAT2 +set_location_assignment PIN_AE13 -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_location_assignment PIN_AF14 -to SD_WP_N +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_location_assignment PIN_G13 -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_A12 -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_location_assignment PIN_E12 -to VGA_R[0] +set_location_assignment PIN_E11 -to VGA_R[1] +set_location_assignment PIN_D10 -to VGA_R[2] +set_location_assignment PIN_F12 -to VGA_R[3] +set_location_assignment PIN_G10 -to VGA_R[4] +set_location_assignment PIN_J12 -to VGA_R[5] +set_location_assignment PIN_H8 -to VGA_R[6] +set_location_assignment PIN_H10 -to VGA_R[7] +set_location_assignment PIN_G8 -to VGA_G[0] +set_location_assignment PIN_G11 -to VGA_G[1] +set_location_assignment PIN_F8 -to VGA_G[2] +set_location_assignment PIN_H12 -to VGA_G[3] +set_location_assignment PIN_C8 -to VGA_G[4] +set_location_assignment PIN_B8 -to VGA_G[5] +set_location_assignment PIN_F10 -to VGA_G[6] +set_location_assignment PIN_C9 -to VGA_G[7] +set_location_assignment PIN_B10 -to VGA_B[0] +set_location_assignment PIN_A10 -to VGA_B[1] +set_location_assignment PIN_C11 -to VGA_B[2] +set_location_assignment PIN_B11 -to VGA_B[3] +set_location_assignment PIN_A11 -to VGA_B[4] +set_location_assignment PIN_C12 -to VGA_B[5] +set_location_assignment PIN_D11 -to VGA_B[6] +set_location_assignment PIN_D12 -to VGA_B[7] +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_location_assignment PIN_D1 -to AUD_DACDAT +set_location_assignment PIN_E1 -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_location_assignment PIN_B7 -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_location_assignment PIN_A14 -to ENETCLK_25 +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_location_assignment PIN_C19 -to ENET0_RST_N +set_location_assignment PIN_C20 -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_location_assignment PIN_A21 -to ENET0_INT_N +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_location_assignment PIN_D22 -to ENET1_RST_N +set_location_assignment PIN_D23 -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_location_assignment PIN_D24 -to ENET1_INT_N +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_location_assignment PIN_E5 -to TD_HS +set_location_assignment PIN_E4 -to TD_VS +set_location_assignment PIN_B14 -to TD_CLK27 +set_location_assignment PIN_G7 -to TD_RESET_N +set_location_assignment PIN_E8 -to TD_DATA[0] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_location_assignment PIN_F7 -to TD_DATA[7] +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_location_assignment PIN_A3 -to OTG_CS_N +set_location_assignment PIN_A4 -to OTG_WR_N +set_location_assignment PIN_B3 -to OTG_RD_N +set_location_assignment PIN_D5 -to OTG_INT +set_location_assignment PIN_C5 -to OTG_RST_N +set_location_assignment PIN_Y15 -to IRDA_RXD +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_location_assignment PIN_AE5 -to DRAM_CLK +set_location_assignment PIN_V6 -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_location_assignment PIN_AG7 -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_location_assignment PIN_Y1 -to FL_RY +set_location_assignment PIN_AC10 -to FL_WE_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_location_assignment PIN_AB22 -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_location_assignment PIN_AD15 -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_location_assignment PIN_AC19 -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_location_assignment PIN_AH23 -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_location_assignment PIN_J10 -to EX_IO[0] +set_location_assignment PIN_J14 -to EX_IO[1] +set_location_assignment PIN_H13 -to EX_IO[2] +set_location_assignment PIN_H14 -to EX_IO[3] +set_location_assignment PIN_F14 -to EX_IO[4] +set_location_assignment PIN_E10 -to EX_IO[5] +set_location_assignment PIN_D9 -to EX_IO[6] +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qws b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qws new file mode 100644 index 0000000000000000000000000000000000000000..4c432a4df447e6831f993cdcb012142f326a9c31 GIT binary patch literal 2491 zcmds(J#Q015QgWD$g-$XA&4ka0J4y5@Nt$CiYVf%K!^g-P+9i*9IV9HIEF+*5tPvK z8)&Hb6Ygke5lHzL2nj=Y-u0d3*ij;^(0Hx=nAw@x*_n6eyq>ePU9>H$+P3wqVmsEh zu5Chf;6)ZAbcP>weS%%@-B1~K0EY}szPi1modGpNVRZ6a60^R7hgfTlTV zi*^sym@7ymvdyD}@XXY6_J}-e5Z4(_l3^LS! z1&0dB8$1Cq*;IhA`u&NDd-`zVUan;>aNLuW;@CgxqFqr}8B_5JlOm=sW}dPX0+^%V zq=GgHrx58PP~1x|<$c2Z2sG~bfFyWcf8Z*<%2JMRe1~uSbH3TC+7WX-38wx7G@&-| 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b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.logdb new file mode 100644 index 0000000..599525e --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.logdb @@ -0,0 +1,68 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;26;26;0;0;26;26;0;0;0;0;0;0;8;0;0;0;18;8;0;18;0;0;8;0;26;26;26;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,26;0;0;26;26;0;0;26;26;26;26;26;26;18;26;26;26;8;18;26;8;26;26;18;26;0;0;0;26;26, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,LEDG[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[11],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[17],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[12],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[16],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[13],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[14],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[10],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[15],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.rdb 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