diff --git a/2ano/2semestre/ac2/aula08/AC2-P-Aula08.pdf b/2ano/2semestre/ac2/aula08/AC2-P-Aula08.pdf new file mode 100644 index 0000000..9e767d9 Binary files /dev/null and b/2ano/2semestre/ac2/aula08/AC2-P-Aula08.pdf differ diff --git a/2ano/2semestre/ac2/aula08/part1-ex1.c b/2ano/2semestre/ac2/aula08/part1-ex1.c new file mode 100644 index 0000000..24febc3 --- /dev/null +++ b/2ano/2semestre/ac2/aula08/part1-ex1.c @@ -0,0 +1,16 @@ +#include + +int main() { + T3CONbits.TCKPS = 7; // 1:256 prescaler + PR3 = 39062; // Fout = 20MHz / (256 * (39062 + 1)) = 2Hz + TMR3 = 0; // Reset timer T3 count register + T3CONbits.TON = 1; // Enable timer T3 (must be the last command of the timer configuration sequence) + + while (1) { + while (IFS0bits.T3IF == 0); // Wait while T3IF is 0 + IFS0bits.T3IF = 0; // Reset T3IF + putChar('.'); + } + + return 0; +} diff --git a/2ano/2semestre/ac2/aula08/part1-ex2.c b/2ano/2semestre/ac2/aula08/part1-ex2.c new file mode 100644 index 0000000..483c622 --- /dev/null +++ b/2ano/2semestre/ac2/aula08/part1-ex2.c @@ -0,0 +1,22 @@ +#include + +void _int_(12) isr_T3(void) { + putChar('.'); + IFS0bits.T3IF = 0; // Reset timer T3 interrupt flag +} + +int main() { + T3CONbits.TCKPS = 7; // 1:256 prescaler + PR3 = 39062; // Fout = 20MHz / (256 * (39062 + 1)) = 2Hz + TMR3 = 0; // Reset timer T3 count register + T3CONbits.TON = 1; // Enable timer T3 (must be the last command of the timer configuration sequence) + + IPC3bits.T3IP = 2; // Interrupt priority (must be in range [1..6]) + IEC0bits.T3IE = 1; // Enable timer T3 interrupts + IFS0bits.T3IF = 0; // Reset timer T3 interrupt flag + + EnableInterrupts(); // Global Interrupt Enable + while (1); + + return 0; +} diff --git a/2ano/2semestre/ac2/aula08/part1-ex3.c b/2ano/2semestre/ac2/aula08/part1-ex3.c new file mode 100644 index 0000000..a48cee3 --- /dev/null +++ b/2ano/2semestre/ac2/aula08/part1-ex3.c @@ -0,0 +1,24 @@ +#include + +void _int_(12) isr_T3(void) { + static int flag = 0; + if (flag == 0) putChar('.'); + flag = !flag; + IFS0bits.T3IF = 0; // Reset timer T3 interrupt flag +} + +int main() { + T3CONbits.TCKPS = 7; // 1:256 prescaler + PR3 = 39062; // Fout = 20MHz / (256 * (39062 + 1)) = 2Hz + TMR3 = 0; // Reset timer T3 count register + T3CONbits.TON = 1; // Enable timer T3 (must be the last command of the timer configuration sequence) + + IPC3bits.T3IP = 2; // Interrupt priority (must be in range [1..6]) + IEC0bits.T3IE = 1; // Enable timer T3 interrupts + IFS0bits.T3IF = 0; // Reset timer T3 interrupt flag + + EnableInterrupts(); // Global Interrupt Enable + while (1); + + return 0; +} diff --git a/2ano/2semestre/ac2/aula08/part1-ex4.c b/2ano/2semestre/ac2/aula08/part1-ex4.c new file mode 100644 index 0000000..9ace12d --- /dev/null +++ b/2ano/2semestre/ac2/aula08/part1-ex4.c @@ -0,0 +1,57 @@ +#include + +int counters[] = {0, 0}; + +void print() { + putChar('\r'); + printStr("T1: "); + printInt10(0[counters]); + printStr(" T3: "); + printInt10(1[counters]); +} + +void _int_(4) isr_T1(void) { + counters[0]++; + LATD ^= 0x0001; + LATE ^= 0x0002; + print(); + IFS0bits.T1IF = 0; // Reset timer T1 interrupt flag +} + +void _int_(12) isr_T3(void) { + counters[1]++; + LATD ^= 0x0004; + LATE ^= 0x0008; + print(); + IFS0bits.T3IF = 0; // Reset timer T3 interrupt flag +} + +int main() { + T1CONbits.TCKPS = 2; + PR1 = 62499; + TMR1 = 0; + T1CONbits.TON = 1; + + T3CONbits.TCKPS = 4; + PR3 = 49999; + TMR3 = 0; + T3CONbits.TON = 1; + + IPC1bits.T1IP = 2; // Interrupt priority (must be in range [1..6]) + IEC0bits.T1IE = 1; // Enable timer T1 interrupts + IFS0bits.T1IF = 0; // Reset timer T1 interrupt flag + + IPC3bits.T3IP = 2; // Interrupt priority (must be in range [1..6]) + IEC0bits.T3IE = 1; // Enable timer T3 interrupts + IFS0bits.T3IF = 0; // Reset timer T3 interrupt flag + + TRISD &= 0xFFFA; + LATD &= 0xFFFA; + TRISE &= 0xFFF5; + LATE &= 0xFFF5; + + EnableInterrupts(); // Global Interrupt Enable + while (1); + + return 0; +} diff --git a/2ano/2semestre/ac2/aula08/part1-ex4.txt b/2ano/2semestre/ac2/aula08/part1-ex4.txt new file mode 100644 index 0000000..87fe57c --- /dev/null +++ b/2ano/2semestre/ac2/aula08/part1-ex4.txt @@ -0,0 +1,17 @@ +Timer 1 + +K > 20000000 / (65536 * 5) +K > 61.035 +K = 64 + +PR1 = ((20000000 / 64) / 5) - 1 = 62499 + +------------------------------------------------ + +Timer 3 + +K > 20000000 / (65536 * 25) +K > 12.207 +K > 16 + +PR3 = ((20000000 / 16) / 25) - 1 = 49999 diff --git a/2ano/2semestre/ac2/aula08/part2-ex1.c b/2ano/2semestre/ac2/aula08/part2-ex1.c new file mode 100644 index 0000000..2fc6000 --- /dev/null +++ b/2ano/2semestre/ac2/aula08/part2-ex1.c @@ -0,0 +1,21 @@ +#include + +void delay(unsigned int ms) { + resetCoreTimer(); + while (readCoreTimer() < 20000 * ms); +} + +int main() { + TRISD |= 0x0100; + TRISE &= 0xFFFE; + LATE &= 0xFFFE; + + while (1) { + while (((PORTD >> 8) & 0x0001) == 1); + LATE ^= 0x0001; + delay(3000); + LATE ^= 0x0001; + } + + return 0; +} diff --git a/2ano/2semestre/ac2/aula08/part2-ex2.c b/2ano/2semestre/ac2/aula08/part2-ex2.c new file mode 100644 index 0000000..b1eb9cb --- /dev/null +++ b/2ano/2semestre/ac2/aula08/part2-ex2.c @@ -0,0 +1,41 @@ +#include + +void _int_(8) isr_T2() { + static int c = 0; + if (c++ == 6) { + IEC0bits.T2IE = 0; + LATE &= 0xFFFE; + c = 0; + } + IFS0bits.T2IF = 0; +} + +void _int_(7) isr_INT1() { + LATE |= 0x0001; + IEC0bits.T2IE = 1; + IFS0bits.INT1IF = 0; +} + +int main() { + TRISD |= 0x0100; + TRISE &= 0xFFFE; + LATE &= 0xFFFE; + + IPC1bits.INT1IP = 2; + IEC0bits.INT1IE = 1; + IFS0bits.INT1IF = 0; + + IPC2bits.T2IP = 2; + IFS0bits.T2IF = 0; + + T2CONbits.TCKPS = 7; + PR2 = 39062; + TMR2 = 0; + T2CONbits.TON = 1; + + EnableInterrupts(); + + while (1); + + return 0; +}