[LSD] Mux2_1 finished
This commit is contained in:
TiagoRG
parent
9932fa0f2c
commit
ee5253ff18
|
|
@ -39,7 +39,7 @@
|
|||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE115F29C7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Mux2_1Demo
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Mux2_1
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:28:47 MARCH 07, 2023"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
|
||||
|
|
@ -58,9 +58,6 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
|
|||
set_global_assignment -name VHDL_FILE Mux2_1.vhd
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Mux2_1.vwf
|
||||
set_global_assignment -name BDF_FILE Mux2_1Demo.bdf
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_location_assignment PIN_Y2 -to CLOCK_50
|
||||
set_location_assignment PIN_AG14 -to CLOCK2_50
|
||||
set_location_assignment PIN_AG15 -to CLOCK3_50
|
||||
|
|
@ -580,4 +577,7 @@ set_location_assignment PIN_H14 -to EX_IO[3]
|
|||
set_location_assignment PIN_F14 -to EX_IO[4]
|
||||
set_location_assignment PIN_E10 -to EX_IO[5]
|
||||
set_location_assignment PIN_D9 -to EX_IO[6]
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,3 +1,3 @@
|
|||
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Version_Index = 520278016
|
||||
Creation_Time = Tue Mar 7 22:20:46 2023
|
||||
Creation_Time = Wed Mar 8 09:48:15 2023
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678227272079 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2020 Intel Corporation. All rights reserved. " "Copyright (C) 2020 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and any partner logic " "and other software and tools, and any partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors. Please " "Intel and sold by Intel or its authorized distributors. Please" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details, at " "refer to the applicable agreement for further details, at" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "https://fpgasoftware.intel.com/eula. " "https://fpgasoftware.intel.com/eula." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:14:31 2023 " "Processing started: Tue Mar 7 22:14:31 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678227272079 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/ Mux2_1Demo -c Mux2_1Demo " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/ Mux2_1Demo -c Mux2_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678227272079 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678227272211 ""}
|
||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "Mux2_1Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim// simulation " "Generated file Mux2_1Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678227272233 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "611 " "Peak virtual memory: 611 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678227272243 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:14:32 2023 " "Processing ended: Tue Mar 7 22:14:32 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678227272243 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678227272243 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678227272243 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678227272243 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678268911921 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2020 Intel Corporation. All rights reserved. " "Copyright (C) 2020 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and any partner logic " "and other software and tools, and any partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors. Please " "Intel and sold by Intel or its authorized distributors. Please" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details, at " "refer to the applicable agreement for further details, at" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "https://fpgasoftware.intel.com/eula. " "https://fpgasoftware.intel.com/eula." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 09:48:31 2023 " "Processing started: Wed Mar 8 09:48:31 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678268911921 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678268911921 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht " "Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678268911922 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678268912094 ""}
|
||||
{ "Error" "EQNETO_INVALID_TESTBENCH_OUTPUT_PATH" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht " "HDL output file name \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht\" used with --testbench_file option contains a non-existent directory path" { } { } 0 199013 "HDL output file name \"%1!s!\" used with --testbench_file option contains a non-existent directory path" 0 0 "EDA Netlist Writer" 0 -1 1678268912095 ""}
|
||||
{ "Error" "EQNETO_INVALID_TESTBENCH_INPUT_PATH" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf " "Vector source file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf specified with --testbench_vector_input_file option does not exist" { } { } 0 199014 "Vector source file %1!s! specified with --testbench_vector_input_file option does not exist" 0 0 "EDA Netlist Writer" 0 -1 1678268912095 ""}
|
||||
{ "Error" "EQEXE_ERROR_COUNT" "EDA Netlist Writer 2 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "608 " "Peak virtual memory: 608 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678268912108 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Mar 8 09:48:32 2023 " "Processing ended: Wed Mar 8 09:48:32 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678268912108 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678268912108 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678268912108 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678268912108 ""}
|
||||
|
|
|
|||
|
|
@ -1,4 +0,0 @@
|
|||
start_full_compilation:s
|
||||
start_assembler:s-start_full_compilation
|
||||
start_timing_analyzer:s-start_full_compilation
|
||||
start_eda_netlist_writer:s-start_full_compilation
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
EDA Netlist Writer report for Mux2_1Demo
|
||||
Tue Mar 7 22:14:32 2023
|
||||
Wed Mar 8 09:48:32 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -8,9 +8,7 @@ Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
|||
---------------------
|
||||
1. Legal Notice
|
||||
2. EDA Netlist Writer Summary
|
||||
3. Simulation Settings
|
||||
4. Simulation Generated Files
|
||||
5. EDA Netlist Writer Messages
|
||||
3. EDA Netlist Writer Messages
|
||||
|
||||
|
||||
|
||||
|
|
@ -34,45 +32,14 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
+---------------------------------------------------------------+
|
||||
; EDA Netlist Writer Summary ;
|
||||
+---------------------------+---------------------------------------+
|
||||
; EDA Netlist Writer Status ; Successful - Tue Mar 7 22:14:32 2023 ;
|
||||
+---------------------------+-----------------------------------+
|
||||
; EDA Netlist Writer Status ; Failed - Wed Mar 8 09:48:32 2023 ;
|
||||
; Revision Name ; Mux2_1Demo ;
|
||||
; Top-level Entity Name ; Mux2_1Demo ;
|
||||
; Family ; Cyclone IV E ;
|
||||
; Simulation Files Creation ; Successful ;
|
||||
+---------------------------+---------------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------+
|
||||
; Simulation Settings ;
|
||||
+---------------------------------------------------------------------------------------------------+------------------------+
|
||||
; Option ; Setting ;
|
||||
+---------------------------------------------------------------------------------------------------+------------------------+
|
||||
; Tool Name ; ModelSim-Altera (VHDL) ;
|
||||
; Generate functional simulation netlist ; On ;
|
||||
; Truncate long hierarchy paths ; Off ;
|
||||
; Map illegal HDL characters ; Off ;
|
||||
; Flatten buses into individual nodes ; Off ;
|
||||
; Maintain hierarchy ; Off ;
|
||||
; Bring out device-wide set/reset signals as ports ; Off ;
|
||||
; Enable glitch filtering ; Off ;
|
||||
; Do not write top level VHDL entity ; Off ;
|
||||
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
|
||||
; Architecture name in VHDL output netlist ; structure ;
|
||||
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
|
||||
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
|
||||
+---------------------------------------------------------------------------------------------------+------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------+
|
||||
; Simulation Generated Files ;
|
||||
+------------------------------------------------------------------------------------------------------+
|
||||
; Generated Files ;
|
||||
+------------------------------------------------------------------------------------------------------+
|
||||
; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim//Mux2_1Demo.vho ;
|
||||
+------------------------------------------------------------------------------------------------------+
|
||||
+---------------------------+-----------------------------------+
|
||||
|
||||
|
||||
+-----------------------------+
|
||||
|
|
@ -95,14 +62,15 @@ Info: Running Quartus Prime EDA Netlist Writer
|
|||
Info: Intel and sold by Intel or its authorized distributors. Please
|
||||
Info: refer to the applicable agreement for further details, at
|
||||
Info: https://fpgasoftware.intel.com/eula.
|
||||
Info: Processing started: Tue Mar 7 22:14:31 2023
|
||||
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/ Mux2_1Demo -c Mux2_1Demo
|
||||
Info: Processing started: Wed Mar 8 09:48:31 2023
|
||||
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (204019): Generated file Mux2_1Demo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim//" for EDA simulation tool
|
||||
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 611 megabytes
|
||||
Info: Processing ended: Tue Mar 7 22:14:32 2023
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
Error (199013): HDL output file name "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht" used with --testbench_file option contains a non-existent directory path
|
||||
Error (199014): Vector source file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf specified with --testbench_vector_input_file option does not exist
|
||||
Error: Quartus Prime EDA Netlist Writer was unsuccessful. 2 errors, 1 warning
|
||||
Error: Peak virtual memory: 608 megabytes
|
||||
Error: Processing ended: Wed Mar 8 09:48:32 2023
|
||||
Error: Elapsed time: 00:00:01
|
||||
Error: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Flow report for Mux2_1Demo
|
||||
Tue Mar 7 22:14:32 2023
|
||||
Wed Mar 8 09:48:32 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -38,10 +38,10 @@ https://fpgasoftware.intel.com/eula.
|
|||
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------+
|
||||
+-------------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Mar 7 22:14:32 2023 ;
|
||||
+------------------------------------+------------------------------------------------------+
|
||||
; Flow Status ; EDA Netlist Writer Failed - Wed Mar 8 09:48:32 2023 ;
|
||||
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
|
||||
; Revision Name ; Mux2_1Demo ;
|
||||
; Top-level Entity Name ; Mux2_1Demo ;
|
||||
|
|
@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
; Total memory bits ; 0 / 3,981,312 ( 0 % ) ;
|
||||
; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ;
|
||||
; Total PLLs ; 0 / 4 ( 0 % ) ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
+------------------------------------+------------------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
|
|
@ -108,7 +108,8 @@ https://fpgasoftware.intel.com/eula.
|
|||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 611 MB ; 00:00:00 ;
|
||||
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 608 MB ; 00:00:00 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 611 MB ; 00:00:00 ;
|
||||
; Total ; 00:00:16 ; -- ; -- ; 00:00:24 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 608 MB ; 00:00:00 ;
|
||||
; Total ; 00:00:17 ; -- ; -- ; 00:00:24 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
|
@ -126,6 +127,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
|
||||
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
|
||||
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
|
||||
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
|
||||
+----------------------+------------------+----------------+------------+----------------+
|
||||
|
||||
|
||||
|
|
@ -141,6 +143,7 @@ quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_f
|
|||
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/ Mux2_1Demo -c Mux2_1Demo
|
||||
quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht
|
||||
quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/ Mux2_1Demo -c Mux2_1Demo
|
||||
quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue