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All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. 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+(junction (pt 24 328)) +(junction (pt 48 168)) +(junction (pt 48 256)) +(junction (pt 48 344)) +(junction (pt 104 184)) +(junction (pt 128 64)) +(junction (pt 80 64)) +(junction (pt 80 360)) +(junction (pt 152 200)) +(junction (pt 128 288)) diff --git a/1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qpf b/1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qpf new file mode 100644 index 0000000..3608a45 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 11:42:26 November 04, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "20.1" +DATE = "11:42:26 November 04, 2022" + +# Revisions + +PROJECT_REVISION = "DecoderDemo" diff --git a/1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qsf b/1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qsf new file mode 100644 index 0000000..1651693 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qsf @@ -0,0 +1,61 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 11:42:27 November 04, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# DecoderDemo_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE auto +set_global_assignment -name TOP_LEVEL_ENTITY Dec2_4 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:42:27 NOVEMBER 04, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name BDF_FILE Dec2_4.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE WaveformDecoderNode.vwf +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qws b/1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qws new file mode 100644 index 0000000..4cf6a83 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/DecoderDemo.qws differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/EqCmpDemo.bdf b/1ano/isd/quartus-projects/DecoderDemo/EqCmpDemo.bdf new file mode 100644 index 0000000..e221593 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/EqCmpDemo.bdf @@ -0,0 +1,22 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "graphic" (version "1.4")) diff --git a/1ano/isd/quartus-projects/DecoderDemo/Waveform.vwf b/1ano/isd/quartus-projects/DecoderDemo/Waveform.vwf new file mode 100644 index 0000000..0bf417f --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/Waveform.vwf @@ -0,0 +1,694 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/tiagorg/repos/DecoderDemo/Waveform.vwf" --testbench_file="/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform.vwf.vht" +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/tiagorg/repos/DecoderDemo/Waveform.vwf" --testbench_file="/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform.vwf.vht" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/DecoderDemo/simulation/qsim/" DecoderDemo -c DecoderDemo +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/DecoderDemo/simulation/qsim/" DecoderDemo -c DecoderDemo +onerror {exit -code 1} +vlib work +vcom -work work DecoderDemo.vho +vcom -work work Waveform.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst +vcd file -direction DecoderDemo.msim.vcd +vcd add -internal Dec2_4_vhd_vec_tst/* +vcd add -internal Dec2_4_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vcom -work work DecoderDemo.vho +vcom -work work Waveform.vwf.vht +vsim -novopt -c -t 1ps -sdfmax Dec2_4_vhd_vec_tst/i1=DecoderDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst +vcd file -direction DecoderDemo.msim.vcd +vcd add -internal Dec2_4_vhd_vec_tst/* +vcd add -internal Dec2_4_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +vhdl +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("E0L") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("E1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Y0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("E0L") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 65.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; 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+ LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + } +} + +TRANSITION_LIST("Y0") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y1") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y3") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "E0L"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "E1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/isd/quartus-projects/DecoderDemo/Waveform1.vwf b/1ano/isd/quartus-projects/DecoderDemo/Waveform1.vwf new file mode 100644 index 0000000..2981fc8 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/Waveform1.vwf @@ -0,0 +1,328 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/tiagorg/repos/DecoderDemo/Waveform1.vwf" --testbench_file="/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform1.vwf.vht" +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/tiagorg/repos/DecoderDemo/Waveform1.vwf" --testbench_file="/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform1.vwf.vht" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/DecoderDemo/simulation/qsim/" DecoderDemo -c DecoderDemo +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/DecoderDemo/simulation/qsim/" DecoderDemo -c DecoderDemo +onerror {exit -code 1} +vlib work +vcom -work work DecoderDemo.vho +vcom -work work Waveform1.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst +vcd file -direction DecoderDemo.msim.vcd +vcd add -internal Dec2_4_vhd_vec_tst/* +vcd add -internal Dec2_4_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vcom -work work DecoderDemo.vho +vcom -work work Waveform1.vwf.vht +vsim -novopt -c -t 1ps -sdfmax Dec2_4_vhd_vec_tst/i1=DecoderDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst +vcd file -direction DecoderDemo.msim.vcd +vcd add -internal Dec2_4_vhd_vec_tst/* +vcd add -internal Dec2_4_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +vhdl +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("E0L") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("E1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Y0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("E0L") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 40; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + } + } +} + +TRANSITION_LIST("E1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 20; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("X0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("X1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("Y0") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y1") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y3") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "E0L"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "E1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/isd/quartus-projects/DecoderDemo/WaveformDecoderNode.vwf b/1ano/isd/quartus-projects/DecoderDemo/WaveformDecoderNode.vwf new file mode 100644 index 0000000..bdbd7d6 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/WaveformDecoderNode.vwf @@ -0,0 +1,330 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/WaveformDecoderNode.vwf" --testbench_file="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/WaveformDecoderNode.vwf.vht" +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/WaveformDecoderNode.vwf" --testbench_file="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/WaveformDecoderNode.vwf.vht" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/" DecoderDemo -c DecoderDemo +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/" DecoderDemo -c DecoderDemo +onerror {exit -code 1} +vlib work +vcom -work work DecoderDemo.vho +vcom -work work WaveformDecoderNode.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst +vcd file -direction DecoderDemo.msim.vcd +vcd add -internal Dec2_4_vhd_vec_tst/* +vcd add -internal Dec2_4_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + + +onerror {exit -code 1} +vlib work +vcom -work work DecoderDemo.vho +vcom -work work WaveformDecoderNode.vwf.vht +vsim -c -t 1ps -sdfmax Dec2_4_vhd_vec_tst/i1=DecoderDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst +vcd file -direction DecoderDemo.msim.vcd +vcd add -internal Dec2_4_vhd_vec_tst/* +vcd add -internal Dec2_4_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + + +vhdl +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("E0L") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("E1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Y0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("X1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +TRANSITION_LIST("E0L") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("E1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("X0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 40; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + } + } +} + +TRANSITION_LIST("Y0") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y1") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y3") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("X1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 20; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "E0L"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "E1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/isd/quartus-projects/DecoderDemo/WaveformDecoderNoide.vwf b/1ano/isd/quartus-projects/DecoderDemo/WaveformDecoderNoide.vwf new file mode 100644 index 0000000..d2c9f7d --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/WaveformDecoderNoide.vwf @@ -0,0 +1,308 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/Waveform.vwf" --testbench_file="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/Waveform.vwf" --testbench_file="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/" DecoderDemo -c DecoderDemo +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/rubeng/Documents/UAlinux/ISD/Quartus Prime/simulation/qsim/" DecoderDemo -c DecoderDemo +onerror {exit -code 1} +vlib work +vlog -work work DecoderDemo.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Dec2_4_vlg_vec_tst +vcd file -direction DecoderDemo.msim.vcd +vcd add -internal Dec2_4_vlg_vec_tst/* +vcd add -internal Dec2_4_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work DecoderDemo.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.Dec2_4_vlg_vec_tst +vcd file -direction DecoderDemo.msim.vcd +vcd add -internal Dec2_4_vlg_vec_tst/* +vcd add -internal Dec2_4_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("E0L") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("E1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Y0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("E0L") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("E1") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("X0") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("X1") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("Y0") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y1") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y2") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("Y3") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "E0L"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "E1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/.cmp.kpt b/1ano/isd/quartus-projects/DecoderDemo/db/.cmp.kpt new file mode 100644 index 0000000..e067e29 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/.cmp.kpt differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.(0).cnf.cdb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.(0).cnf.cdb new file mode 100644 index 0000000..2364920 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.(0).cnf.cdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.(0).cnf.hdb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.(0).cnf.hdb new file mode 100644 index 0000000..122667c Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.(0).cnf.hdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm.qmsg b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm.qmsg new file mode 100644 index 0000000..c8ab3b8 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668463009510 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668463009510 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:56:49 2022 " "Processing started: Mon Nov 14 21:56:49 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668463009510 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1668463009510 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1668463009510 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1668463009605 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1668463009774 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1668463009781 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668463009828 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:56:49 2022 " "Processing ended: Mon Nov 14 21:56:49 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668463009828 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668463009828 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668463009828 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1668463009828 ""} diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm.rdb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm.rdb new file mode 100644 index 0000000..9b146b8 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm.rdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm_labs.ddb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm_labs.ddb new file mode 100644 index 0000000..7666cdc Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.asm_labs.ddb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cbx.xml b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cbx.xml new file mode 100644 index 0000000..03bf357 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.bpm b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.bpm new file mode 100644 index 0000000..f6d6904 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.bpm differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.cdb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.cdb new file mode 100644 index 0000000..a4a7d54 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.cdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.hdb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.hdb new file mode 100644 index 0000000..f927437 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.hdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.idb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.idb new file mode 100644 index 0000000..c34e4bf Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.idb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.logdb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.logdb new file mode 100644 index 0000000..aff02eb --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.logdb @@ -0,0 +1,50 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;8;0;0;0;0;0;0;0;4;0;0;0;4;4;0;4;0;0;4;0;8;8;8;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,8;8;8;8;8;0;8;8;8;8;8;8;8;4;8;8;8;4;4;8;4;8;8;4;8;0;0;0;8;8, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Y3,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Y2,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Y1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,Y0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,E1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,X0,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,X1,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,E0L,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,9, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.rdb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.rdb new file mode 100644 index 0000000..cf035f8 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp.rdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp_merge.kpt b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp_merge.kpt new file mode 100644 index 0000000..23a5cd1 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cmp_merge.kpt differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd new file mode 100644 index 0000000..d9c61ce Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd new file mode 100644 index 0000000..599a335 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd new file mode 100644 index 0000000..cc4b33a Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.db_info b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.db_info new file mode 100644 index 0000000..89c6181 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Mon Nov 14 21:39:53 2022 diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.eda.qmsg b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.eda.qmsg new file mode 100644 index 0000000..73e8517 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.eda.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668463011444 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668463011449 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:56:51 2022 " "Processing started: Mon Nov 14 21:56:51 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668463011449 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668463011449 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668463011449 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1668463011567 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "DecoderDemo.vho /home/tiagorg/repos/DecoderDemo/simulation/modelsim/ simulation " "Generated file DecoderDemo.vho in folder \"/home/tiagorg/repos/DecoderDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668463011589 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "600 " "Peak virtual memory: 600 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668463011596 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:56:51 2022 " "Processing ended: Mon Nov 14 21:56:51 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668463011596 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668463011596 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668463011596 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1668463011596 ""} diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.fit.qmsg b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.fit.qmsg new file mode 100644 index 0000000..33f7098 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.fit.qmsg @@ -0,0 +1,49 @@ +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1668463007155 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1668463007156 ""} +{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "DecoderDemo EP4CE6E22C6 " "Automatically selected device EP4CE6E22C6 for design DecoderDemo" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1668463007236 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1668463007272 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1668463007272 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1668463007338 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1668463007341 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C6 " "Device EP4CE10E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668463007365 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C6 " "Device EP4CE15E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668463007365 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C6 " "Device EP4CE22E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668463007365 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1668463007365 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 27 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668463007366 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 29 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668463007366 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 31 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668463007366 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 33 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668463007366 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 35 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668463007366 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1668463007366 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1668463007367 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "8 8 " "No exact pin location assignment(s) for 8 pins of 8 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1668463007518 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DecoderDemo.sdc " "Synopsys Design Constraints File file not found: 'DecoderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1668463007574 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1668463007574 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1668463007574 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1668463007574 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1668463007575 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1668463007575 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1668463007575 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1668463007576 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668463007576 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668463007576 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668463007577 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668463007577 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1668463007577 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1668463007577 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1668463007577 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1668463007577 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1668463007577 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1668463007577 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "8 unused 2.5V 4 4 0 " "Number of I/O pins in group: 8 (unused VREF, 2.5V VCCIO, 4 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1668463007578 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1668463007578 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1668463007578 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 7 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 7 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 8 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 8 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 11 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 11 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 13 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 9 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 9 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 13 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 12 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668463007578 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1668463007578 ""} } { } 0 176215 "I/O bank details %1!s! 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HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
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a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta.qmsg b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta.qmsg new file mode 100644 index 0000000..3d74e6e --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta.qmsg @@ -0,0 +1,49 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668463010289 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668463010289 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:56:50 2022 " "Processing started: Mon Nov 14 21:56:50 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668463010289 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1668463010289 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DecoderDemo -c DecoderDemo " "Command: quartus_sta DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1668463010289 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1668463010309 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1668463010348 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1668463010348 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1668463010383 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1668463010383 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DecoderDemo.sdc " "Synopsys Design Constraints File file not found: 'DecoderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1668463010479 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668463010479 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668463010479 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668463010479 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1668463010479 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668463010479 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1668463010480 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1668463010481 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1668463010481 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010482 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010483 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010484 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010484 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010484 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010485 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668463010486 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1668463010498 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1668463010702 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668463010713 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668463010713 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668463010713 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668463010713 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010713 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010714 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010714 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010715 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010715 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010715 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668463010716 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668463010753 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668463010753 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668463010753 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668463010753 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010754 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010754 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010754 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010755 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668463010755 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668463010955 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668463010955 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "465 " "Peak virtual memory: 465 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668463010962 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:56:50 2022 " "Processing ended: Mon Nov 14 21:56:50 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668463010962 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668463010962 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668463010962 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1668463010962 ""} diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta.rdb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta.rdb new file mode 100644 index 0000000..cb7a68f Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta.rdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta_cmp.6_slow_1200mv_85c.tdb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 0000000..f4c7d43 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tis_db_list.ddb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tis_db_list.ddb new file mode 100644 index 0000000..73e5ec9 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tis_db_list.ddb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 0000000..2c69010 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.fast_1200mv_0c.ddb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 0000000..f51ea24 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.slow_1200mv_0c.ddb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 0000000..eefa9d0 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.tiscmp.slow_1200mv_85c.ddb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.vpr.ammdb b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.vpr.ammdb new file mode 100644 index 0000000..18a08c4 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo.vpr.ammdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo_partition_pins.json b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo_partition_pins.json new file mode 100644 index 0000000..15ccf6d --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/db/DecoderDemo_partition_pins.json @@ -0,0 +1,41 @@ +{ + "partitions" : [ + { + "name" : "Top", + "pins" : [ + { + "name" : "Y3", + "strict" : false + }, + { + "name" : "Y2", + "strict" : false + }, + { + "name" : "Y1", + "strict" : false + }, + { + "name" : "Y0", + "strict" : false + }, + { + "name" : "E1", + "strict" : false + }, + { + "name" : "X0", + "strict" : false + }, + { + "name" : "X1", + "strict" : false + }, + { + "name" : "E0L", + "strict" : false + } + ] + } + ] +} \ No newline at end of file diff --git a/1ano/isd/quartus-projects/DecoderDemo/db/prev_cmp_DecoderDemo.qmsg b/1ano/isd/quartus-projects/DecoderDemo/db/prev_cmp_DecoderDemo.qmsg new file mode 100644 index 0000000..0ff9d72 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/db/prev_cmp_DecoderDemo.qmsg @@ -0,0 +1,130 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1668462005146 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668462005146 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:40:05 2022 " "Processing started: Mon Nov 14 21:40:05 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668462005146 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668462005146 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668462005146 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1668462005241 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1668462005241 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec2_4.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Dec2_4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Dec2_4 " "Found entity 1: Dec2_4" { } { { "Dec2_4.bdf" "" { Schematic "/home/tiagorg/repos/DecoderDemo/Dec2_4.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1668462009856 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1668462009856 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "Dec2_4 " "Elaborating entity \"Dec2_4\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1668462009881 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1668462010158 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1668462010370 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1668462010370 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "12 " "Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1668462010407 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1668462010407 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4 " "Implemented 4 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1668462010407 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1668462010407 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "398 " "Peak virtual memory: 398 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668462010410 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:40:10 2022 " "Processing ended: Mon Nov 14 21:40:10 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668462010410 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668462010410 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668462010410 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1668462010410 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1668462010962 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668462010962 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:40:10 2022 " "Processing started: Mon Nov 14 21:40:10 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668462010962 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1668462010962 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_fit --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1668462010962 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1668462011028 ""} +{ "Info" "0" "" "Project = DecoderDemo" { } { } 0 0 "Project = DecoderDemo" 0 0 "Fitter" 0 0 1668462011029 ""} +{ "Info" "0" "" "Revision = DecoderDemo" { } { } 0 0 "Revision = DecoderDemo" 0 0 "Fitter" 0 0 1668462011029 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1668462011053 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1668462011053 ""} +{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "DecoderDemo EP4CE6E22C6 " "Automatically selected device EP4CE6E22C6 for design DecoderDemo" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1668462011132 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1668462011166 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1668462011166 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1668462011241 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1668462011245 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C6 " "Device EP4CE10E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668462011294 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C6 " "Device EP4CE15E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668462011294 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C6 " "Device EP4CE22E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1668462011294 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1668462011294 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 27 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668462011298 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 29 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668462011298 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 31 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668462011298 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 33 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668462011298 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 0 { 0 ""} 0 35 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1668462011298 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1668462011298 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1668462011300 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "8 8 " "No exact pin location assignment(s) for 8 pins of 8 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1668462011464 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DecoderDemo.sdc " "Synopsys Design Constraints File file not found: 'DecoderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1668462011528 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1668462011528 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1668462011528 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1668462011528 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1668462011529 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1668462011529 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1668462011529 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1668462011532 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668462011532 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1668462011532 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668462011532 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1668462011532 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1668462011532 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1668462011532 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1668462011532 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1668462011532 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1668462011532 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1668462011532 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "8 unused 2.5V 4 4 0 " "Number of I/O pins in group: 8 (unused VREF, 2.5V VCCIO, 4 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1668462011534 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1668462011534 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1668462011534 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 4 7 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 7 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 8 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 8 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 11 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 11 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 13 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 9 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 9 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 13 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 12 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1668462011535 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1668462011535 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1668462011535 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668462011538 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1668462011542 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1668462011795 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668462011811 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1668462011819 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1668462011863 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668462011863 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1668462011977 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X10_Y11 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11" { } { { "loc" "" { Generic "/home/tiagorg/repos/DecoderDemo/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11"} { { 12 { 0 ""} 0 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1668462012210 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1668462012210 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1668462012235 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1668462012235 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1668462012235 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668462012236 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1668462012307 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1668462012310 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1668462012397 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1668462012398 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1668462012591 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1668462012807 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/DecoderDemo/output_files/DecoderDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/DecoderDemo/output_files/DecoderDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1668462012957 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "941 " "Peak virtual memory: 941 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668462013056 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:40:13 2022 " "Processing ended: Mon Nov 14 21:40:13 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668462013056 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668462013056 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668462013056 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1668462013056 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1668462013569 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668462013569 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:40:13 2022 " "Processing started: Mon Nov 14 21:40:13 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668462013569 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1668462013569 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1668462013569 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1668462013663 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1668462013824 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1668462013832 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "352 " "Peak virtual memory: 352 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668462013883 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:40:13 2022 " "Processing ended: Mon Nov 14 21:40:13 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668462013883 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668462013883 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668462013883 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1668462013883 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1668462014024 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1668462014420 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668462014420 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:40:14 2022 " "Processing started: Mon Nov 14 21:40:14 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668462014420 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1668462014420 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DecoderDemo -c DecoderDemo " "Command: quartus_sta DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1668462014420 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1668462014441 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1668462014478 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1668462014478 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1668462014516 ""} +{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1668462014516 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DecoderDemo.sdc " "Synopsys Design Constraints File file not found: 'DecoderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1668462014612 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668462014612 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668462014612 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668462014613 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1668462014613 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668462014613 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1668462014613 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1668462014615 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1668462014615 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014616 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014618 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014619 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014619 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014619 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014620 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668462014621 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1668462014633 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1668462014834 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668462014845 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668462014845 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668462014845 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668462014845 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014845 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014846 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014846 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014847 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014847 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014847 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1668462014848 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1668462014882 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1668462014882 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1668462014882 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1668462014882 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014883 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014883 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014884 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014884 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1668462014884 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668462015083 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1668462015083 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "463 " "Peak virtual memory: 463 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668462015091 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:40:15 2022 " "Processing ended: Mon Nov 14 21:40:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668462015091 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668462015091 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668462015091 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1668462015091 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1668462015560 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1668462015560 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 14 21:40:15 2022 " "Processing started: Mon Nov 14 21:40:15 2022" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1668462015560 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668462015560 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1668462015560 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. 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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1668462015678 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "DecoderDemo.vho /home/tiagorg/repos/DecoderDemo/simulation/modelsim/ simulation " "Generated file DecoderDemo.vho in folder \"/home/tiagorg/repos/DecoderDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1668462015705 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "600 " "Peak virtual memory: 600 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1668462015714 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 14 21:40:15 2022 " "Processing ended: Mon Nov 14 21:40:15 2022" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1668462015714 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1668462015714 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1668462015714 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1668462015714 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 14 s " "Quartus Prime Full Compilation was successful. 0 errors, 14 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1668462015772 ""} diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/README b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.db_info b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.db_info new file mode 100644 index 0000000..b453ba0 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Version_Index = 520278016 +Creation_Time = Fri Nov 4 12:15:36 2022 diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.ammdb b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.ammdb new file mode 100644 index 0000000..e41bd8c Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.ammdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.cdb b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.cdb new file mode 100644 index 0000000..6bb873a Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.cdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.dfp b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.dfp differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.hdb b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.hdb new file mode 100644 index 0000000..eebbbcf Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.hdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.logdb b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.logdb new file mode 100644 index 0000000..626799f --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.rcfdb b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.rcfdb new file mode 100644 index 0000000..71adfbd Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.cmp.rcfdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.cdb b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.cdb new file mode 100644 index 0000000..2c97874 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.cdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.dpi b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.dpi new file mode 100644 index 0000000..558b6f3 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.dpi differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.cdb b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..c21113e Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.cdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.hb_info b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.hb_info differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.hdb b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..83795eb Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.hdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.sig b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.sig new file mode 100644 index 0000000..6c0af65 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +c5eb7f6cdd530884c3b884e0a3668ea4 \ No newline at end of file diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hdb b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hdb new file mode 100644 index 0000000..a5ffc61 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.hdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.kpt b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.kpt new file mode 100644 index 0000000..526b9b1 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.root_partition.map.kpt differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.rrp.hdb b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.rrp.hdb new file mode 100644 index 0000000..571cc52 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/incremental_db/compiled_partitions/DecoderDemo.rrp.hdb differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.asm.rpt b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.asm.rpt new file mode 100644 index 0000000..8d16f93 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.asm.rpt @@ -0,0 +1,92 @@ +Assembler report for DecoderDemo +Mon Nov 14 21:56:49 2022 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: DecoderDemo.sof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Mon Nov 14 21:56:49 2022 ; +; Revision Name ; DecoderDemo ; +; Top-level Entity Name ; Dec2_4 ; +; Family ; Cyclone IV E ; +; Device ; EP4CE6E22C6 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------+ +; Assembler Settings ; ++--------+---------+---------------+ +; Option ; Setting ; Default Value ; ++--------+---------+---------------+ + + ++--------------------------------------------------------------+ +; Assembler Generated Files ; ++--------------------------------------------------------------+ +; File Name ; ++--------------------------------------------------------------+ +; /home/tiagorg/repos/DecoderDemo/output_files/DecoderDemo.sof ; ++--------------------------------------------------------------+ + + ++-------------------------------------------+ +; Assembler Device Options: DecoderDemo.sof ; ++----------------+--------------------------+ +; Option ; Setting ; ++----------------+--------------------------+ +; JTAG usercode ; 0x00093A30 ; +; Checksum ; 0x00093A30 ; ++----------------+--------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Assembler + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Mon Nov 14 21:56:49 2022 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus Prime Assembler was successful. 0 errors, 1 warning + Info: Peak virtual memory: 352 megabytes + Info: Processing ended: Mon Nov 14 21:56:49 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.done b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.done new file mode 100644 index 0000000..bc6e379 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.done @@ -0,0 +1 @@ +Mon Nov 14 21:56:51 2022 diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.eda.rpt b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.eda.rpt new file mode 100644 index 0000000..fd06dc2 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.eda.rpt @@ -0,0 +1,94 @@ +EDA Netlist Writer report for DecoderDemo +Mon Nov 14 21:56:51 2022 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Mon Nov 14 21:56:51 2022 ; +; Revision Name ; DecoderDemo ; +; Top-level Entity Name ; Dec2_4 ; +; Family ; Cyclone IV E ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+------------------------+ +; Tool Name ; ModelSim-Altera (VHDL) ; +; Generate functional simulation netlist ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+------------------------+ + + ++---------------------------------------------------------------------+ +; Simulation Generated Files ; ++---------------------------------------------------------------------+ +; Generated Files ; ++---------------------------------------------------------------------+ +; /home/tiagorg/repos/DecoderDemo/simulation/modelsim/DecoderDemo.vho ; ++---------------------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime EDA Netlist Writer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Mon Nov 14 21:56:51 2022 +Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (204019): Generated file DecoderDemo.vho in folder "/home/tiagorg/repos/DecoderDemo/simulation/modelsim/" for EDA simulation tool +Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 600 megabytes + Info: Processing ended: Mon Nov 14 21:56:51 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:00 + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.fit.rpt b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.fit.rpt new file mode 100644 index 0000000..cceb611 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.fit.rpt @@ -0,0 +1,873 @@ +Fitter report for DecoderDemo +Mon Nov 14 21:56:48 2022 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. Dual Purpose and Dedicated Pins + 14. I/O Bank Usage + 15. All Package Pins + 16. I/O Assignment Warnings + 17. Fitter Resource Utilization by Entity + 18. Delay Chain Summary + 19. Pad To Core Delay Chain Fanout + 20. Routing Usage Summary + 21. LAB Logic Elements + 22. LAB Signals Sourced + 23. LAB Signals Sourced Out + 24. LAB Distinct Inputs + 25. I/O Rules Summary + 26. I/O Rules Details + 27. I/O Rules Matrix + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------+ +; Fitter Status ; Successful - Mon Nov 14 21:56:48 2022 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; DecoderDemo ; +; Top-level Entity Name ; Dec2_4 ; +; Family ; Cyclone IV E ; +; Device ; EP4CE6E22C6 ; +; Timing Models ; Final ; +; Total logic elements ; 4 / 6,272 ( < 1 % ) ; +; Total combinational functions ; 4 / 6,272 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 6,272 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 8 / 92 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 276,480 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; ++------------------------------------+---------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; auto ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Periphery to Core Placement and Routing Optimization ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Auto ; Auto ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++--------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.1% ; ++----------------------------+-------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; ++---------------------+-------------------+----------------------------+--------------------------+ +; Placement (by node) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 31 ) ; 0.00 % ( 0 / 31 ) ; 0.00 % ( 0 / 31 ) ; +; -- Achieved ; 0.00 % ( 0 / 31 ) ; 0.00 % ( 0 / 31 ) ; 0.00 % ( 0 / 31 ) ; +; ; ; ; ; +; Routing (by net) ; ; ; ; +; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; +; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; ++---------------------+-------------------+----------------------------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ +; Top ; 0.00 % ( 0 / 21 ) ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ; ++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in /home/tiagorg/repos/DecoderDemo/output_files/DecoderDemo.pin. + + ++-------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+---------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------+ +; Total logic elements ; 4 / 6,272 ( < 1 % ) ; +; -- Combinational with no register ; 4 ; +; -- Register only ; 0 ; +; -- Combinational with a register ; 0 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 4 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 0 ; +; -- Register only ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 4 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers* ; 0 / 6,684 ( 0 % ) ; +; -- Dedicated logic registers ; 0 / 6,272 ( 0 % ) ; +; -- I/O registers ; 0 / 412 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 1 / 392 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 8 / 92 ( 9 % ) ; +; -- Clock pins ; 1 / 3 ( 33 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; ; ; +; M9Ks ; 0 / 30 ( 0 % ) ; +; Total block memory bits ; 0 / 276,480 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 276,480 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; +; PLLs ; 0 / 2 ( 0 % ) ; +; Global signals ; 0 ; +; -- Global clocks ; 0 / 10 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Oscillator blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0.0% / 0.1% / 0.0% ; +; Peak interconnect usage (total/H/V) ; 0.3% / 0.3% / 0.2% ; +; Maximum fan-out ; 4 ; +; Highest non-global fan-out ; 4 ; +; Total fan-out ; 33 ; +; Average fan-out ; 1.10 ; ++---------------------------------------------+---------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++---------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+--------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+--------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 4 / 6272 ( < 1 % ) ; 0 / 6272 ( 0 % ) ; +; -- Combinational with no register ; 4 ; 0 ; +; -- Register only ; 0 ; 0 ; +; -- Combinational with a register ; 0 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 4 ; 0 ; +; -- 3 input functions ; 0 ; 0 ; +; -- <=2 input functions ; 0 ; 0 ; +; -- Register only ; 0 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 4 ; 0 ; +; -- arithmetic mode ; 0 ; 0 ; +; ; ; ; +; Total registers ; 0 ; 0 ; +; -- Dedicated logic registers ; 0 / 6272 ( 0 % ) ; 0 / 6272 ( 0 % ) ; +; -- I/O registers ; 0 ; 0 ; +; ; ; ; +; Total LABs: partially or completely used ; 1 / 392 ( < 1 % ) ; 0 / 392 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 8 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; 0 / 30 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 28 ; 5 ; +; -- Registered Connections ; 0 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 4 ; 0 ; +; -- Output Ports ; 4 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+--------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ +; E0L ; 30 ; 2 ; 0 ; 8 ; 14 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; E1 ; 24 ; 2 ; 0 ; 11 ; 14 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; X0 ; 25 ; 2 ; 0 ; 11 ; 21 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; +; X1 ; 31 ; 2 ; 0 ; 7 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; Fitter ; no ; ++------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Y0 ; 34 ; 2 ; 0 ; 5 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Y1 ; 28 ; 2 ; 0 ; 9 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Y2 ; 32 ; 2 ; 0 ; 6 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; +; Y3 ; 33 ; 2 ; 0 ; 6 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; Fitter ; - ; - ; ++------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ +; 6 ; DIFFIO_L1n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; 8 ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; 9 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; 12 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; 13 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; 14 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; 21 ; nCE ; - ; - ; Dedicated Programming Pin ; +; 92 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; 94 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; 96 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; 97 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; 97 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; 101 ; DIFFIO_R3n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; ++----------+-----------------------------+--------------------------+-------------------------+---------------------------+ + + ++-----------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-----------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-----------------+---------------+--------------+ +; 1 ; 4 / 11 ( 36 % ) ; 2.5V ; -- ; +; 2 ; 8 / 8 ( 100 % ) ; 2.5V ; -- ; +; 3 ; 0 / 11 ( 0 % ) ; 2.5V ; -- ; +; 4 ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; +; 5 ; 0 / 13 ( 0 % ) ; 2.5V ; -- ; +; 6 ; 1 / 10 ( 10 % ) ; 2.5V ; -- ; +; 7 ; 0 / 13 ( 0 % ) ; 2.5V ; -- ; +; 8 ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; ++----------+-----------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; 1 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 3 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 5 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 6 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 7 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 8 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 9 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; 10 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 11 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 12 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 13 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; 14 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; 15 ; 18 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 16 ; 19 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 17 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 18 ; 20 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 20 ; 21 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 21 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; 22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 23 ; 24 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 24 ; 25 ; 2 ; E1 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 25 ; 26 ; 2 ; X0 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 26 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 28 ; 31 ; 2 ; Y1 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 29 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 30 ; 34 ; 2 ; E0L ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 31 ; 36 ; 2 ; X1 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 32 ; 39 ; 2 ; Y2 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 33 ; 40 ; 2 ; Y3 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 34 ; 41 ; 2 ; Y0 ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 35 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 36 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; 37 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 38 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 39 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 40 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 41 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 42 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 43 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 44 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 45 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 46 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; 47 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 48 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 49 ; 68 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 50 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 51 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 52 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 53 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 54 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 55 ; 75 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 56 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 57 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 58 ; 80 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 59 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 60 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 61 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 62 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 63 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 64 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 65 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; 66 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 67 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 68 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 69 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 70 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 71 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 72 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 73 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 74 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 75 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 76 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 77 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 78 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 80 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 81 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 82 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 83 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 84 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 85 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 86 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 87 ; 121 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 88 ; 125 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 89 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 90 ; 127 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 91 ; 128 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; 92 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; 93 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 94 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; 95 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 96 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; 97 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; 97 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; 98 ; 136 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 99 ; 137 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 100 ; 138 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 101 ; 139 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; 102 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 103 ; 140 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 104 ; 141 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 105 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ; +; 106 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; 107 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 108 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; 109 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 110 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 111 ; 154 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 112 ; 155 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 113 ; 156 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 114 ; 157 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 115 ; 158 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 116 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 117 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 118 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 119 ; 163 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; 120 ; 164 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 121 ; 165 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 122 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 123 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 124 ; 173 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 125 ; 174 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 126 ; 175 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 127 ; 176 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 128 ; 177 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 129 ; 178 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 130 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 131 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 132 ; 181 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 133 ; 182 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 134 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; 135 ; 185 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 136 ; 187 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ; +; 137 ; 190 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 138 ; 191 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 139 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; 140 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 141 ; 195 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 142 ; 201 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 143 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; 144 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; EPAD ; ; ; GND ; ; ; ; -- ; ; -- ; -- ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++------------------------------------------+ +; I/O Assignment Warnings ; ++----------+-------------------------------+ +; Pin Name ; Reason ; ++----------+-------------------------------+ +; Y3 ; Incomplete set of assignments ; +; Y2 ; Incomplete set of assignments ; +; Y1 ; Incomplete set of assignments ; +; Y0 ; Incomplete set of assignments ; +; E1 ; Incomplete set of assignments ; +; X0 ; Incomplete set of assignments ; +; X1 ; Incomplete set of assignments ; +; E0L ; Incomplete set of assignments ; +; Y3 ; Missing location assignment ; +; Y2 ; Missing location assignment ; +; Y1 ; Missing location assignment ; +; Y0 ; Missing location assignment ; +; E1 ; Missing location assignment ; +; X0 ; Missing location assignment ; +; X1 ; Missing location assignment ; +; E0L ; Missing location assignment ; ++----------+-------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+-------------+--------------+ +; |Dec2_4 ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 4 (4) ; 0 (0) ; 0 (0) ; |Dec2_4 ; Dec2_4 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++------+----------+---------------+---------------+-----------------------+-----+------+ +; Y3 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Y2 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Y1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; Y0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; E1 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; X0 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; X1 ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; E0L ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; ++------+----------+---------------+---------------+-----------------------+-----+------+ + + ++---------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++---------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++---------------------+-------------------+---------+ +; E1 ; ; ; +; X0 ; ; ; +; X1 ; ; ; +; - inst ; 0 ; 6 ; +; - inst1 ; 0 ; 6 ; +; - inst3 ; 0 ; 6 ; +; - inst2 ; 0 ; 6 ; +; E0L ; ; ; +; - inst ; 0 ; 6 ; +; - inst1 ; 0 ; 6 ; +; - inst3 ; 0 ; 6 ; +; - inst2 ; 0 ; 6 ; ++---------------------+-------------------+---------+ + + ++----------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+----------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+----------------------+ +; Block interconnects ; 8 / 32,401 ( < 1 % ) ; +; C16 interconnects ; 0 / 1,326 ( 0 % ) ; +; C4 interconnects ; 7 / 21,816 ( < 1 % ) ; +; Direct links ; 0 / 32,401 ( 0 % ) ; +; Global clocks ; 0 / 10 ( 0 % ) ; +; Local interconnects ; 0 / 10,320 ( 0 % ) ; +; R24 interconnects ; 4 / 1,289 ( < 1 % ) ; +; R4 interconnects ; 8 / 28,186 ( < 1 % ) ; ++-----------------------+----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 4.00) ; Number of LABs (Total = 1) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; ++--------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 4.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 4.00) ; Number of LABs (Total = 1) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 4.00) ; Number of LABs (Total = 1) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 9 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 21 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000002 ; IO_000001 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000047 ; IO_000046 ; IO_000045 ; IO_000027 ; IO_000026 ; IO_000024 ; IO_000023 ; IO_000022 ; IO_000021 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 4 ; 4 ; 0 ; 4 ; 0 ; 0 ; 4 ; 0 ; 8 ; 8 ; 8 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 8 ; 8 ; 8 ; 8 ; 8 ; 0 ; 8 ; 8 ; 8 ; 8 ; 8 ; 8 ; 8 ; 4 ; 8 ; 8 ; 8 ; 4 ; 4 ; 8 ; 4 ; 8 ; 8 ; 4 ; 8 ; 0 ; 0 ; 0 ; 8 ; 8 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Y3 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; Y2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; Y1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; Y0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; E1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; X0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; X1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; +; E0L ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (119004): Automatically selected device EP4CE6E22C6 for design DecoderDemo +Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'. +Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE10E22C6 is compatible + Info (176445): Device EP4CE15E22C6 is compatible + Info (176445): Device EP4CE22E22C6 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location 12 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location 13 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location 101 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Critical Warning (169085): No exact pin location assignment(s) for 8 pins of 8 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'DecoderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 8 (unused VREF, 2.5V VCCIO, 4 input, 4 output, 0 bidirectional) + Info (176212): I/O standards used: 2.5 V. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used -- 7 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 8 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 11 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 9 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X10_Y11 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds. +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Info (144001): Generated suppressed messages file /home/tiagorg/repos/DecoderDemo/output_files/DecoderDemo.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings + Info: Peak virtual memory: 942 megabytes + Info: Processing ended: Mon Nov 14 21:56:49 2022 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in /home/tiagorg/repos/DecoderDemo/output_files/DecoderDemo.fit.smsg. + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.fit.smsg b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.fit.smsg new file mode 100644 index 0000000..7121cbb --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.fit.summary b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.fit.summary new file mode 100644 index 0000000..730c2b4 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Mon Nov 14 21:56:48 2022 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : DecoderDemo +Top-level Entity Name : Dec2_4 +Family : Cyclone IV E +Device : EP4CE6E22C6 +Timing Models : Final +Total logic elements : 4 / 6,272 ( < 1 % ) + Total combinational functions : 4 / 6,272 ( < 1 % ) + Dedicated logic registers : 0 / 6,272 ( 0 % ) +Total registers : 0 +Total pins : 8 / 92 ( 9 % ) +Total virtual pins : 0 +Total memory bits : 0 / 276,480 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 30 ( 0 % ) +Total PLLs : 0 / 2 ( 0 % ) diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.flow.rpt b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.flow.rpt new file mode 100644 index 0000000..c7349fa --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.flow.rpt @@ -0,0 +1,132 @@ +Flow report for DecoderDemo +Mon Nov 14 21:56:51 2022 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------+ +; Flow Status ; Successful - Mon Nov 14 21:56:51 2022 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; DecoderDemo ; +; Top-level Entity Name ; Dec2_4 ; +; Family ; Cyclone IV E ; +; Total logic elements ; 4 / 6,272 ( < 1 % ) ; +; Total combinational functions ; 4 / 6,272 ( < 1 % ) ; +; Dedicated logic registers ; 0 / 6,272 ( 0 % ) ; +; Total registers ; 0 ; +; Total pins ; 8 / 92 ( 9 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 276,480 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; +; Total PLLs ; 0 / 2 ( 0 % ) ; +; Device ; EP4CE6E22C6 ; +; Timing Models ; Final ; ++------------------------------------+---------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 11/14/2022 21:56:41 ; +; Main task ; Compilation ; +; Revision Name ; DecoderDemo ; ++-------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +; COMPILER_SIGNATURE_ID ; 198516037997543.166846300130887 ; -- ; -- ; -- ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ; +; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; ; -- ; -- ; +; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; +; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; Dec2_4 ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; Dec2_4 ; Top ; +; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; Dec2_4 ; Top ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; TOP_LEVEL_ENTITY ; Dec2_4 ; DecoderDemo ; -- ; -- ; ++-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 395 MB ; 00:00:13 ; +; Fitter ; 00:00:02 ; 1.0 ; 942 MB ; 00:00:02 ; +; Assembler ; 00:00:00 ; 1.0 ; 352 MB ; 00:00:00 ; +; Timing Analyzer ; 00:00:00 ; 1.0 ; 465 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 600 MB ; 00:00:00 ; +; Total ; 00:00:07 ; -- ; -- ; 00:00:16 ; ++----------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++----------------------+------------------+----------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++----------------------+------------------+----------------+------------+----------------+ +; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ; +; Fitter ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ; +; Assembler ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ; +; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ; +; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.1 ; 22 ; x86_64 ; ++----------------------+------------------+----------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off DecoderDemo -c DecoderDemo +quartus_fit --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo +quartus_asm --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo +quartus_sta DecoderDemo -c DecoderDemo +quartus_eda --read_settings_files=off --write_settings_files=off DecoderDemo -c DecoderDemo + + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.jdi b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.jdi new file mode 100644 index 0000000..6d0170e --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.map.rpt b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.map.rpt new file mode 100644 index 0000000..d2b34fc --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.map.rpt @@ -0,0 +1,280 @@ +Analysis & Synthesis report for DecoderDemo +Mon Nov 14 21:56:46 2022 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. General Register Statistics + 9. Post-Synthesis Netlist Statistics for Top Partition + 10. Elapsed Time Per Partition + 11. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Mon Nov 14 21:56:46 2022 ; +; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Revision Name ; DecoderDemo ; +; Top-level Entity Name ; Dec2_4 ; +; Family ; Cyclone IV E ; +; Total logic elements ; 4 ; +; Total combinational functions ; 4 ; +; Dedicated logic registers ; 0 ; +; Total registers ; 0 ; +; Total pins ; 8 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Top-level entity name ; Dec2_4 ; DecoderDemo ; +; Family name ; Cyclone IV E ; Cyclone V ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------+---------+ +; Dec2_4.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/DecoderDemo/Dec2_4.bdf ; ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------+---------+ + + ++--------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------+ +; Resource ; Usage ; ++---------------------------------------------+----------+ +; Estimated Total logic elements ; 4 ; +; ; ; +; Total combinational functions ; 4 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 4 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 0 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 4 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 8 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; E1~input ; +; Maximum fan-out ; 4 ; +; Total fan-out ; 28 ; +; Average fan-out ; 1.40 ; ++---------------------------------------------+----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+ +; |Dec2_4 ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 8 ; 0 ; |Dec2_4 ; Dec2_4 ; work ; ++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+---------------------+-------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 0 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 0 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++-----------------------------------------------------+ +; Post-Synthesis Netlist Statistics for Top Partition ; ++-----------------------+-----------------------------+ +; Type ; Count ; ++-----------------------+-----------------------------+ +; boundary_port ; 8 ; +; cycloneiii_lcell_comb ; 4 ; +; normal ; 4 ; +; 4 data inputs ; 4 ; +; ; ; +; Max LUT depth ; 1.00 ; +; Average LUT depth ; 1.00 ; ++-----------------------+-----------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Mon Nov 14 21:56:41 2022 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DecoderDemo -c DecoderDemo +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (12021): Found 1 design units, including 1 entities, in source file Dec2_4.bdf + Info (12023): Found entity 1: Dec2_4 +Info (12127): Elaborating entity "Dec2_4" for the top level hierarchy +Info (286030): Timing-Driven Synthesis is running +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 12 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 4 input pins + Info (21059): Implemented 4 output pins + Info (21061): Implemented 4 logic cells +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 402 megabytes + Info: Processing ended: Mon Nov 14 21:56:46 2022 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:13 + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.map.summary b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.map.summary new file mode 100644 index 0000000..19dd9b6 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Mon Nov 14 21:56:46 2022 +Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition +Revision Name : DecoderDemo +Top-level Entity Name : Dec2_4 +Family : Cyclone IV E +Total logic elements : 4 + Total combinational functions : 4 + Dedicated logic registers : 0 +Total registers : 0 +Total pins : 8 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.pin b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.pin new file mode 100644 index 0000000..b9de1a5 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.pin @@ -0,0 +1,216 @@ + -- Copyright (C) 2020 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +CHIP "DecoderDemo" ASSIGNED TO AN: EP4CE6E22C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 3 : : : : 1 : +GND : 4 : gnd : : : : +VCCINT : 5 : power : : 1.2V : : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 6 : input : 2.5 V : : 1 : N +RESERVED_INPUT_WITH_WEAK_PULLUP : 7 : : : : 1 : +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 8 : input : 2.5 V : : 1 : N +nSTATUS : 9 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 10 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 11 : : : : 1 : +~ALTERA_DCLK~ : 12 : output : 2.5 V : : 1 : N +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 13 : input : 2.5 V : : 1 : N +nCONFIG : 14 : : : : 1 : +TDI : 15 : input : : : 1 : +TCK : 16 : input : : : 1 : +VCCIO1 : 17 : power : : 2.5V : 1 : +TMS : 18 : input : : : 1 : +GND : 19 : gnd : : : : +TDO : 20 : output : : : 1 : +nCE : 21 : : : : 1 : +GND : 22 : gnd : : : : +GND+ : 23 : : : : 1 : +E1 : 24 : input : 2.5 V : : 2 : N +X0 : 25 : input : 2.5 V : : 2 : N +VCCIO2 : 26 : power : : 2.5V : 2 : +GND : 27 : gnd : : : : +Y1 : 28 : output : 2.5 V : : 2 : N +VCCINT : 29 : power : : 1.2V : : +E0L : 30 : input : 2.5 V : : 2 : N +X1 : 31 : input : 2.5 V : : 2 : N +Y2 : 32 : output : 2.5 V : : 2 : N +Y3 : 33 : output : 2.5 V : : 2 : N +Y0 : 34 : output : 2.5 V : : 2 : N +VCCA1 : 35 : power : : 2.5V : : +GNDA1 : 36 : gnd : : : : +VCCD_PLL1 : 37 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 38 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 39 : : : : 3 : +VCCIO3 : 40 : power : : 2.5V : 3 : +GND : 41 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 42 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 43 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 44 : : : : 3 : +VCCINT : 45 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 46 : : : : 3 : +VCCIO3 : 47 : power : : 2.5V : 3 : +GND : 48 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 49 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 50 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 51 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 52 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 53 : : : : 3 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 54 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 55 : : : : 4 : +VCCIO4 : 56 : power : : 2.5V : 4 : +GND : 57 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 58 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 59 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 60 : : : : 4 : +VCCINT : 61 : power : : 1.2V : : +VCCIO4 : 62 : power : : 2.5V : 4 : +GND : 63 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 64 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 65 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 66 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 67 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 68 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 69 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 70 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 71 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 72 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 73 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 74 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 75 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 76 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 77 : : : : 5 : +VCCINT : 78 : power : : 1.2V : : +GND : 79 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 80 : : : : 5 : +VCCIO5 : 81 : power : : 2.5V : 5 : +GND : 82 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 83 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 84 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 85 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 86 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 87 : : : : 5 : +GND+ : 88 : : : : 5 : +GND+ : 89 : : : : 5 : +GND+ : 90 : : : : 6 : +GND+ : 91 : : : : 6 : +CONF_DONE : 92 : : : : 6 : +VCCIO6 : 93 : power : : 2.5V : 6 : +MSEL0 : 94 : : : : 6 : +GND : 95 : gnd : : : : +MSEL1 : 96 : : : : 6 : +MSEL2 : 97 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 98 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 99 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 100 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : 101 : output : 2.5 V : : 6 : N +VCCINT : 102 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 103 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 104 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 105 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 106 : : : : 6 : +VCCA2 : 107 : power : : 2.5V : : +GNDA2 : 108 : gnd : : : : +VCCD_PLL2 : 109 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 110 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 111 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 112 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 113 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 114 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 115 : : : : 7 : +VCCINT : 116 : power : : 1.2V : : +VCCIO7 : 117 : power : : 2.5V : 7 : +GND : 118 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 119 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 120 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 121 : : : : 7 : +VCCIO7 : 122 : power : : 2.5V : 7 : +GND : 123 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 124 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 125 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 126 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 127 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 128 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 129 : : : : 8 : +VCCIO8 : 130 : power : : 2.5V : 8 : +GND : 131 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 132 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 133 : : : : 8 : +VCCINT : 134 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 135 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 136 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 137 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 138 : : : : 8 : +VCCIO8 : 139 : power : : 2.5V : 8 : +GND : 140 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : 141 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 142 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 143 : : : : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : 144 : : : : 8 : +GND : EPAD : : : : : diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sld b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sld new file mode 100644 index 0000000..f7d3ed7 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sld @@ -0,0 +1 @@ + diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sof b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sof new file mode 100644 index 0000000..f0a1ec8 Binary files /dev/null and b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sof differ diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sta.rpt b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sta.rpt new file mode 100644 index 0000000..6448284 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sta.rpt @@ -0,0 +1,455 @@ +Timing Analyzer report for DecoderDemo +Mon Nov 14 21:56:50 2022 +Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow 1200mV 85C Model Fmax Summary + 6. Timing Closure Recommendations + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Slow 1200mV 85C Model Metastability Summary + 13. Slow 1200mV 0C Model Fmax Summary + 14. Slow 1200mV 0C Model Setup Summary + 15. Slow 1200mV 0C Model Hold Summary + 16. Slow 1200mV 0C Model Recovery Summary + 17. Slow 1200mV 0C Model Removal Summary + 18. Slow 1200mV 0C Model Minimum Pulse Width Summary + 19. Slow 1200mV 0C Model Metastability Summary + 20. Fast 1200mV 0C Model Setup Summary + 21. Fast 1200mV 0C Model Hold Summary + 22. Fast 1200mV 0C Model Recovery Summary + 23. Fast 1200mV 0C Model Removal Summary + 24. Fast 1200mV 0C Model Minimum Pulse Width Summary + 25. Fast 1200mV 0C Model Metastability Summary + 26. Multicorner Timing Analysis Summary + 27. Board Trace Model Assignments + 28. Input Transition Times + 29. Signal Integrity Metrics (Slow 1200mv 0c Model) + 30. Signal Integrity Metrics (Slow 1200mv 85c Model) + 31. Signal Integrity Metrics (Fast 1200mv 0c Model) + 32. Clock Transfers + 33. Report TCCS + 34. Report RSKM + 35. Unconstrained Paths Summary + 36. Unconstrained Input Ports + 37. Unconstrained Output Ports + 38. Unconstrained Input Ports + 39. Unconstrained Output Ports + 40. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; DecoderDemo ; +; Device Family ; Cyclone IV E ; +; Device Name ; EP4CE6E22C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.1% ; ++----------------------------+-------------+ + + +---------- +; Clocks ; +---------- +No clocks to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Fmax Summary ; +-------------------------------------- +No paths to report. + + +---------------------------------- +; Timing Closure Recommendations ; +---------------------------------- +HTML report is unavailable in plain text report export. + + +--------------------------------------- +; Slow 1200mV 85C Model Setup Summary ; +--------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------------ +; Slow 1200mV 85C Model Recovery Summary ; +------------------------------------------ +No paths to report. + + +----------------------------------------- +; Slow 1200mV 85C Model Removal Summary ; +----------------------------------------- +No paths to report. + + +----------------------------------------------------- +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +----------------------------------------------------- +No paths to report. + + +----------------------------------------------- +; Slow 1200mV 85C Model Metastability Summary ; +----------------------------------------------- +No synchronizer chains to report. + + +------------------------------------- +; Slow 1200mV 0C Model Fmax Summary ; +------------------------------------- +No paths to report. + + +-------------------------------------- +; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Slow 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Slow 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Slow 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Slow 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + +-------------------------------------- +; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------- +No paths to report. + + +------------------------------------- +; Fast 1200mV 0C Model Hold Summary ; +------------------------------------- +No paths to report. + + +----------------------------------------- +; Fast 1200mV 0C Model Recovery Summary ; +----------------------------------------- +No paths to report. + + +---------------------------------------- +; Fast 1200mV 0C Model Removal Summary ; +---------------------------------------- +No paths to report. + + +---------------------------------------------------- +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +---------------------------------------------------- +No paths to report. + + +---------------------------------------------- +; Fast 1200mV 0C Model Metastability Summary ; +---------------------------------------------- +No synchronizer chains to report. + + ++----------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+-------+------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+-------+------+----------+---------+---------------------+ +; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; N/A ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ++------------------+-------+------+----------+---------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Y3 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Y2 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Y1 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; Y0 ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; E1 ; 2.5 V ; 2000 ps ; 2000 ps ; +; X0 ; 2.5 V ; 2000 ps ; 2000 ps ; +; X1 ; 2.5 V ; 2000 ps ; 2000 ps ; +; E0L ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Y3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; +; Y2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; +; Y1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; Y0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.45e-09 V ; 2.38 V ; -0.0609 V ; 0.148 V ; 0.095 V ; 2.82e-10 s ; 2.59e-10 s ; Yes ; Yes ; 2.32 V ; 3.45e-09 V ; 2.38 V ; -0.0609 V ; 0.148 V ; 0.095 V ; 2.82e-10 s ; 2.59e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.61e-09 V ; 2.38 V ; -0.00274 V ; 0.141 V ; 0.006 V ; 4.7e-10 s ; 6.02e-10 s ; Yes ; Yes ; 2.32 V ; 5.61e-09 V ; 2.38 V ; -0.00274 V ; 0.141 V ; 0.006 V ; 4.7e-10 s ; 6.02e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Y3 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; +; Y2 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; +; Y1 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; Y0 ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.74e-07 V ; 2.36 V ; -0.0201 V ; 0.072 V ; 0.033 V ; 4.04e-10 s ; 3.29e-10 s ; Yes ; Yes ; 2.32 V ; 5.74e-07 V ; 2.36 V ; -0.0201 V ; 0.072 V ; 0.033 V ; 4.04e-10 s ; 3.29e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.45e-07 V ; 2.35 V ; -0.00643 V ; 0.081 V ; 0.031 V ; 5.31e-10 s ; 7.59e-10 s ; Yes ; Yes ; 2.32 V ; 9.45e-07 V ; 2.35 V ; -0.00643 V ; 0.081 V ; 0.031 V ; 5.31e-10 s ; 7.59e-10 s ; Yes ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Y3 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; Y2 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; Y1 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; Y0 ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + +------------------- +; Clock Transfers ; +------------------- +Nothing to report. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 4 ; 4 ; +; Unconstrained Input Port Paths ; 16 ; 16 ; +; Unconstrained Output Ports ; 4 ; 4 ; +; Unconstrained Output Port Paths ; 16 ; 16 ; ++---------------------------------+-------+------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; E0L ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; E1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; X0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; X1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Y0 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Y1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Y2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Y3 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; E0L ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; E1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; X0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; X1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; Y0 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Y1 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Y2 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Y3 ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition + Info: Processing started: Mon Nov 14 21:56:50 2022 +Info: Command: quartus_sta DecoderDemo -c DecoderDemo +Info: qsta_default_script.tcl version: #1 +Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected +Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'. +Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. +Critical Warning (332012): Synopsys Design Constraints File file not found: 'DecoderDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332159): No clocks to report +Info: Analyzing Slow 1200mV 85C Model +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No fmax paths to report +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info: Analyzing Fast 1200mV 0C Model +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. +Warning (332068): No clocks defined in design. +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332140): No Setup paths to report +Info (332140): No Hold paths to report +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332140): No Minimum Pulse Width paths to report +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 465 megabytes + Info: Processing ended: Mon Nov 14 21:56:50 2022 + Info: Elapsed time: 00:00:00 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sta.summary b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sta.summary new file mode 100644 index 0000000..aa5b327 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/output_files/DecoderDemo.sta.summary @@ -0,0 +1,5 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +------------------------------------------------------------ diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/DecoderDemo.sft b/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/DecoderDemo.sft new file mode 100644 index 0000000..0c5034b --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/DecoderDemo.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (VHDL)" diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/DecoderDemo.vho b/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/DecoderDemo.vho new file mode 100644 index 0000000..1f49a6a --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/DecoderDemo.vho @@ -0,0 +1,328 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- VENDOR "Altera" +-- PROGRAM "Quartus Prime" +-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" + +-- DATE "11/14/2022 21:56:51" + +-- +-- Device: Altera EP4CE6E22C6 Package TQFP144 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY hard_block IS + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic + ); +END hard_block; + +-- Design Ports Information +-- ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA + + +ARCHITECTURE structure OF hard_block IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic; +SIGNAL \~ALTERA_DATA0~~padout\ : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic; + +BEGIN + +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +END structure; + + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY Dec2_4 IS + PORT ( + Y3 : OUT std_logic; + E0L : IN std_logic; + E1 : IN std_logic; + X1 : IN std_logic; + X0 : IN std_logic; + Y2 : OUT std_logic; + Y1 : OUT std_logic; + Y0 : OUT std_logic + ); +END Dec2_4; + +-- Design Ports Information +-- Y3 => Location: PIN_33, I/O Standard: 2.5 V, Current Strength: Default +-- Y2 => Location: PIN_32, I/O Standard: 2.5 V, Current Strength: Default +-- Y1 => Location: PIN_28, I/O Standard: 2.5 V, Current Strength: Default +-- Y0 => Location: PIN_34, I/O Standard: 2.5 V, Current Strength: Default +-- E1 => Location: PIN_24, I/O Standard: 2.5 V, Current Strength: Default +-- X0 => Location: PIN_25, I/O Standard: 2.5 V, Current Strength: Default +-- X1 => Location: PIN_31, I/O Standard: 2.5 V, Current Strength: Default +-- E0L => Location: PIN_30, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF Dec2_4 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_Y3 : std_logic; +SIGNAL ww_E0L : std_logic; +SIGNAL ww_E1 : std_logic; +SIGNAL ww_X1 : std_logic; +SIGNAL ww_X0 : std_logic; +SIGNAL ww_Y2 : std_logic; +SIGNAL ww_Y1 : std_logic; +SIGNAL ww_Y0 : std_logic; +SIGNAL \Y3~output_o\ : std_logic; +SIGNAL \Y2~output_o\ : std_logic; +SIGNAL \Y1~output_o\ : std_logic; +SIGNAL \Y0~output_o\ : std_logic; +SIGNAL \E1~input_o\ : std_logic; +SIGNAL \X1~input_o\ : std_logic; +SIGNAL \X0~input_o\ : std_logic; +SIGNAL \E0L~input_o\ : std_logic; +SIGNAL \inst~combout\ : std_logic; +SIGNAL \inst1~combout\ : std_logic; +SIGNAL \inst3~combout\ : std_logic; +SIGNAL \inst2~combout\ : std_logic; + +COMPONENT hard_block + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic); +END COMPONENT; + +BEGIN + +Y3 <= ww_Y3; +ww_E0L <= E0L; +ww_E1 <= E1; +ww_X1 <= X1; +ww_X0 <= X0; +Y2 <= ww_Y2; +Y1 <= ww_Y1; +Y0 <= ww_Y0; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +auto_generated_inst : hard_block +PORT MAP ( + devoe => ww_devoe, + devclrn => ww_devclrn, + devpor => ww_devpor); + +-- Location: IOOBUF_X0_Y6_N23 +\Y3~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst~combout\, + devoe => ww_devoe, + o => \Y3~output_o\); + +-- Location: IOOBUF_X0_Y6_N16 +\Y2~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1~combout\, + devoe => ww_devoe, + o => \Y2~output_o\); + +-- Location: IOOBUF_X0_Y9_N9 +\Y1~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3~combout\, + devoe => ww_devoe, + o => \Y1~output_o\); + +-- Location: IOOBUF_X0_Y5_N16 +\Y0~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2~combout\, + devoe => ww_devoe, + o => \Y0~output_o\); + +-- Location: IOIBUF_X0_Y11_N15 +\E1~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_E1, + o => \E1~input_o\); + +-- Location: IOIBUF_X0_Y7_N1 +\X1~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_X1, + o => \X1~input_o\); + +-- Location: IOIBUF_X0_Y11_N22 +\X0~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_X0, + o => \X0~input_o\); + +-- Location: IOIBUF_X0_Y8_N15 +\E0L~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_E0L, + o => \E0L~input_o\); + +-- Location: LCCOMB_X6_Y9_N8 +inst : cycloneive_lcell_comb +-- Equation(s): +-- \inst~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst~combout\); + +-- Location: LCCOMB_X6_Y9_N2 +inst1 : cycloneive_lcell_comb +-- Equation(s): +-- \inst1~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst1~combout\); + +-- Location: LCCOMB_X6_Y9_N28 +inst3 : cycloneive_lcell_comb +-- Equation(s): +-- \inst3~combout\ = (\E1~input_o\ & (\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst3~combout\); + +-- Location: LCCOMB_X6_Y9_N30 +inst2 : cycloneive_lcell_comb +-- Equation(s): +-- \inst2~combout\ = (\E1~input_o\ & (\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst2~combout\); + +ww_Y3 <= \Y3~output_o\; + +ww_Y2 <= \Y2~output_o\; + +ww_Y1 <= \Y1~output_o\; + +ww_Y0 <= \Y0~output_o\; +END structure; + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/DecoderDemo_modelsim.xrf b/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/DecoderDemo_modelsim.xrf new file mode 100644 index 0000000..ec369e7 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/DecoderDemo_modelsim.xrf @@ -0,0 +1,16 @@ +vendor_name = ModelSim +source_file = 1, /home/tiagorg/repos/DecoderDemo/Dec2_4.bdf +source_file = 1, /home/tiagorg/repos/DecoderDemo/WaveformDecoderNode.vwf +source_file = 1, /home/tiagorg/repos/DecoderDemo/Waveform.vwf +source_file = 1, /home/tiagorg/repos/DecoderDemo/Waveform1.vwf +source_file = 1, /home/tiagorg/repos/DecoderDemo/db/DecoderDemo.cbx.xml +design_name = hard_block +design_name = Dec2_4 +instance = comp, \Y3~output\, Y3~output, Dec2_4, 1 +instance = comp, \Y2~output\, Y2~output, Dec2_4, 1 +instance = comp, \Y1~output\, Y1~output, Dec2_4, 1 +instance = comp, \Y0~output\, Y0~output, Dec2_4, 1 +instance = comp, \E1~input\, E1~input, Dec2_4, 1 +instance = comp, \X1~input\, X1~input, Dec2_4, 1 +instance = comp, \X0~input\, X0~input, Dec2_4, 1 +instance = comp, \E0L~input\, E0L~input, Dec2_4, 1 diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/WaveformDecoderNode.vwf.do b/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/WaveformDecoderNode.vwf.do new file mode 100644 index 0000000..c1b0f63 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/WaveformDecoderNode.vwf.do @@ -0,0 +1,4 @@ +vcom -work work WaveformDecoderNode.vwf.vht +vsim -novopt -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst -voptargs="+acc" +add wave /* +run -all diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/WaveformDecoderNode.vwf.vht b/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/WaveformDecoderNode.vwf.vht new file mode 100644 index 0000000..0a22283 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/modelsim/WaveformDecoderNode.vwf.vht @@ -0,0 +1,118 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- ***************************************************************************** +-- This file contains a Vhdl test bench with test vectors .The test vectors +-- are exported from a vector file in the Quartus Waveform Editor and apply to +-- the top level entity of the current Quartus project .The user can use this +-- testbench to simulate his design using a third-party simulation tool . +-- ***************************************************************************** +-- Generated on "11/04/2022 12:48:42" + +-- Vhdl Test Bench(with test vectors) for design : Dec2_4 +-- +-- Simulation tool : 3rd Party +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY Dec2_4_vhd_vec_tst IS +END Dec2_4_vhd_vec_tst; +ARCHITECTURE Dec2_4_arch OF Dec2_4_vhd_vec_tst IS +-- constants +-- signals +SIGNAL E0L : STD_LOGIC; +SIGNAL E1 : STD_LOGIC; +SIGNAL X0 : STD_LOGIC; +SIGNAL X1 : STD_LOGIC; +SIGNAL Y0 : STD_LOGIC; +SIGNAL Y1 : STD_LOGIC; +SIGNAL Y2 : STD_LOGIC; +SIGNAL Y3 : STD_LOGIC; +COMPONENT Dec2_4 + PORT ( + E0L : IN STD_LOGIC; + E1 : IN STD_LOGIC; + X0 : IN STD_LOGIC; + X1 : IN STD_LOGIC; + Y0 : OUT STD_LOGIC; + Y1 : OUT STD_LOGIC; + Y2 : OUT STD_LOGIC; + Y3 : OUT STD_LOGIC + ); +END COMPONENT; +BEGIN + i1 : Dec2_4 + PORT MAP ( +-- list connections between master ports and signals + E0L => E0L, + E1 => E1, + X0 => X0, + X1 => X1, + Y0 => Y0, + Y1 => Y1, + Y2 => Y2, + Y3 => Y3 + ); + +-- E0L +t_prcs_E0L: PROCESS +BEGIN +LOOP + E0L <= '0'; + WAIT FOR 100000 ps; + E0L <= '1'; + WAIT FOR 100000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_E0L; + +-- E1 +t_prcs_E1: PROCESS +BEGIN +LOOP + E1 <= '0'; + WAIT FOR 50000 ps; + E1 <= '1'; + WAIT FOR 50000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_E1; + +-- X1 +t_prcs_X1: PROCESS +BEGIN +LOOP + X1 <= '0'; + WAIT FOR 25000 ps; + X1 <= '1'; + WAIT FOR 25000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_X1; + +-- X0 +t_prcs_X0: PROCESS +BEGIN +LOOP + X0 <= '0'; + WAIT FOR 12500 ps; + X0 <= '1'; + WAIT FOR 12500 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_X0; +END Dec2_4_arch; diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.do b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.do new file mode 100644 index 0000000..58c4d91 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.do @@ -0,0 +1,17 @@ +onerror {exit -code 1} +vlib work +vcom -work work DecoderDemo.vho +vcom -work work Waveform1.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst +vcd file -direction DecoderDemo.msim.vcd +vcd add -internal Dec2_4_vhd_vec_tst/* +vcd add -internal Dec2_4_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.msim.vcd b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.msim.vcd new file mode 100644 index 0000000..4d95cfb --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.msim.vcd @@ -0,0 +1,775 @@ +$comment + File created using the following command: + vcd file DecoderDemo.msim.vcd -direction +$end +$date + Mon Nov 14 21:42:31 2022 +$end +$version + ModelSim Version 2020.1 +$end +$timescale + 1ps +$end + +$scope module dec2_4_vhd_vec_tst $end +$var wire 1 ! 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All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- VENDOR "Altera" +-- PROGRAM "Quartus Prime" +-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" + +-- DATE "11/14/2022 21:42:31" + +-- +-- Device: Altera EP4CE6E22C6 Package TQFP144 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY hard_block IS + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic + ); +END hard_block; + +-- Design Ports Information +-- ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA + + +ARCHITECTURE structure OF hard_block IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic; +SIGNAL \~ALTERA_DATA0~~padout\ : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic; + +BEGIN + +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +END structure; + + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY Dec2_4 IS + PORT ( + Y3 : OUT std_logic; + E0L : IN std_logic; + E1 : IN std_logic; + X1 : IN std_logic; + X0 : IN std_logic; + Y2 : OUT std_logic; + Y1 : OUT std_logic; + Y0 : OUT std_logic + ); +END Dec2_4; + +-- Design Ports Information +-- Y3 => Location: PIN_33, I/O Standard: 2.5 V, Current Strength: Default +-- Y2 => Location: PIN_32, I/O Standard: 2.5 V, Current Strength: Default +-- Y1 => Location: PIN_28, I/O Standard: 2.5 V, Current Strength: Default +-- Y0 => Location: PIN_34, I/O Standard: 2.5 V, Current Strength: Default +-- E1 => Location: PIN_24, I/O Standard: 2.5 V, Current Strength: Default +-- X0 => Location: PIN_25, I/O Standard: 2.5 V, Current Strength: Default +-- X1 => Location: PIN_31, I/O Standard: 2.5 V, Current Strength: Default +-- E0L => Location: PIN_30, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF Dec2_4 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_Y3 : std_logic; +SIGNAL ww_E0L : std_logic; +SIGNAL ww_E1 : std_logic; +SIGNAL ww_X1 : std_logic; +SIGNAL ww_X0 : std_logic; +SIGNAL ww_Y2 : std_logic; +SIGNAL ww_Y1 : std_logic; +SIGNAL ww_Y0 : std_logic; +SIGNAL \Y3~output_o\ : std_logic; +SIGNAL \Y2~output_o\ : std_logic; +SIGNAL \Y1~output_o\ : std_logic; +SIGNAL \Y0~output_o\ : std_logic; +SIGNAL \E1~input_o\ : std_logic; +SIGNAL \X1~input_o\ : std_logic; +SIGNAL \X0~input_o\ : std_logic; +SIGNAL \E0L~input_o\ : std_logic; +SIGNAL \inst~combout\ : std_logic; +SIGNAL \inst1~combout\ : std_logic; +SIGNAL \inst3~combout\ : std_logic; +SIGNAL \inst2~combout\ : std_logic; + +COMPONENT hard_block + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic); +END COMPONENT; + +BEGIN + +Y3 <= ww_Y3; +ww_E0L <= E0L; +ww_E1 <= E1; +ww_X1 <= X1; +ww_X0 <= X0; +Y2 <= ww_Y2; +Y1 <= ww_Y1; +Y0 <= ww_Y0; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +auto_generated_inst : hard_block +PORT MAP ( + devoe => ww_devoe, + devclrn => ww_devclrn, + devpor => ww_devpor); + +-- Location: IOOBUF_X0_Y6_N23 +\Y3~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst~combout\, + devoe => ww_devoe, + o => \Y3~output_o\); + +-- Location: IOOBUF_X0_Y6_N16 +\Y2~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1~combout\, + devoe => ww_devoe, + o => \Y2~output_o\); + +-- Location: IOOBUF_X0_Y9_N9 +\Y1~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3~combout\, + devoe => ww_devoe, + o => \Y1~output_o\); + +-- Location: IOOBUF_X0_Y5_N16 +\Y0~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2~combout\, + devoe => ww_devoe, + o => \Y0~output_o\); + +-- Location: IOIBUF_X0_Y11_N15 +\E1~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_E1, + o => \E1~input_o\); + +-- Location: IOIBUF_X0_Y7_N1 +\X1~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_X1, + o => \X1~input_o\); + +-- Location: IOIBUF_X0_Y11_N22 +\X0~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_X0, + o => \X0~input_o\); + +-- Location: IOIBUF_X0_Y8_N15 +\E0L~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_E0L, + o => \E0L~input_o\); + +-- Location: LCCOMB_X6_Y9_N8 +inst : cycloneive_lcell_comb +-- Equation(s): +-- \inst~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst~combout\); + +-- Location: LCCOMB_X6_Y9_N2 +inst1 : cycloneive_lcell_comb +-- Equation(s): +-- \inst1~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst1~combout\); + +-- Location: LCCOMB_X6_Y9_N28 +inst3 : cycloneive_lcell_comb +-- Equation(s): +-- \inst3~combout\ = (\E1~input_o\ & (\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst3~combout\); + +-- Location: LCCOMB_X6_Y9_N30 +inst2 : cycloneive_lcell_comb +-- Equation(s): +-- \inst2~combout\ = (\E1~input_o\ & (\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst2~combout\); + +ww_Y3 <= \Y3~output_o\; + +ww_Y2 <= \Y2~output_o\; + +ww_Y1 <= \Y1~output_o\; + +ww_Y0 <= \Y0~output_o\; +END structure; + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.vo b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.vo new file mode 100644 index 0000000..cce1ee5 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo.vo @@ -0,0 +1,294 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// VENDOR "Altera" +// PROGRAM "Quartus Prime" +// VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" + +// DATE "11/14/2022 21:42:11" + +// +// Device: Altera EP4CE6E22C6 Package TQFP144 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module Dec2_4 ( + Y3, + E0L, + E1, + X1, + X0, + Y2, + Y1, + Y0); +output Y3; +input E0L; +input E1; +input X1; +input X0; +output Y2; +output Y1; +output Y0; + +// Design Ports Information +// Y3 => Location: PIN_33, I/O Standard: 2.5 V, Current Strength: Default +// Y2 => Location: PIN_32, I/O Standard: 2.5 V, Current Strength: Default +// Y1 => Location: PIN_28, I/O Standard: 2.5 V, Current Strength: Default +// Y0 => Location: PIN_34, I/O Standard: 2.5 V, Current Strength: Default +// E1 => Location: PIN_24, I/O Standard: 2.5 V, Current Strength: Default +// X0 => Location: PIN_25, I/O Standard: 2.5 V, Current Strength: Default +// X1 => Location: PIN_31, I/O Standard: 2.5 V, Current Strength: Default +// E0L => Location: PIN_30, I/O Standard: 2.5 V, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \Y3~output_o ; +wire \Y2~output_o ; +wire \Y1~output_o ; +wire \Y0~output_o ; +wire \E1~input_o ; +wire \X1~input_o ; +wire \X0~input_o ; +wire \E0L~input_o ; +wire \inst~combout ; +wire \inst1~combout ; +wire \inst3~combout ; +wire \inst2~combout ; + + +hard_block auto_generated_inst( + .devpor(devpor), + .devclrn(devclrn), + .devoe(devoe)); + +// Location: IOOBUF_X0_Y6_N23 +cycloneive_io_obuf \Y3~output ( + .i(\inst~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Y3~output_o ), + .obar()); +// synopsys translate_off +defparam \Y3~output .bus_hold = "false"; +defparam \Y3~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y6_N16 +cycloneive_io_obuf \Y2~output ( + .i(\inst1~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Y2~output_o ), + .obar()); +// synopsys translate_off +defparam \Y2~output .bus_hold = "false"; +defparam \Y2~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y9_N9 +cycloneive_io_obuf \Y1~output ( + .i(\inst3~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Y1~output_o ), + .obar()); +// synopsys translate_off +defparam \Y1~output .bus_hold = "false"; +defparam \Y1~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOOBUF_X0_Y5_N16 +cycloneive_io_obuf \Y0~output ( + .i(\inst2~combout ), + .oe(vcc), + .seriesterminationcontrol(16'b0000000000000000), + .devoe(devoe), + .o(\Y0~output_o ), + .obar()); +// synopsys translate_off +defparam \Y0~output .bus_hold = "false"; +defparam \Y0~output .open_drain_output = "false"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N15 +cycloneive_io_ibuf \E1~input ( + .i(E1), + .ibar(gnd), + .o(\E1~input_o )); +// synopsys translate_off +defparam \E1~input .bus_hold = "false"; +defparam \E1~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y7_N1 +cycloneive_io_ibuf \X1~input ( + .i(X1), + .ibar(gnd), + .o(\X1~input_o )); +// synopsys translate_off +defparam \X1~input .bus_hold = "false"; +defparam \X1~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y11_N22 +cycloneive_io_ibuf \X0~input ( + .i(X0), + .ibar(gnd), + .o(\X0~input_o )); +// synopsys translate_off +defparam \X0~input .bus_hold = "false"; +defparam \X0~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: IOIBUF_X0_Y8_N15 +cycloneive_io_ibuf \E0L~input ( + .i(E0L), + .ibar(gnd), + .o(\E0L~input_o )); +// synopsys translate_off +defparam \E0L~input .bus_hold = "false"; +defparam \E0L~input .simulate_z_as = "z"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N8 +cycloneive_lcell_comb inst( +// Equation(s): +// \inst~combout = (\E1~input_o & (!\X1~input_o & (!\X0~input_o & !\E0L~input_o ))) + + .dataa(\E1~input_o ), + .datab(\X1~input_o ), + .datac(\X0~input_o ), + .datad(\E0L~input_o ), + .cin(gnd), + .combout(\inst~combout ), + .cout()); +// synopsys translate_off +defparam inst.lut_mask = 16'h0002; +defparam inst.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N2 +cycloneive_lcell_comb inst1( +// Equation(s): +// \inst1~combout = (\E1~input_o & (!\X1~input_o & (\X0~input_o & !\E0L~input_o ))) + + .dataa(\E1~input_o ), + .datab(\X1~input_o ), + .datac(\X0~input_o ), + .datad(\E0L~input_o ), + .cin(gnd), + .combout(\inst1~combout ), + .cout()); +// synopsys translate_off +defparam inst1.lut_mask = 16'h0020; +defparam inst1.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N28 +cycloneive_lcell_comb inst3( +// Equation(s): +// \inst3~combout = (\E1~input_o & (\X1~input_o & (\X0~input_o & !\E0L~input_o ))) + + .dataa(\E1~input_o ), + .datab(\X1~input_o ), + .datac(\X0~input_o ), + .datad(\E0L~input_o ), + .cin(gnd), + .combout(\inst3~combout ), + .cout()); +// synopsys translate_off +defparam inst3.lut_mask = 16'h0080; +defparam inst3.sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X6_Y9_N30 +cycloneive_lcell_comb inst2( +// Equation(s): +// \inst2~combout = (\E1~input_o & (\X1~input_o & (!\X0~input_o & !\E0L~input_o ))) + + .dataa(\E1~input_o ), + .datab(\X1~input_o ), + .datac(\X0~input_o ), + .datad(\E0L~input_o ), + .cin(gnd), + .combout(\inst2~combout ), + .cout()); +// synopsys translate_off +defparam inst2.lut_mask = 16'h0008; +defparam inst2.sum_lutc_input = "datac"; +// synopsys translate_on + +assign Y3 = \Y3~output_o ; + +assign Y2 = \Y2~output_o ; + +assign Y1 = \Y1~output_o ; + +assign Y0 = \Y0~output_o ; + +endmodule + +module hard_block ( + + devpor, + devclrn, + devoe); + +// Design Ports Information +// ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default +// ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA + +input devpor; +input devclrn; +input devoe; + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +wire \~ALTERA_ASDO_DATA1~~padout ; +wire \~ALTERA_FLASH_nCE_nCSO~~padout ; +wire \~ALTERA_DATA0~~padout ; +wire \~ALTERA_ASDO_DATA1~~ibuf_o ; +wire \~ALTERA_FLASH_nCE_nCSO~~ibuf_o ; +wire \~ALTERA_DATA0~~ibuf_o ; + + +endmodule diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_20221104180429.sim.vwf b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_20221104180429.sim.vwf new file mode 100644 index 0000000..6e61402 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_20221104180429.sim.vwf @@ -0,0 +1,483 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("E0L") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("E1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Y0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("X1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +TRANSITION_LIST("E0L") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("E1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("X0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + } + } +} + +TRANSITION_LIST("Y0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 87.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 100.0; + } + } +} + +TRANSITION_LIST("Y1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 75.0; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 112.5; + } + } +} + +TRANSITION_LIST("Y2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 62.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 125.0; + } + } +} + +TRANSITION_LIST("Y3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 137.5; + } + } +} + +TRANSITION_LIST("X1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "E0L"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "E1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_20221114162829.sim.vwf b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_20221114162829.sim.vwf new file mode 100644 index 0000000..e0a6706 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_20221114162829.sim.vwf @@ -0,0 +1,787 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("E0L") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("E1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Y0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("E0L") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 65.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; 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+ LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 35.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + } + } +} + +TRANSITION_LIST("X1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("Y0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 75.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 45.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 85.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 145.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + } + } +} + +TRANSITION_LIST("Y1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 55.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 65.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + } + } +} + +TRANSITION_LIST("Y2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 215.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 155.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 85.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 55.0; + } + } +} + +TRANSITION_LIST("Y3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 185.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 235.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "E0L"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "E1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_20221114214232.sim.vwf b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_20221114214232.sim.vwf new file mode 100644 index 0000000..05e9dd7 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_20221114214232.sim.vwf @@ -0,0 +1,483 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("E0L") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("E1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("X1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("Y0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("Y3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("E0L") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + } + } +} + +TRANSITION_LIST("E1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("X0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("X1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("Y0") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 125.0; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 62.5; + } + } +} + +TRANSITION_LIST("Y1") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 175.0; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + } + } +} + +TRANSITION_LIST("Y2") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 75.0; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 112.5; + } + } +} + +TRANSITION_LIST("Y3") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 187.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 162.5; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "E0L"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "E1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "X1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "Y3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_0c_slow.vho b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_0c_slow.vho new file mode 100644 index 0000000..2f842ec --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_0c_slow.vho @@ -0,0 +1,328 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- VENDOR "Altera" +-- PROGRAM "Quartus Prime" +-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" + +-- DATE "11/04/2022 15:08:53" + +-- +-- Device: Altera EP4CE6E22C6 Package TQFP144 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY hard_block IS + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic + ); +END hard_block; + +-- Design Ports Information +-- ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA + + +ARCHITECTURE structure OF hard_block IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic; +SIGNAL \~ALTERA_DATA0~~padout\ : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic; + +BEGIN + +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +END structure; + + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY Dec2_4 IS + PORT ( + Y3 : OUT std_logic; + E0L : IN std_logic; + E1 : IN std_logic; + X1 : IN std_logic; + X0 : IN std_logic; + Y2 : OUT std_logic; + Y1 : OUT std_logic; + Y0 : OUT std_logic + ); +END Dec2_4; + +-- Design Ports Information +-- Y3 => Location: PIN_33, I/O Standard: 2.5 V, Current Strength: Default +-- Y2 => Location: PIN_32, I/O Standard: 2.5 V, Current Strength: Default +-- Y1 => Location: PIN_28, I/O Standard: 2.5 V, Current Strength: Default +-- Y0 => Location: PIN_34, I/O Standard: 2.5 V, Current Strength: Default +-- E1 => Location: PIN_24, I/O Standard: 2.5 V, Current Strength: Default +-- X0 => Location: PIN_25, I/O Standard: 2.5 V, Current Strength: Default +-- X1 => Location: PIN_31, I/O Standard: 2.5 V, Current Strength: Default +-- E0L => Location: PIN_30, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF Dec2_4 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_Y3 : std_logic; +SIGNAL ww_E0L : std_logic; +SIGNAL ww_E1 : std_logic; +SIGNAL ww_X1 : std_logic; +SIGNAL ww_X0 : std_logic; +SIGNAL ww_Y2 : std_logic; +SIGNAL ww_Y1 : std_logic; +SIGNAL ww_Y0 : std_logic; +SIGNAL \Y3~output_o\ : std_logic; +SIGNAL \Y2~output_o\ : std_logic; +SIGNAL \Y1~output_o\ : std_logic; +SIGNAL \Y0~output_o\ : std_logic; +SIGNAL \E1~input_o\ : std_logic; +SIGNAL \X1~input_o\ : std_logic; +SIGNAL \X0~input_o\ : std_logic; +SIGNAL \E0L~input_o\ : std_logic; +SIGNAL \inst~combout\ : std_logic; +SIGNAL \inst1~combout\ : std_logic; +SIGNAL \inst2~combout\ : std_logic; +SIGNAL \inst3~combout\ : std_logic; + +COMPONENT hard_block + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic); +END COMPONENT; + +BEGIN + +Y3 <= ww_Y3; +ww_E0L <= E0L; +ww_E1 <= E1; +ww_X1 <= X1; +ww_X0 <= X0; +Y2 <= ww_Y2; +Y1 <= ww_Y1; +Y0 <= ww_Y0; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +auto_generated_inst : hard_block +PORT MAP ( + devoe => ww_devoe, + devclrn => ww_devclrn, + devpor => ww_devpor); + +-- Location: IOOBUF_X0_Y6_N23 +\Y3~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst~combout\, + devoe => ww_devoe, + o => \Y3~output_o\); + +-- Location: IOOBUF_X0_Y6_N16 +\Y2~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1~combout\, + devoe => ww_devoe, + o => \Y2~output_o\); + +-- Location: IOOBUF_X0_Y9_N9 +\Y1~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2~combout\, + devoe => ww_devoe, + o => \Y1~output_o\); + +-- Location: IOOBUF_X0_Y5_N16 +\Y0~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3~combout\, + devoe => ww_devoe, + o => \Y0~output_o\); + +-- Location: IOIBUF_X0_Y11_N15 +\E1~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_E1, + o => \E1~input_o\); + +-- Location: IOIBUF_X0_Y7_N1 +\X1~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_X1, + o => \X1~input_o\); + +-- Location: IOIBUF_X0_Y11_N22 +\X0~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_X0, + o => \X0~input_o\); + +-- Location: IOIBUF_X0_Y8_N15 +\E0L~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_E0L, + o => \E0L~input_o\); + +-- Location: LCCOMB_X6_Y9_N8 +inst : cycloneive_lcell_comb +-- Equation(s): +-- \inst~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst~combout\); + +-- Location: LCCOMB_X6_Y9_N2 +inst1 : cycloneive_lcell_comb +-- Equation(s): +-- \inst1~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst1~combout\); + +-- Location: LCCOMB_X6_Y9_N28 +inst2 : cycloneive_lcell_comb +-- Equation(s): +-- \inst2~combout\ = (\E1~input_o\ & (\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst2~combout\); + +-- Location: LCCOMB_X6_Y9_N30 +inst3 : cycloneive_lcell_comb +-- Equation(s): +-- \inst3~combout\ = (\E1~input_o\ & (\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst3~combout\); + +ww_Y3 <= \Y3~output_o\; + +ww_Y2 <= \Y2~output_o\; + +ww_Y1 <= \Y1~output_o\; + +ww_Y0 <= \Y0~output_o\; +END structure; + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_0c_vhd_slow.sdo b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_0c_vhd_slow.sdo new file mode 100644 index 0000000..9a86ad6 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_0c_vhd_slow.sdo @@ -0,0 +1,180 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + + +// +// Device: Altera EP4CE6E22C6 Package TQFP144 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE6E22C6, +// with speed grade 6, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "Dec2_4") + (DATE "11/04/2022 15:08:53") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (941:941:941) (908:908:908)) + (IOPATH i o (2225:2225:2225) (2220:2220:2220)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (927:927:927) (894:894:894)) + (IOPATH i o (2225:2225:2225) (2220:2220:2220)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (622:622:622) (573:573:573)) + (IOPATH i o (2330:2330:2330) (2303:2303:2303)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (925:925:925) (885:885:885)) + (IOPATH i o (2225:2225:2225) (2220:2220:2220)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\E1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (581:581:581) (723:723:723)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\X1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (581:581:581) (723:723:723)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\X0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (581:581:581) (723:723:723)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\E0L\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (581:581:581) (723:723:723)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst) + (DELAY + (ABSOLUTE + (PORT dataa (791:791:791) (815:815:815)) + (PORT datab (2629:2629:2629) (2810:2810:2810)) + (PORT datac (720:720:720) (756:756:756)) + (PORT datad (2649:2649:2649) (2850:2850:2850)) + (IOPATH dataa combout (318:318:318) (307:307:307)) + (IOPATH datab combout (336:336:336) (337:337:337)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst1) + (DELAY + (ABSOLUTE + (PORT dataa (788:788:788) (814:814:814)) + (PORT datab (2629:2629:2629) (2814:2814:2814)) + (PORT datac (723:723:723) (757:757:757)) + (PORT datad (2649:2649:2649) (2853:2853:2853)) + (IOPATH dataa combout (307:307:307) (280:280:280)) + (IOPATH datab combout (325:325:325) (332:332:332)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst2) + (DELAY + (ABSOLUTE + (PORT dataa (797:797:797) (819:819:819)) + (PORT datab (2628:2628:2628) (2810:2810:2810)) + (PORT datac (719:719:719) (754:754:754)) + (PORT datad (2647:2647:2647) (2849:2849:2849)) + (IOPATH dataa combout (300:300:300) (323:323:323)) + (IOPATH datab combout (306:306:306) (324:324:324)) + (IOPATH datac combout (218:218:218) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst3) + (DELAY + (ABSOLUTE + (PORT dataa (798:798:798) (819:819:819)) + (PORT datab (2628:2628:2628) (2810:2810:2810)) + (PORT datac (719:719:719) (754:754:754)) + (PORT datad (2648:2648:2648) (2849:2849:2849)) + (IOPATH dataa combout (290:290:290) (306:306:306)) + (IOPATH datab combout (295:295:295) (300:300:300)) + (IOPATH datac combout (220:220:220) (215:215:215)) + (IOPATH datad combout (119:119:119) (106:106:106)) + ) + ) + ) +) diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_85c_slow.vho b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_85c_slow.vho new file mode 100644 index 0000000..2f842ec --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_85c_slow.vho @@ -0,0 +1,328 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- VENDOR "Altera" +-- PROGRAM "Quartus Prime" +-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" + +-- DATE "11/04/2022 15:08:53" + +-- +-- Device: Altera EP4CE6E22C6 Package TQFP144 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY hard_block IS + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic + ); +END hard_block; + +-- Design Ports Information +-- ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA + + +ARCHITECTURE structure OF hard_block IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic; +SIGNAL \~ALTERA_DATA0~~padout\ : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic; + +BEGIN + +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +END structure; + + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY Dec2_4 IS + PORT ( + Y3 : OUT std_logic; + E0L : IN std_logic; + E1 : IN std_logic; + X1 : IN std_logic; + X0 : IN std_logic; + Y2 : OUT std_logic; + Y1 : OUT std_logic; + Y0 : OUT std_logic + ); +END Dec2_4; + +-- Design Ports Information +-- Y3 => Location: PIN_33, I/O Standard: 2.5 V, Current Strength: Default +-- Y2 => Location: PIN_32, I/O Standard: 2.5 V, Current Strength: Default +-- Y1 => Location: PIN_28, I/O Standard: 2.5 V, Current Strength: Default +-- Y0 => Location: PIN_34, I/O Standard: 2.5 V, Current Strength: Default +-- E1 => Location: PIN_24, I/O Standard: 2.5 V, Current Strength: Default +-- X0 => Location: PIN_25, I/O Standard: 2.5 V, Current Strength: Default +-- X1 => Location: PIN_31, I/O Standard: 2.5 V, Current Strength: Default +-- E0L => Location: PIN_30, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF Dec2_4 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_Y3 : std_logic; +SIGNAL ww_E0L : std_logic; +SIGNAL ww_E1 : std_logic; +SIGNAL ww_X1 : std_logic; +SIGNAL ww_X0 : std_logic; +SIGNAL ww_Y2 : std_logic; +SIGNAL ww_Y1 : std_logic; +SIGNAL ww_Y0 : std_logic; +SIGNAL \Y3~output_o\ : std_logic; +SIGNAL \Y2~output_o\ : std_logic; +SIGNAL \Y1~output_o\ : std_logic; +SIGNAL \Y0~output_o\ : std_logic; +SIGNAL \E1~input_o\ : std_logic; +SIGNAL \X1~input_o\ : std_logic; +SIGNAL \X0~input_o\ : std_logic; +SIGNAL \E0L~input_o\ : std_logic; +SIGNAL \inst~combout\ : std_logic; +SIGNAL \inst1~combout\ : std_logic; +SIGNAL \inst2~combout\ : std_logic; +SIGNAL \inst3~combout\ : std_logic; + +COMPONENT hard_block + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic); +END COMPONENT; + +BEGIN + +Y3 <= ww_Y3; +ww_E0L <= E0L; +ww_E1 <= E1; +ww_X1 <= X1; +ww_X0 <= X0; +Y2 <= ww_Y2; +Y1 <= ww_Y1; +Y0 <= ww_Y0; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +auto_generated_inst : hard_block +PORT MAP ( + devoe => ww_devoe, + devclrn => ww_devclrn, + devpor => ww_devpor); + +-- Location: IOOBUF_X0_Y6_N23 +\Y3~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst~combout\, + devoe => ww_devoe, + o => \Y3~output_o\); + +-- Location: IOOBUF_X0_Y6_N16 +\Y2~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1~combout\, + devoe => ww_devoe, + o => \Y2~output_o\); + +-- Location: IOOBUF_X0_Y9_N9 +\Y1~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2~combout\, + devoe => ww_devoe, + o => \Y1~output_o\); + +-- Location: IOOBUF_X0_Y5_N16 +\Y0~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3~combout\, + devoe => ww_devoe, + o => \Y0~output_o\); + +-- Location: IOIBUF_X0_Y11_N15 +\E1~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_E1, + o => \E1~input_o\); + +-- Location: IOIBUF_X0_Y7_N1 +\X1~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_X1, + o => \X1~input_o\); + +-- Location: IOIBUF_X0_Y11_N22 +\X0~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_X0, + o => \X0~input_o\); + +-- Location: IOIBUF_X0_Y8_N15 +\E0L~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_E0L, + o => \E0L~input_o\); + +-- Location: LCCOMB_X6_Y9_N8 +inst : cycloneive_lcell_comb +-- Equation(s): +-- \inst~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst~combout\); + +-- Location: LCCOMB_X6_Y9_N2 +inst1 : cycloneive_lcell_comb +-- Equation(s): +-- \inst1~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst1~combout\); + +-- Location: LCCOMB_X6_Y9_N28 +inst2 : cycloneive_lcell_comb +-- Equation(s): +-- \inst2~combout\ = (\E1~input_o\ & (\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst2~combout\); + +-- Location: LCCOMB_X6_Y9_N30 +inst3 : cycloneive_lcell_comb +-- Equation(s): +-- \inst3~combout\ = (\E1~input_o\ & (\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst3~combout\); + +ww_Y3 <= \Y3~output_o\; + +ww_Y2 <= \Y2~output_o\; + +ww_Y1 <= \Y1~output_o\; + +ww_Y0 <= \Y0~output_o\; +END structure; + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_85c_vhd_slow.sdo b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_85c_vhd_slow.sdo new file mode 100644 index 0000000..6aae15c --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_6_1200mv_85c_vhd_slow.sdo @@ -0,0 +1,180 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + + +// +// Device: Altera EP4CE6E22C6 Package TQFP144 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE6E22C6, +// with speed grade 6, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "Dec2_4") + (DATE "11/04/2022 15:08:53") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1004:1004:1004) (1006:1006:1006)) + (IOPATH i o (2533:2533:2533) (2516:2516:2516)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (991:991:991) (1012:1012:1012)) + (IOPATH i o (2533:2533:2533) (2516:2516:2516)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (661:661:661) (653:653:653)) + (IOPATH i o (2627:2627:2627) (2603:2603:2603)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (991:991:991) (984:984:984)) + (IOPATH i o (2533:2533:2533) (2516:2516:2516)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\E1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (596:596:596) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\X1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (596:596:596) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\X0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (596:596:596) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\E0L\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (596:596:596) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (893:893:893)) + (PORT datab (3049:3049:3049) (3301:3301:3301)) + (PORT datac (803:803:803) (816:816:816)) + (PORT datad (3063:3063:3063) (3333:3333:3333)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst1) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (890:890:890)) + (PORT datab (3049:3049:3049) (3305:3305:3305)) + (PORT datac (806:806:806) (817:817:817)) + (PORT datad (3063:3063:3063) (3336:3336:3336)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst2) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (899:899:899)) + (PORT datab (3049:3049:3049) (3301:3301:3301)) + (PORT datac (801:801:801) (812:812:812)) + (PORT datad (3061:3061:3061) (3332:3332:3332)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst3) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (900:900:900)) + (PORT datab (3049:3049:3049) (3301:3301:3301)) + (PORT datac (801:801:801) (811:811:811)) + (PORT datad (3061:3061:3061) (3332:3332:3332)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) +) diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_min_1200mv_0c_fast.vho b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_min_1200mv_0c_fast.vho new file mode 100644 index 0000000..2f842ec --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_min_1200mv_0c_fast.vho @@ -0,0 +1,328 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- VENDOR "Altera" +-- PROGRAM "Quartus Prime" +-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" + +-- DATE "11/04/2022 15:08:53" + +-- +-- Device: Altera EP4CE6E22C6 Package TQFP144 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY hard_block IS + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic + ); +END hard_block; + +-- Design Ports Information +-- ~ALTERA_ASDO_DATA1~ => Location: PIN_6, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_8, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_DCLK~ => Location: PIN_12, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_DATA0~ => Location: PIN_13, I/O Standard: 2.5 V, Current Strength: Default +-- ~ALTERA_nCEO~ => Location: PIN_101, I/O Standard: 2.5 V, Current Strength: 8mA + + +ARCHITECTURE structure OF hard_block IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic; +SIGNAL \~ALTERA_DATA0~~padout\ : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic; + +BEGIN + +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +END structure; + + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY Dec2_4 IS + PORT ( + Y3 : OUT std_logic; + E0L : IN std_logic; + E1 : IN std_logic; + X1 : IN std_logic; + X0 : IN std_logic; + Y2 : OUT std_logic; + Y1 : OUT std_logic; + Y0 : OUT std_logic + ); +END Dec2_4; + +-- Design Ports Information +-- Y3 => Location: PIN_33, I/O Standard: 2.5 V, Current Strength: Default +-- Y2 => Location: PIN_32, I/O Standard: 2.5 V, Current Strength: Default +-- Y1 => Location: PIN_28, I/O Standard: 2.5 V, Current Strength: Default +-- Y0 => Location: PIN_34, I/O Standard: 2.5 V, Current Strength: Default +-- E1 => Location: PIN_24, I/O Standard: 2.5 V, Current Strength: Default +-- X0 => Location: PIN_25, I/O Standard: 2.5 V, Current Strength: Default +-- X1 => Location: PIN_31, I/O Standard: 2.5 V, Current Strength: Default +-- E0L => Location: PIN_30, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF Dec2_4 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_Y3 : std_logic; +SIGNAL ww_E0L : std_logic; +SIGNAL ww_E1 : std_logic; +SIGNAL ww_X1 : std_logic; +SIGNAL ww_X0 : std_logic; +SIGNAL ww_Y2 : std_logic; +SIGNAL ww_Y1 : std_logic; +SIGNAL ww_Y0 : std_logic; +SIGNAL \Y3~output_o\ : std_logic; +SIGNAL \Y2~output_o\ : std_logic; +SIGNAL \Y1~output_o\ : std_logic; +SIGNAL \Y0~output_o\ : std_logic; +SIGNAL \E1~input_o\ : std_logic; +SIGNAL \X1~input_o\ : std_logic; +SIGNAL \X0~input_o\ : std_logic; +SIGNAL \E0L~input_o\ : std_logic; +SIGNAL \inst~combout\ : std_logic; +SIGNAL \inst1~combout\ : std_logic; +SIGNAL \inst2~combout\ : std_logic; +SIGNAL \inst3~combout\ : std_logic; + +COMPONENT hard_block + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic); +END COMPONENT; + +BEGIN + +Y3 <= ww_Y3; +ww_E0L <= E0L; +ww_E1 <= E1; +ww_X1 <= X1; +ww_X0 <= X0; +Y2 <= ww_Y2; +Y1 <= ww_Y1; +Y0 <= ww_Y0; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +auto_generated_inst : hard_block +PORT MAP ( + devoe => ww_devoe, + devclrn => ww_devclrn, + devpor => ww_devpor); + +-- Location: IOOBUF_X0_Y6_N23 +\Y3~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst~combout\, + devoe => ww_devoe, + o => \Y3~output_o\); + +-- Location: IOOBUF_X0_Y6_N16 +\Y2~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1~combout\, + devoe => ww_devoe, + o => \Y2~output_o\); + +-- Location: IOOBUF_X0_Y9_N9 +\Y1~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst2~combout\, + devoe => ww_devoe, + o => \Y1~output_o\); + +-- Location: IOOBUF_X0_Y5_N16 +\Y0~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst3~combout\, + devoe => ww_devoe, + o => \Y0~output_o\); + +-- Location: IOIBUF_X0_Y11_N15 +\E1~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_E1, + o => \E1~input_o\); + +-- Location: IOIBUF_X0_Y7_N1 +\X1~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_X1, + o => \X1~input_o\); + +-- Location: IOIBUF_X0_Y11_N22 +\X0~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_X0, + o => \X0~input_o\); + +-- Location: IOIBUF_X0_Y8_N15 +\E0L~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_E0L, + o => \E0L~input_o\); + +-- Location: LCCOMB_X6_Y9_N8 +inst : cycloneive_lcell_comb +-- Equation(s): +-- \inst~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst~combout\); + +-- Location: LCCOMB_X6_Y9_N2 +inst1 : cycloneive_lcell_comb +-- Equation(s): +-- \inst1~combout\ = (\E1~input_o\ & (!\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst1~combout\); + +-- Location: LCCOMB_X6_Y9_N28 +inst2 : cycloneive_lcell_comb +-- Equation(s): +-- \inst2~combout\ = (\E1~input_o\ & (\X1~input_o\ & (!\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst2~combout\); + +-- Location: LCCOMB_X6_Y9_N30 +inst3 : cycloneive_lcell_comb +-- Equation(s): +-- \inst3~combout\ = (\E1~input_o\ & (\X1~input_o\ & (\X0~input_o\ & !\E0L~input_o\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \E1~input_o\, + datab => \X1~input_o\, + datac => \X0~input_o\, + datad => \E0L~input_o\, + combout => \inst3~combout\); + +ww_Y3 <= \Y3~output_o\; + +ww_Y2 <= \Y2~output_o\; + +ww_Y1 <= \Y1~output_o\; + +ww_Y0 <= \Y0~output_o\; +END structure; + + diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_min_1200mv_0c_vhd_fast.sdo b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_min_1200mv_0c_vhd_fast.sdo new file mode 100644 index 0000000..063aa5b --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_min_1200mv_0c_vhd_fast.sdo @@ -0,0 +1,180 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + + +// +// Device: Altera EP4CE6E22C6 Package TQFP144 +// + +// +// This file contains Fast Corner delays for the design using part EP4CE6E22C6, +// with speed grade M, core voltage 1.2VmV, and temperature 0 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "Dec2_4") + (DATE "11/04/2022 15:08:53") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (540:540:540) (609:609:609)) + (IOPATH i o (1565:1565:1565) (1570:1570:1570)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (537:537:537) (605:605:605)) + (IOPATH i o (1565:1565:1565) (1570:1570:1570)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (342:342:342) (377:377:377)) + (IOPATH i o (1619:1619:1619) (1644:1644:1644)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (526:526:526) (591:591:591)) + (IOPATH i o (1565:1565:1565) (1570:1570:1570)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\E1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\X1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\X0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\E0L\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (318:318:318) (698:698:698)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst) + (DELAY + (ABSOLUTE + (PORT dataa (542:542:542) (481:481:481)) + (PORT datab (1756:1756:1756) (1967:1967:1967)) + (PORT datac (500:500:500) (454:454:454)) + (PORT datad (1759:1759:1759) (1985:1985:1985)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst1) + (DELAY + (ABSOLUTE + (PORT dataa (540:540:540) (479:479:479)) + (PORT datab (1757:1757:1757) (1968:1968:1968)) + (PORT datac (501:501:501) (455:455:455)) + (PORT datad (1759:1759:1759) (1986:1986:1986)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (160:160:160) (156:156:156)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst2) + (DELAY + (ABSOLUTE + (PORT dataa (549:549:549) (486:486:486)) + (PORT datab (1755:1755:1755) (1966:1966:1966)) + (PORT datac (496:496:496) (450:450:450)) + (PORT datad (1756:1756:1756) (1982:1982:1982)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (120:120:120) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst3) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (487:487:487)) + (PORT datab (1755:1755:1755) (1966:1966:1966)) + (PORT datac (496:496:496) (450:450:450)) + (PORT datad (1756:1756:1756) (1982:1982:1982)) + (IOPATH dataa combout (170:170:170) (163:163:163)) + (IOPATH datab combout (168:168:168) (167:167:167)) + (IOPATH datac combout (119:119:119) (124:124:124)) + (IOPATH datad combout (68:68:68) (63:63:63)) + ) + ) + ) +) diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_modelsim.xrf b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_modelsim.xrf new file mode 100644 index 0000000..05d6f72 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_modelsim.xrf @@ -0,0 +1,15 @@ +vendor_name = ModelSim +source_file = 1, /home/tiagorg/repos/DecoderDemo/Dec2_4.bdf +source_file = 1, /home/tiagorg/repos/DecoderDemo/WaveformDecoderNode.vwf +source_file = 1, /home/tiagorg/repos/DecoderDemo/Waveform.vwf +source_file = 1, /home/tiagorg/repos/DecoderDemo/db/DecoderDemo.cbx.xml +design_name = hard_block +design_name = Dec2_4 +instance = comp, \Y3~output\, Y3~output, Dec2_4, 1 +instance = comp, \Y2~output\, Y2~output, Dec2_4, 1 +instance = comp, \Y1~output\, Y1~output, Dec2_4, 1 +instance = comp, \Y0~output\, Y0~output, Dec2_4, 1 +instance = comp, \E1~input\, E1~input, Dec2_4, 1 +instance = comp, \X1~input\, X1~input, Dec2_4, 1 +instance = comp, \X0~input\, X0~input, Dec2_4, 1 +instance = comp, \E0L~input\, E0L~input, Dec2_4, 1 diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_vhd.sdo b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_vhd.sdo new file mode 100644 index 0000000..6aae15c --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/DecoderDemo_vhd.sdo @@ -0,0 +1,180 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + + +// +// Device: Altera EP4CE6E22C6 Package TQFP144 +// + +// +// This file contains Slow Corner delays for the design using part EP4CE6E22C6, +// with speed grade 6, core voltage 1.2VmV, and temperature 85 Celsius +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "Dec2_4") + (DATE "11/04/2022 15:08:53") + (VENDOR "Altera") + (PROGRAM "Quartus Prime") + (VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y3\~output\\) + (DELAY + (ABSOLUTE + (PORT i (1004:1004:1004) (1006:1006:1006)) + (IOPATH i o (2533:2533:2533) (2516:2516:2516)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y2\~output\\) + (DELAY + (ABSOLUTE + (PORT i (991:991:991) (1012:1012:1012)) + (IOPATH i o (2533:2533:2533) (2516:2516:2516)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y1\~output\\) + (DELAY + (ABSOLUTE + (PORT i (661:661:661) (653:653:653)) + (IOPATH i o (2627:2627:2627) (2603:2603:2603)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_obuf") + (INSTANCE \\Y0\~output\\) + (DELAY + (ABSOLUTE + (PORT i (991:991:991) (984:984:984)) + (IOPATH i o (2533:2533:2533) (2516:2516:2516)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\E1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (596:596:596) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\X1\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (596:596:596) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\X0\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (596:596:596) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_io_ibuf") + (INSTANCE \\E0L\~input\\) + (DELAY + (ABSOLUTE + (IOPATH i o (596:596:596) (761:761:761)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst) + (DELAY + (ABSOLUTE + (PORT dataa (882:882:882) (893:893:893)) + (PORT datab (3049:3049:3049) (3301:3301:3301)) + (PORT datac (803:803:803) (816:816:816)) + (PORT datad (3063:3063:3063) (3333:3333:3333)) + (IOPATH dataa combout (354:354:354) (349:349:349)) + (IOPATH datab combout (381:381:381) (380:380:380)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst1) + (DELAY + (ABSOLUTE + (PORT dataa (879:879:879) (890:890:890)) + (PORT datab (3049:3049:3049) (3305:3305:3305)) + (PORT datac (806:806:806) (817:817:817)) + (PORT datad (3063:3063:3063) (3336:3336:3336)) + (IOPATH dataa combout (341:341:341) (319:319:319)) + (IOPATH datab combout (365:365:365) (373:373:373)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst2) + (DELAY + (ABSOLUTE + (PORT dataa (889:889:889) (899:899:899)) + (PORT datab (3049:3049:3049) (3301:3301:3301)) + (PORT datac (801:801:801) (812:812:812)) + (PORT datad (3061:3061:3061) (3332:3332:3332)) + (IOPATH dataa combout (339:339:339) (367:367:367)) + (IOPATH datab combout (344:344:344) (369:369:369)) + (IOPATH datac combout (241:241:241) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneive_lcell_comb") + (INSTANCE inst3) + (DELAY + (ABSOLUTE + (PORT dataa (890:890:890) (900:900:900)) + (PORT datab (3049:3049:3049) (3301:3301:3301)) + (PORT datac (801:801:801) (811:811:811)) + (PORT datad (3061:3061:3061) (3332:3332:3332)) + (IOPATH dataa combout (327:327:327) (347:347:347)) + (IOPATH datab combout (331:331:331) (342:342:342)) + (IOPATH datac combout (243:243:243) (241:241:241)) + (IOPATH datad combout (130:130:130) (120:120:120)) + ) + ) + ) +) diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform.vwf.vht b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform.vwf.vht new file mode 100644 index 0000000..a6d9e5a --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform.vwf.vht @@ -0,0 +1,870 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- ***************************************************************************** +-- This file contains a Vhdl test bench with test vectors .The test vectors +-- are exported from a vector file in the Quartus Waveform Editor and apply to +-- the top level entity of the current Quartus project .The user can use this +-- testbench to simulate his design using a third-party simulation tool . +-- ***************************************************************************** +-- Generated on "11/14/2022 16:28:27" + +-- Vhdl Test Bench(with test vectors) for design : Dec2_4 +-- +-- Simulation tool : 3rd Party +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY Dec2_4_vhd_vec_tst IS +END Dec2_4_vhd_vec_tst; +ARCHITECTURE Dec2_4_arch OF Dec2_4_vhd_vec_tst IS +-- constants +-- signals +SIGNAL E0L : STD_LOGIC; +SIGNAL E1 : STD_LOGIC; +SIGNAL X0 : STD_LOGIC; +SIGNAL X1 : STD_LOGIC; +SIGNAL Y0 : STD_LOGIC; +SIGNAL Y1 : STD_LOGIC; +SIGNAL Y2 : STD_LOGIC; +SIGNAL Y3 : STD_LOGIC; +COMPONENT Dec2_4 + PORT ( + E0L : IN STD_LOGIC; + E1 : IN STD_LOGIC; + X0 : IN STD_LOGIC; + X1 : IN STD_LOGIC; + Y0 : OUT STD_LOGIC; + Y1 : OUT STD_LOGIC; + Y2 : OUT STD_LOGIC; + Y3 : OUT STD_LOGIC + ); +END COMPONENT; +BEGIN + i1 : Dec2_4 + PORT MAP ( +-- list connections between master ports and signals + E0L => E0L, + E1 => E1, + X0 => X0, + X1 => X1, + Y0 => Y0, + Y1 => Y1, + Y2 => Y2, + Y3 => Y3 + ); + +-- E0L +t_prcs_E0L: PROCESS +BEGIN + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 65000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 20000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 15000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 30000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 15000 ps; + E0L <= '0'; + WAIT FOR 20000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 15000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 15000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 20000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 15000 ps; + E0L <= '0'; + WAIT FOR 30000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 35000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 20000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 30000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 20000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 15000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 10000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; + WAIT FOR 10000 ps; + E0L <= '0'; + WAIT FOR 45000 ps; + E0L <= '1'; + WAIT FOR 5000 ps; + E0L <= '0'; + WAIT FOR 5000 ps; + E0L <= '1'; +WAIT; +END PROCESS t_prcs_E0L; + +-- E1 +t_prcs_E1: PROCESS +BEGIN + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 15000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 20000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 15000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 20000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 15000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 15000 ps; + E1 <= '0'; + WAIT FOR 15000 ps; + E1 <= '1'; + WAIT FOR 30000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 15000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 30000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 25000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 15000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 50000 ps; + E1 <= '0'; + WAIT FOR 15000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 20000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 15000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 15000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 15000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 20000 ps; + E1 <= '0'; + WAIT FOR 25000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 10000 ps; + E1 <= '1'; + WAIT FOR 25000 ps; + E1 <= '0'; + WAIT FOR 15000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 25000 ps; + E1 <= '1'; + WAIT FOR 10000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 15000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 15000 ps; + E1 <= '0'; + WAIT FOR 5000 ps; + E1 <= '1'; + WAIT FOR 20000 ps; + E1 <= '0'; + WAIT FOR 15000 ps; + E1 <= '1'; + WAIT FOR 5000 ps; + E1 <= '0'; +WAIT; +END PROCESS t_prcs_E1; + +-- X0 +t_prcs_X0: PROCESS +BEGIN + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 10000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 10000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 15000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 15000 ps; + X0 <= '1'; + WAIT FOR 20000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 35000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 40000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 15000 ps; + X0 <= '1'; + WAIT FOR 15000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 15000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 10000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 15000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 15000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 20000 ps; + X0 <= '1'; + WAIT FOR 15000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 35000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 20000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 10000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 10000 ps; + X0 <= '0'; + WAIT FOR 20000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 15000 ps; + X0 <= '1'; + WAIT FOR 15000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 20000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 15000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 10000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 15000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 10000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 40000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 35000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 30000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 10000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 10000 ps; + X0 <= '0'; + WAIT FOR 5000 ps; + X0 <= '1'; + WAIT FOR 5000 ps; + X0 <= '0'; + WAIT FOR 10000 ps; + X0 <= '1'; + WAIT FOR 10000 ps; + X0 <= '0'; +WAIT; +END PROCESS t_prcs_X0; + +-- X1 +t_prcs_X1: PROCESS +BEGIN + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 15000 ps; + X1 <= '0'; + WAIT FOR 25000 ps; + X1 <= '1'; + WAIT FOR 10000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 10000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 15000 ps; + X1 <= '1'; + WAIT FOR 10000 ps; + X1 <= '0'; + WAIT FOR 20000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 20000 ps; + X1 <= '1'; + WAIT FOR 20000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 20000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 10000 ps; + X1 <= '0'; + WAIT FOR 20000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 20000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 10000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 20000 ps; + X1 <= '1'; + WAIT FOR 15000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 10000 ps; + X1 <= '0'; + WAIT FOR 20000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 10000 ps; + X1 <= '0'; + WAIT FOR 25000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 25000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 15000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 15000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 20000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 10000 ps; + X1 <= '0'; + WAIT FOR 15000 ps; + X1 <= '1'; + WAIT FOR 20000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 25000 ps; + X1 <= '1'; + WAIT FOR 10000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 15000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 25000 ps; + X1 <= '0'; + WAIT FOR 15000 ps; + X1 <= '1'; + WAIT FOR 15000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 10000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 25000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 20000 ps; + X1 <= '0'; + WAIT FOR 10000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 20000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; + WAIT FOR 5000 ps; + X1 <= '0'; + WAIT FOR 5000 ps; + X1 <= '1'; +WAIT; +END PROCESS t_prcs_X1; +END Dec2_4_arch; diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform.vwf.vt b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform.vwf.vt new file mode 100644 index 0000000..eed1d2f --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform.vwf.vt @@ -0,0 +1,470 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "11/14/2022 16:20:00" + +// Verilog Test Bench (with test vectors) for design : Dec2_4 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module Dec2_4_vlg_vec_tst(); +// constants +// general purpose registers +reg E0L; +reg E1; +reg X0; +reg X1; +// wires +wire Y0; +wire Y1; +wire Y2; +wire Y3; + +// assign statements (if any) +Dec2_4 i1 ( +// port map - connection between master ports and signals/registers + .E0L(E0L), + .E1(E1), + .X0(X0), + .X1(X1), + .Y0(Y0), + .Y1(Y1), + .Y2(Y2), + .Y3(Y3) +); +initial +begin +#1000000 $finish; +end + +// E0L +initial +begin + E0L = 1'b1; + E0L = #5000 1'b0; + E0L = #65000 1'b1; + E0L = #10000 1'b0; + E0L = #10000 1'b1; + E0L = #20000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #15000 1'b1; + E0L = #5000 1'b0; + E0L = #10000 1'b1; + E0L = #30000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #10000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #10000 1'b1; + E0L = #15000 1'b0; + E0L = #20000 1'b1; + E0L = #10000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #15000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #5000 1'b1; + E0L = #15000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #20000 1'b1; + E0L = #10000 1'b0; + E0L = #10000 1'b1; + E0L = #15000 1'b0; + E0L = #30000 1'b1; + E0L = #5000 1'b0; + E0L = #10000 1'b1; + E0L = #10000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #35000 1'b1; + E0L = #5000 1'b0; + E0L = #10000 1'b1; + E0L = #20000 1'b0; + E0L = #10000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #30000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #10000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #20000 1'b1; + E0L = #5000 1'b0; + E0L = #10000 1'b1; + E0L = #5000 1'b0; + E0L = #10000 1'b1; + E0L = #10000 1'b0; + E0L = #10000 1'b1; + E0L = #10000 1'b0; + E0L = #10000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; + E0L = #5000 1'b0; + E0L = #15000 1'b1; + E0L = #10000 1'b0; + E0L = #10000 1'b1; + E0L = #10000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #5000 1'b1; + E0L = #10000 1'b0; + E0L = #45000 1'b1; + E0L = #5000 1'b0; + E0L = #5000 1'b1; +end + +// E1 +initial +begin + E1 = 1'b1; + E1 = #5000 1'b0; + E1 = #10000 1'b1; + E1 = #10000 1'b0; + E1 = #10000 1'b1; + E1 = #5000 1'b0; + E1 = #5000 1'b1; + E1 = #15000 1'b0; + E1 = #10000 1'b1; + E1 = #20000 1'b0; + E1 = #5000 1'b1; + E1 = #10000 1'b0; + E1 = #10000 1'b1; + E1 = #10000 1'b0; + E1 = #15000 1'b1; + E1 = #10000 1'b0; + E1 = #10000 1'b1; + E1 = #5000 1'b0; + E1 = #5000 1'b1; + E1 = #20000 1'b0; + E1 = #10000 1'b1; + E1 = #15000 1'b0; + E1 = #5000 1'b1; + E1 = #5000 1'b0; + E1 = #10000 1'b1; + E1 = #15000 1'b0; + E1 = #15000 1'b1; + E1 = #30000 1'b0; + E1 = #5000 1'b1; + E1 = #10000 1'b0; + E1 = #10000 1'b1; + E1 = #5000 1'b0; + E1 = #5000 1'b1; + E1 = #5000 1'b0; + E1 = #5000 1'b1; + E1 = #5000 1'b0; + E1 = #5000 1'b1; + E1 = #5000 1'b0; + E1 = #5000 1'b1; + E1 = #10000 1'b0; + E1 = #5000 1'b1; + E1 = #10000 1'b0; + E1 = #15000 1'b1; + E1 = #10000 1'b0; + E1 = #5000 1'b1; + E1 = #5000 1'b0; + E1 = #5000 1'b1; + E1 = #5000 1'b0; + E1 = #10000 1'b1; + E1 = #5000 1'b0; + E1 = #30000 1'b1; + E1 = #5000 1'b0; + E1 = #25000 1'b1; + E1 = #5000 1'b0; + E1 = #5000 1'b1; + E1 = #5000 1'b0; + E1 = #15000 1'b1; + E1 = #10000 1'b0; + E1 = #10000 1'b1; + E1 = #50000 1'b0; + E1 = #15000 1'b1; + E1 = #10000 1'b0; + E1 = #20000 1'b1; + E1 = #10000 1'b0; + E1 = #15000 1'b1; + E1 = #10000 1'b0; + E1 = #15000 1'b1; + E1 = #10000 1'b0; + E1 = #5000 1'b1; + E1 = #15000 1'b0; + E1 = #5000 1'b1; + E1 = #5000 1'b0; + E1 = #5000 1'b1; + E1 = #20000 1'b0; + E1 = #25000 1'b1; + E1 = #10000 1'b0; + E1 = #5000 1'b1; + E1 = #10000 1'b0; + E1 = #10000 1'b1; + E1 = #25000 1'b0; + E1 = #15000 1'b1; + E1 = #10000 1'b0; + E1 = #25000 1'b1; + E1 = #10000 1'b0; + E1 = #5000 1'b1; + E1 = #15000 1'b0; + E1 = #5000 1'b1; + E1 = #15000 1'b0; + E1 = #5000 1'b1; + E1 = #20000 1'b0; + E1 = #15000 1'b1; + E1 = #5000 1'b0; +end + +// X0 +initial +begin + X0 = 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #10000 1'b0; + X0 = #5000 1'b1; + X0 = #10000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #15000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #15000 1'b1; + X0 = #20000 1'b0; + X0 = #10000 1'b1; + X0 = #5000 1'b0; + X0 = #35000 1'b1; + X0 = #5000 1'b0; + X0 = #40000 1'b1; + X0 = #5000 1'b0; + X0 = #15000 1'b1; + X0 = #15000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #10000 1'b1; + X0 = #15000 1'b0; + X0 = #10000 1'b1; + X0 = #5000 1'b0; + X0 = #10000 1'b1; + X0 = #10000 1'b0; + X0 = #5000 1'b1; + X0 = #15000 1'b0; + X0 = #5000 1'b1; + X0 = #15000 1'b0; + X0 = #10000 1'b1; + X0 = #5000 1'b0; + X0 = #20000 1'b1; + X0 = #15000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #35000 1'b1; + X0 = #5000 1'b0; + X0 = #20000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #10000 1'b0; + X0 = #10000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #10000 1'b0; + X0 = #20000 1'b1; + X0 = #5000 1'b0; + X0 = #15000 1'b1; + X0 = #15000 1'b0; + X0 = #10000 1'b1; + X0 = #20000 1'b0; + X0 = #5000 1'b1; + X0 = #15000 1'b0; + X0 = #5000 1'b1; + X0 = #10000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #10000 1'b1; + X0 = #5000 1'b0; + X0 = #10000 1'b1; + X0 = #5000 1'b0; + X0 = #10000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #15000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #10000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #5000 1'b1; + X0 = #40000 1'b0; + X0 = #5000 1'b1; + X0 = #35000 1'b0; + X0 = #10000 1'b1; + X0 = #30000 1'b0; + X0 = #5000 1'b1; + X0 = #10000 1'b0; + X0 = #10000 1'b1; + X0 = #10000 1'b0; + X0 = #5000 1'b1; + X0 = #5000 1'b0; + X0 = #10000 1'b1; + X0 = #10000 1'b0; +end + +// X1 +initial +begin + X1 = 1'b0; + X1 = #10000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #10000 1'b1; + X1 = #15000 1'b0; + X1 = #25000 1'b1; + X1 = #10000 1'b0; + X1 = #10000 1'b1; + X1 = #10000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #15000 1'b1; + X1 = #10000 1'b0; + X1 = #20000 1'b1; + X1 = #5000 1'b0; + X1 = #20000 1'b1; + X1 = #20000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #20000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; + X1 = #10000 1'b0; + X1 = #20000 1'b1; + X1 = #5000 1'b0; + X1 = #10000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; + X1 = #20000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; + X1 = #10000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #20000 1'b1; + X1 = #15000 1'b0; + X1 = #5000 1'b1; + X1 = #10000 1'b0; + X1 = #20000 1'b1; + X1 = #5000 1'b0; + X1 = #10000 1'b1; + X1 = #5000 1'b0; + X1 = #10000 1'b1; + X1 = #10000 1'b0; + X1 = #25000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #10000 1'b1; + X1 = #25000 1'b0; + X1 = #5000 1'b1; + X1 = #15000 1'b0; + X1 = #5000 1'b1; + X1 = #15000 1'b0; + X1 = #10000 1'b1; + X1 = #5000 1'b0; + X1 = #20000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; + X1 = #10000 1'b0; + X1 = #15000 1'b1; + X1 = #20000 1'b0; + X1 = #10000 1'b1; + X1 = #5000 1'b0; + X1 = #25000 1'b1; + X1 = #10000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #10000 1'b1; + X1 = #5000 1'b0; + X1 = #15000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; + X1 = #25000 1'b0; + X1 = #15000 1'b1; + X1 = #15000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #10000 1'b1; + X1 = #10000 1'b0; + X1 = #10000 1'b1; + X1 = #25000 1'b0; + X1 = #5000 1'b1; + X1 = #20000 1'b0; + X1 = #10000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; + X1 = #20000 1'b0; + X1 = #5000 1'b1; + X1 = #5000 1'b0; + X1 = #5000 1'b1; +end +endmodule + diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform1.vwf.vht b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform1.vwf.vht new file mode 100644 index 0000000..0d2b019 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform1.vwf.vht @@ -0,0 +1,118 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- ***************************************************************************** +-- This file contains a Vhdl test bench with test vectors .The test vectors +-- are exported from a vector file in the Quartus Waveform Editor and apply to +-- the top level entity of the current Quartus project .The user can use this +-- testbench to simulate his design using a third-party simulation tool . +-- ***************************************************************************** +-- Generated on "11/14/2022 21:42:30" + +-- Vhdl Test Bench(with test vectors) for design : Dec2_4 +-- +-- Simulation tool : 3rd Party +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY Dec2_4_vhd_vec_tst IS +END Dec2_4_vhd_vec_tst; +ARCHITECTURE Dec2_4_arch OF Dec2_4_vhd_vec_tst IS +-- constants +-- signals +SIGNAL E0L : STD_LOGIC; +SIGNAL E1 : STD_LOGIC; +SIGNAL X0 : STD_LOGIC; +SIGNAL X1 : STD_LOGIC; +SIGNAL Y0 : STD_LOGIC; +SIGNAL Y1 : STD_LOGIC; +SIGNAL Y2 : STD_LOGIC; +SIGNAL Y3 : STD_LOGIC; +COMPONENT Dec2_4 + PORT ( + E0L : IN STD_LOGIC; + E1 : IN STD_LOGIC; + X0 : IN STD_LOGIC; + X1 : IN STD_LOGIC; + Y0 : OUT STD_LOGIC; + Y1 : OUT STD_LOGIC; + Y2 : OUT STD_LOGIC; + Y3 : OUT STD_LOGIC + ); +END COMPONENT; +BEGIN + i1 : Dec2_4 + PORT MAP ( +-- list connections between master ports and signals + E0L => E0L, + E1 => E1, + X0 => X0, + X1 => X1, + Y0 => Y0, + Y1 => Y1, + Y2 => Y2, + Y3 => Y3 + ); + +-- E0L +t_prcs_E0L: PROCESS +BEGIN +LOOP + E0L <= '0'; + WAIT FOR 12500 ps; + E0L <= '1'; + WAIT FOR 12500 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_E0L; + +-- E1 +t_prcs_E1: PROCESS +BEGIN +LOOP + E1 <= '0'; + WAIT FOR 25000 ps; + E1 <= '1'; + WAIT FOR 25000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_E1; + +-- X0 +t_prcs_X0: PROCESS +BEGIN +LOOP + X0 <= '0'; + WAIT FOR 50000 ps; + X0 <= '1'; + WAIT FOR 50000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_X0; + +-- X1 +t_prcs_X1: PROCESS +BEGIN +LOOP + X1 <= '0'; + WAIT FOR 100000 ps; + X1 <= '1'; + WAIT FOR 100000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_X1; +END Dec2_4_arch; diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform1.vwf.vt b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform1.vwf.vt new file mode 100644 index 0000000..b12b1c3 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/Waveform1.vwf.vt @@ -0,0 +1,92 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "11/14/2022 21:42:10" + +// Verilog Test Bench (with test vectors) for design : Dec2_4 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module Dec2_4_vlg_vec_tst(); +// constants +// general purpose registers +reg E0L; +reg E1; +reg X0; +reg X1; +// wires +wire Y0; +wire Y1; +wire Y2; +wire Y3; + +// assign statements (if any) +Dec2_4 i1 ( +// port map - connection between master ports and signals/registers + .E0L(E0L), + .E1(E1), + .X0(X0), + .X1(X1), + .Y0(Y0), + .Y1(Y1), + .Y2(Y2), + .Y3(Y3) +); +initial +begin +#1000000 $finish; +end + +// E0L +always +begin + E0L = 1'b0; + E0L = #12500 1'b1; + #12500; +end + +// E1 +always +begin + E1 = 1'b0; + E1 = #25000 1'b1; + #25000; +end + +// X0 +always +begin + X0 = 1'b0; + X0 = #50000 1'b1; + #50000; +end + +// X1 +always +begin + X1 = 1'b0; + X1 = #100000 1'b1; + #100000; +end +endmodule + diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/WaveformDecoderNode.vwf.vht b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/WaveformDecoderNode.vwf.vht new file mode 100644 index 0000000..eaa536e --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/WaveformDecoderNode.vwf.vht @@ -0,0 +1,118 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- ***************************************************************************** +-- This file contains a Vhdl test bench with test vectors .The test vectors +-- are exported from a vector file in the Quartus Waveform Editor and apply to +-- the top level entity of the current Quartus project .The user can use this +-- testbench to simulate his design using a third-party simulation tool . +-- ***************************************************************************** +-- Generated on "11/04/2022 18:04:28" + +-- Vhdl Test Bench(with test vectors) for design : Dec2_4 +-- +-- Simulation tool : 3rd Party +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY Dec2_4_vhd_vec_tst IS +END Dec2_4_vhd_vec_tst; +ARCHITECTURE Dec2_4_arch OF Dec2_4_vhd_vec_tst IS +-- constants +-- signals +SIGNAL E0L : STD_LOGIC; +SIGNAL E1 : STD_LOGIC; +SIGNAL X0 : STD_LOGIC; +SIGNAL X1 : STD_LOGIC; +SIGNAL Y0 : STD_LOGIC; +SIGNAL Y1 : STD_LOGIC; +SIGNAL Y2 : STD_LOGIC; +SIGNAL Y3 : STD_LOGIC; +COMPONENT Dec2_4 + PORT ( + E0L : IN STD_LOGIC; + E1 : IN STD_LOGIC; + X0 : IN STD_LOGIC; + X1 : IN STD_LOGIC; + Y0 : OUT STD_LOGIC; + Y1 : OUT STD_LOGIC; + Y2 : OUT STD_LOGIC; + Y3 : OUT STD_LOGIC + ); +END COMPONENT; +BEGIN + i1 : Dec2_4 + PORT MAP ( +-- list connections between master ports and signals + E0L => E0L, + E1 => E1, + X0 => X0, + X1 => X1, + Y0 => Y0, + Y1 => Y1, + Y2 => Y2, + Y3 => Y3 + ); + +-- E0L +t_prcs_E0L: PROCESS +BEGIN +LOOP + E0L <= '0'; + WAIT FOR 100000 ps; + E0L <= '1'; + WAIT FOR 100000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_E0L; + +-- E1 +t_prcs_E1: PROCESS +BEGIN +LOOP + E1 <= '0'; + WAIT FOR 50000 ps; + E1 <= '1'; + WAIT FOR 50000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_E1; + +-- X1 +t_prcs_X1: PROCESS +BEGIN +LOOP + X1 <= '0'; + WAIT FOR 25000 ps; + X1 <= '1'; + WAIT FOR 25000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_X1; + +-- X0 +t_prcs_X0: PROCESS +BEGIN +LOOP + X0 <= '0'; + WAIT FOR 12500 ps; + X0 <= '1'; + WAIT FOR 12500 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_X0; +END Dec2_4_arch; diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/WaveformDecoderNode.vwf.vt b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/WaveformDecoderNode.vwf.vt new file mode 100644 index 0000000..2977ed4 --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/WaveformDecoderNode.vwf.vt @@ -0,0 +1,92 @@ +// Copyright (C) 2020 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions +// and other software and tools, and any partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License +// Subscription Agreement, the Intel Quartus Prime License Agreement, +// the Intel FPGA IP License Agreement, or other applicable license +// agreement, including, without limitation, that your use is for +// the sole purpose of programming logic devices manufactured by +// Intel and sold by Intel or its authorized distributors. Please +// refer to the applicable agreement for further details, at +// https://fpgasoftware.intel.com/eula. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "11/04/2022 15:15:39" + +// Verilog Test Bench (with test vectors) for design : Dec2_4 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module Dec2_4_vlg_vec_tst(); +// constants +// general purpose registers +reg E0L; +reg E1; +reg X0; +reg X1; +// wires +wire Y0; +wire Y1; +wire Y2; +wire Y3; + +// assign statements (if any) +Dec2_4 i1 ( +// port map - connection between master ports and signals/registers + .E0L(E0L), + .E1(E1), + .X0(X0), + .X1(X1), + .Y0(Y0), + .Y1(Y1), + .Y2(Y2), + .Y3(Y3) +); +initial +begin +#1000000 $finish; +end + +// E0L +always +begin + E0L = 1'b0; + E0L = #100000 1'b1; + #100000; +end + +// E1 +always +begin + E1 = 1'b0; + E1 = #50000 1'b1; + #50000; +end + +// X1 +always +begin + X1 = 1'b0; + X1 = #25000 1'b1; + #25000; +end + +// X0 +always +begin + X0 = 1'b0; + X0 = #12500 1'b1; + #12500; +end +endmodule + diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/transcript b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/transcript new file mode 100644 index 0000000..226731f --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/transcript @@ -0,0 +1,47 @@ +# do DecoderDemo.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 21:42:31 on Nov 14,2022 +# vcom -work work DecoderDemo.vho +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package VITAL_Timing +# -- Loading package VITAL_Primitives +# -- Loading package cycloneive_atom_pack +# -- Loading package cycloneive_components +# -- Compiling entity hard_block +# -- Compiling architecture structure of hard_block +# -- Compiling entity Dec2_4 +# -- Compiling architecture structure of Dec2_4 +# End time: 21:42:31 on Nov 14,2022, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 21:42:31 on Nov 14,2022 +# vcom -work work Waveform1.vwf.vht +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling entity Dec2_4_vhd_vec_tst +# -- Compiling architecture Dec2_4_arch of Dec2_4_vhd_vec_tst +# End time: 21:42:31 on Nov 14,2022, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst +# Start time: 21:42:31 on Nov 14,2022 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading work.dec2_4_vhd_vec_tst(dec2_4_arch) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading cycloneive.cycloneive_atom_pack(body) +# Loading cycloneive.cycloneive_components +# Loading work.dec2_4(structure) +# Loading work.hard_block(structure) +# Loading ieee.std_logic_arith(body) +# Loading cycloneive.cycloneive_io_obuf(arch) +# Loading cycloneive.cycloneive_io_ibuf(arch) +# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb) +# after#33 +# End time: 21:42:31 on Nov 14,2022, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 diff --git a/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/vwf_sim_transcript b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/vwf_sim_transcript new file mode 100644 index 0000000..3a3fbbc --- /dev/null +++ b/1ano/isd/quartus-projects/DecoderDemo/simulation/qsim/vwf_sim_transcript @@ -0,0 +1,76 @@ +Determining the location of the ModelSim executable... + +Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/ + +To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options +Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. + +**** Generating the ModelSim Testbench **** + +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source="/home/tiagorg/repos/DecoderDemo/Waveform1.vwf" --testbench_file="/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform1.vwf.vht" + +Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Mon Nov 14 21:42:30 2022Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off DecoderDemo -c DecoderDemo --vector_source=/home/tiagorg/repos/DecoderDemo/Waveform1.vwf --testbench_file=/home/tiagorg/repos/DecoderDemo/simulation/qsim/Waveform1.vwf.vhtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Completed successfully. + +**** Generating the functional simulation netlist **** + +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/DecoderDemo/simulation/qsim/" DecoderDemo -c DecoderDemo + +Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Mon Nov 14 21:42:30 2022Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/DecoderDemo/simulation/qsim/ DecoderDemo -c DecoderDemoWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file DecoderDemo.vho in folder "/home/tiagorg/repos/DecoderDemo/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 603 megabytes Info: Processing ended: Mon Nov 14 21:42:31 2022 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 +Completed successfully. + +**** Generating the ModelSim .do script **** + +/home/tiagorg/repos/DecoderDemo/simulation/qsim/DecoderDemo.do generated. + +Completed successfully. + +**** Running the ModelSim simulation **** + +/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do DecoderDemo.do + +Reading pref.tcl +# 2020.1 +# do DecoderDemo.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 21:42:31 on Nov 14,2022# vcom -work work DecoderDemo.vho +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package VITAL_Timing +# -- Loading package VITAL_Primitives +# -- Loading package cycloneive_atom_pack# -- Loading package cycloneive_components +# -- Compiling entity hard_block +# -- Compiling architecture structure of hard_block +# -- Compiling entity Dec2_4 +# -- Compiling architecture structure of Dec2_4 +# End time: 21:42:31 on Nov 14,2022, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 21:42:31 on Nov 14,2022# vcom -work work Waveform1.vwf.vht +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164# -- Compiling entity Dec2_4_vhd_vec_tst# -- Compiling architecture Dec2_4_arch of Dec2_4_vhd_vec_tst +# End time: 21:42:31 on Nov 14,2022, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Dec2_4_vhd_vec_tst # Start time: 21:42:31 on Nov 14,2022# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.dec2_4_vhd_vec_tst(dec2_4_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.dec2_4(structure)# Loading work.hard_block(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb) +# after#33 +# End time: 21:42:31 on Nov 14,2022, Elapsed time: 0:00:00# Errors: 0, Warnings: 0 +Completed successfully. + +**** Converting ModelSim VCD to vector waveform **** + +Reading /home/tiagorg/repos/DecoderDemo/Waveform1.vwf... + +Reading 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