Merge pull request #51 from TiagoRG/dev-tiagorg

[LSD] material added
[LSD] README update
[LSD] pratica05 part3 added

1ano/2semestre/lsd/README.md

@@ -3,10 +3,15 @@
 
 ---
 ## Índice
-| Aula nº                                                                             | Tópicos             |
+| Aula nº                                                                                | Tópicos                                                                                                                 |
-|-------------------------------------------------------------------------------------|---------------------|
+|----------------------------------------------------------------------------------------|-------------------------------------------------------------------------------------------------------------------------|
-| [01](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica01) | Introdução às FPGAs |
+| [01](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica01) | Introdução às FPGAs                                                                                                     |
-| [02](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica02) | Modelação em VHDL, simulação e implementação de componentes combinatórios |
+| [02](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica02) | Modelação em VHDL, simulação e implementação de componentes combinatórios                                               |
-| [03](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica03) | Modelação em VHDL e implementação de circuitos aritméticos               |
+| [03](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica03) | Modelação em VHDL e implementação de circuitos aritméticos                                                              |
+| [04](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica04) | Modelação em VHDL, simulação e implementação de circuitos sequenciais elementares                                       |
+| [05](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica05) | Parametrização de componentes                                                                                           |
+| [06](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica06) | Modelação em VHDL e implementação de registos e módulos combinatórios de deslocamento                                   |
+| [07](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica07) | Construção e utilização de testbenches em VHDL<br>Simulação comportamental e temporal<br>Depuração de circuitos em FPGA |
+| [10](https://github.com/TiagoRG/uaveiro-leci/tree/master/1ano/2semestre/lsd/pratica10) | Modelação em VHDL de Memórias ROM e RAM de um Porto e Multi-porto                                                       |
 ---
 *Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)

1ano/2semestre/lsd/pratica01/README.md

@@ -3,7 +3,7 @@
 ### Tópico principal da aula: Introdução às FPGAs
 
 * [Slides](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/slides/LSD_2022-23_AulaTP01.pdf)
-* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica01/LSD_2022-23_TrabPrat01-2.pdf)
+* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica01/LSD_2022-23_TrabPrat01.pdf)
 
 ---
 *Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)

1ano/2semestre/lsd/pratica03/README.md

@@ -3,7 +3,7 @@
 ### Tópico principal da aula: Modelação em VHDL e implementação de circuitos aritméticos
 
 * [Slides](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/slides/LSD_2022-23_AulaTP03.pdf)
-* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica03/LSD_2022-23_TrabPrat03-1.pdf)
+* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica03/LSD_2022-23_TrabPrat03.pdf)
 
 ---
 *Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)

1ano/2semestre/lsd/pratica04/README.md

@@ -0,0 +1,9 @@
+# Laboratórios de Sistemas Digitais
+## Trabalho prático 04
+### Tópico principal da aula: Modelação em VHDL, simulação e implementação de circuitos sequenciais elementares
+
+* [Slides](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/slides/LSD_2022-23_AulaTP04.pdf)
+* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica03/LSD_2022-23_TrabPrat04.pdf)
+
+---
+*Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)

1ano/2semestre/lsd/pratica05/README.md

@@ -0,0 +1,9 @@
+# Laboratórios de Sistemas Digitais
+## Trabalho prático 05
+### Tópico principal da aula: Parametrização de componentes
+
+* [Slides](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/slides/LSD_2022-23_AulaTP05.pdf)
+* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica03/LSD_2022-23_TrabPrat05.pdf)
+
+---
+*Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)

1ano/2semestre/lsd/pratica05/TimerN_Demo/FreqDivider.bsf

@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 160 96)
+	(text "FreqDivider" (rect 5 0 52 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clkIn" (rect 0 0 17 12)(font "Arial" ))
+		(text "clkIn" (rect 21 27 38 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "clkOut" (rect 0 0 24 12)(font "Arial" ))
+		(text "clkOut" (rect 99 27 123 39)(font "Arial" ))
+		(line (pt 144 32)(pt 128 32)(line_width 1))
+	)
+	(parameter
+		"divFactor"
+		"10"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(rectangle (rect 16 16 128 64)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 160 -64 260 16))
+)

1ano/2semestre/lsd/pratica05/TimerN_Demo/FreqDivider.vhd

@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity FreqDivider is
+	generic(divFactor : positive := 10);
+	port
+	(
+		clkIn  : in  std_logic;
+		clkOut : out std_logic
+	);
+end FreqDivider;
+
+architecture Behavioral of FreqDivider is
+	subtype TCounter is natural range 0 to divFactor - 1;
+	signal s_divCounter : TCounter := 0;
+begin
+    assert(divFactor >= 2);
+	process(clkIn)
+	begin
+		if (rising_edge(clkIn)) then
+			if (s_divCounter >= (divFactor - 1)) then
+				clkOut <= '0';
+				s_divCounter <= 0;
+			else
+				if (s_divCounter = (divFactor / 2 - 1)) then
+					clkOut <= '1';
+				end if;
+				s_divCounter <= s_divCounter + 1;
+			end if;
+		end if;
+	end process;
+end Behavioral;

1ano/2semestre/lsd/pratica05/TimerN_Demo/TimerN.bsf

@@ -0,0 +1,71 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 176 128)
+	(text "TimerN" (rect 5 0 35 12)(font "Arial" ))
+	(text "inst" (rect 8 96 20 108)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 27 31 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "enable" (rect 0 0 24 12)(font "Arial" ))
+		(text "enable" (rect 21 43 45 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "start" (rect 0 0 17 12)(font "Arial" ))
+		(text "start" (rect 21 59 38 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "reset" (rect 0 0 20 12)(font "Arial" ))
+		(text "reset" (rect 21 75 41 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "timerOut" (rect 0 0 34 12)(font "Arial" ))
+		(text "timerOut" (rect 105 27 139 39)(font "Arial" ))
+		(line (pt 160 32)(pt 144 32)(line_width 1))
+	)
+	(parameter
+		"N"
+		"6"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(rectangle (rect 16 16 144 96)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 176 -64 276 16))
+)

1ano/2semestre/lsd/pratica05/TimerN_Demo/TimerN.vhd

@@ -0,0 +1,40 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity TimerN is
+	generic (N : positive := 6);
+	port
+	(
+		clk      : in  std_logic;
+		enable   : in  std_logic;
+		start    : in  std_logic;
+		reset    : in  std_logic;
+		timerOut : out std_logic
+	);
+end TimerN;
+
+architecture Behavioral of TimerN is
+	signal s_count : std_logic_vector(31 downto 0);
+begin
+	process (clk)
+	begin
+		if (rising_edge(clk)) then
+			if (reset = '0' and enable = '1') then
+				if (unsigned(s_count) < N and not (unsigned(s_count) = 0 and start = '0')) then
+					s_count <= std_logic_vector(unsigned(s_count) + 1);
+				else
+					s_count <= (others => '0');
+				end if;
+			elsif (reset = '1') then
+				s_count <= (others => '0');
+			end if;
+			
+			if (unsigned(s_count) = 0) then
+				timerOut <= '0';
+			else
+				timerOut <= '1';
+			end if;
+		end if;
+	end process;
+end Behavioral;

1ano/2semestre/lsd/pratica05/TimerN_Demo/TimerN_Demo.bdf

@@ -0,0 +1,228 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 664 304 680 472)
+	(text "INPUT" (rect 0 14 10 43)(font "Arial" (font_size 6))(vertical))
+	(text "SW[2]" (rect 0 133 11 163)(font "Arial" )(vertical))
+	(pt 8 0)
+	(drawing
+		(line (pt 12 84)(pt 12 59))
+		(line (pt 4 84)(pt 4 59))
+		(line (pt 8 55)(pt 8 0))
+		(line (pt 12 84)(pt 4 84))
+		(line (pt 4 59)(pt 8 55))
+		(line (pt 12 59)(pt 8 55))
+	)
+	(rotate90)
+	(text "VCC" (rect 7 19 17 40)(font "Arial" (font_size 6))(vertical))
+	(annotation_block (location)(rect 600 472 664 488))
+)
+(pin
+	(input)
+	(rect 648 304 664 472)
+	(text "INPUT" (rect 0 14 10 43)(font "Arial" (font_size 6))(vertical))
+	(text "SW[1]" (rect 0 129 13 163)(font "Intel Clear" )(vertical))
+	(pt 8 0)
+	(drawing
+		(line (pt 12 84)(pt 12 59))
+		(line (pt 4 84)(pt 4 59))
+		(line (pt 8 55)(pt 8 0))
+		(line (pt 12 84)(pt 4 84))
+		(line (pt 4 59)(pt 8 55))
+		(line (pt 12 59)(pt 8 55))
+	)
+	(rotate90)
+	(text "VCC" (rect 7 19 17 40)(font "Arial" (font_size 6))(vertical))
+	(annotation_block (location)(rect 584 472 648 488))
+)
+(pin
+	(input)
+	(rect 632 304 648 472)
+	(text "INPUT" (rect 0 14 10 43)(font "Arial" (font_size 6))(vertical))
+	(text "SW[0]" (rect 0 129 13 163)(font "Intel Clear" )(vertical))
+	(pt 8 0)
+	(drawing
+		(line (pt 12 84)(pt 12 59))
+		(line (pt 4 84)(pt 4 59))
+		(line (pt 8 55)(pt 8 0))
+		(line (pt 12 84)(pt 4 84))
+		(line (pt 4 59)(pt 8 55))
+		(line (pt 12 59)(pt 8 55))
+	)
+	(rotate90)
+	(text "VCC" (rect 7 19 17 40)(font "Arial" (font_size 6))(vertical))
+	(annotation_block (location)(rect 568 472 632 488))
+)
+(pin
+	(input)
+	(rect 472 256 488 424)
+	(text "INPUT" (rect 0 14 10 43)(font "Arial" (font_size 6))(vertical))
+	(text "CLOCK_50" (rect 0 105 11 163)(font "Arial" )(vertical))
+	(pt 8 0)
+	(drawing
+		(line (pt 12 84)(pt 12 59))
+		(line (pt 4 84)(pt 4 59))
+		(line (pt 8 55)(pt 8 0))
+		(line (pt 12 84)(pt 4 84))
+		(line (pt 4 59)(pt 8 55))
+		(line (pt 12 59)(pt 8 55))
+	)
+	(rotate90)
+	(text "VCC" (rect 7 19 17 40)(font "Arial" (font_size 6))(vertical))
+	(annotation_block (location)(rect 416 424 472 440))
+)
+(pin
+	(output)
+	(rect 848 240 1024 256)
+	(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
+	(text "LEDR[0]" (rect 90 0 132 11)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 1024 256 1088 272))
+)
+(symbol
+	(rect 680 216 840 328)
+	(text "TimerN" (rect 5 0 41 11)(font "Arial" ))
+	(text "inst1" (rect 8 96 32 109)(font "Intel Clear" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk" (rect 0 0 15 11)(font "Arial" ))
+		(text "clk" (rect 21 27 36 38)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "enable" (rect 0 0 34 11)(font "Arial" ))
+		(text "enable" (rect 21 43 55 54)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "start" (rect 0 0 23 11)(font "Arial" ))
+		(text "start" (rect 21 59 44 70)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "reset" (rect 0 0 25 11)(font "Arial" ))
+		(text "reset" (rect 21 75 46 86)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "timerOut" (rect 0 0 43 11)(font "Arial" ))
+		(text "timerOut" (rect 103 27 146 38)(font "Arial" ))
+		(line (pt 160 32)(pt 144 32))
+	)
+	(parameter
+		"N"
+		"6"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(rectangle (rect 16 16 144 96))
+	)
+	(annotation_block (parameter)(rect 840 184 1016 216))
+)
+(symbol
+	(rect 488 216 632 296)
+	(text "FreqDivider" (rect 5 0 64 11)(font "Arial" ))
+	(text "inst" (rect 8 64 26 75)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clkIn" (rect 0 0 24 11)(font "Arial" ))
+		(text "clkIn" (rect 21 27 45 38)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 144 32)
+		(output)
+		(text "clkOut" (rect 0 0 33 11)(font "Arial" ))
+		(text "clkOut" (rect 96 27 129 38)(font "Arial" ))
+		(line (pt 144 32)(pt 128 32))
+	)
+	(parameter
+		"divFactor"
+		"50000000"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(rectangle (rect 16 16 128 64))
+	)
+	(annotation_block (parameter)(rect 632 184 826 214))
+)
+(connector
+	(pt 672 296)
+	(pt 672 304)
+)
+(connector
+	(pt 680 296)
+	(pt 672 296)
+)
+(connector
+	(pt 656 304)
+	(pt 656 280)
+)
+(connector
+	(pt 656 280)
+	(pt 680 280)
+)
+(connector
+	(pt 680 264)
+	(pt 640 264)
+)
+(connector
+	(pt 640 264)
+	(pt 640 304)
+)
+(connector
+	(pt 680 248)
+	(pt 632 248)
+)
+(connector
+	(pt 488 248)
+	(pt 480 248)
+)
+(connector
+	(pt 480 248)
+	(pt 480 256)
+)
+(connector
+	(pt 848 248)
+	(pt 840 248)
+)

1ano/2semestre/lsd/pratica06/README.md

@@ -0,0 +1,9 @@
+# Laboratórios de Sistemas Digitais
+## Trabalho prático 06
+### Tópico principal da aula: Modelação em VHDL e implementação de registos e módulos combinatórios de deslocamento
+
+* [Slides](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/slides/LSD_2022-23_AulaTP06.pdf)
+* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica03/LSD_2022-23_TrabPrat06.pdf)
+
+---
+*Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)

1ano/2semestre/lsd/pratica07/README.md

@@ -0,0 +1,14 @@
+# Laboratórios de Sistemas Digitais
+## Trabalho prático 07
+### Tópicos da aula:
+* #### Construção e utilização de testbenches em VHDL
+* #### Simulação comportamental e temporal
+* #### Depuração de circuitos em FPGA
+
+---
+
+* [Slides](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/slides/LSD_2022-23_AulaTP07.pdf)
+* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica03/LSD_2022-23_TrabPrat07.pdf)
+
+---
+*Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)

1ano/2semestre/lsd/pratica10/README.md

@@ -0,0 +1,9 @@
+# Laboratórios de Sistemas Digitais
+## Trabalho prático 10
+### Tópico principal da aula: Modelação em VHDL de Memórias ROM e RAM de um Porto e Multi-porto
+
+* [Slides](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/slides/LSD_2022-23_AulaTP10.pdf)
+* [Guião](https://github.com/TiagoRG/uaveiro-leci/blob/master/1ano/2semestre/lsd/pratica03/LSD_2022-23_TrabPrat10.pdf)
+
+---
+*Pode conter erros, caso encontre algum, crie um* [*ticket*](https://github.com/TiagoRG/uaveiro-leci/issues/new)