diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.bsf b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.bsf new file mode 100644 index 0000000..e7f4eaf --- /dev/null +++ b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.bsf @@ -0,0 +1,65 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 176 128) + (text "ALU4" (rect 5 0 32 12)(font "Arial" )) + (text "inst" (rect 8 96 20 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "a[3..0]" (rect 0 0 24 12)(font "Arial" )) + (text "a[3..0]" (rect 21 27 45 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "b[3..0]" (rect 0 0 24 12)(font "Arial" )) + (text "b[3..0]" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "op[2..0]" (rect 0 0 29 12)(font "Arial" )) + (text "op[2..0]" (rect 21 59 50 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 160 32) + (output) + (text "r[3..0]" (rect 0 0 23 12)(font "Arial" )) + (text "r[3..0]" (rect 116 27 139 39)(font "Arial" )) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 48) + (output) + (text "m[3..0]" (rect 0 0 28 12)(font "Arial" )) + (text "m[3..0]" (rect 111 43 139 55)(font "Arial" )) + (line (pt 160 48)(pt 144 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 144 96)(line_width 1)) + ) +) diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.vhd b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.vhd new file mode 100644 index 0000000..64977d2 --- /dev/null +++ b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALU4.vhd @@ -0,0 +1,35 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity ALU4 is + port + ( + a,b : in std_logic_vector(3 downto 0); + op : in std_logic_vector(2 downto 0); + r, m : out std_logic_vector(3 downto 0) + ); +end ALU4; + +architecture Behavioral of ALU4 is + signal s_a, s_b, s_r : unsigned(3 downto 0); + signal s_m : unsigned(7 downto 0); +begin + s_a <= unsigned(a); + s_b <= unsigned(b); + + s_m <= s_a * s_b; + + with op select + s_r <= s_a + s_b when "000", + s_a - s_b when "001", + s_m(3 downto 0) when "010", + s_a / s_b when "011", + s_a rem s_b when "100", + s_a and s_b when "101", + s_a or s_b when "110", + s_a xor s_b when "111"; + + r <= std_logic_vector(s_r); + m <= std_logic_vector(s_m(7 downto 4)) when (op = "010") else (others => '0'); +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALUDemo.bdf b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALUDemo.bdf new file mode 100644 index 0000000..ed4ab56 --- /dev/null +++ b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/ALUDemo.bdf @@ -0,0 +1,285 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 272 144 440 160) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[3..0]" (rect 5 0 48 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 208 160 272 176)) +) +(pin + (input) + (rect 272 160 440 176) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[7..4]" (rect 5 0 49 13)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 208 176 272 192)) +) +(pin + (input) + (rect 272 176 440 192) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[10..8]" (rect 5 0 54 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 208 192 272 208)) +) +(pin + (output) + (rect 856 144 1032 160) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "HEX0[6..0]" (rect 90 0 144 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1032 160 1096 176)) +) +(pin + (output) + (rect 856 224 1032 240) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "HEX1[6..0]" (rect 90 0 144 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1032 240 1096 256)) +) +(symbol + (rect 448 120 608 232) + (text "ALU4" (rect 5 0 34 11)(font "Arial" )) + (text "inst" (rect 8 96 26 107)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "a[3..0]" (rect 0 0 30 11)(font "Arial" )) + (text "a[3..0]" (rect 21 27 51 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "b[3..0]" (rect 0 0 30 11)(font "Arial" )) + (text "b[3..0]" (rect 21 43 51 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "op[2..0]" (rect 0 0 37 11)(font "Arial" )) + (text "op[2..0]" (rect 21 59 58 70)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 160 32) + (output) + (text "r[3..0]" (rect 0 0 28 11)(font "Arial" )) + (text "r[3..0]" (rect 116 27 144 38)(font "Arial" )) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (port + (pt 160 48) + (output) + (text "m[3..0]" (rect 0 0 34 11)(font "Arial" )) + (text "m[3..0]" (rect 111 43 145 54)(font "Arial" )) + (line (pt 160 48)(pt 144 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 144 96)) + ) +) +(symbol + (rect 640 120 848 200) + (text "Bin7SegDecoder" (rect 5 0 89 11)(font "Arial" )) + (text "inst1" (rect 8 64 32 77)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "binInput[3..0]" (rect 0 0 63 11)(font "Arial" )) + (text "binInput[3..0]" (rect 21 27 84 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "enable" (rect 0 0 34 11)(font "Arial" )) + (text "enable" (rect 21 43 55 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 208 32) + (output) + (text "decOut_n[6..0]" (rect 0 0 73 11)(font "Arial" )) + (text "decOut_n[6..0]" (rect 126 27 199 38)(font "Arial" )) + (line (pt 208 32)(pt 192 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 192 64)) + ) +) +(symbol + (rect 640 200 848 280) + (text "Bin7SegDecoder" (rect 5 0 89 11)(font "Arial" )) + (text "inst2" (rect 8 64 32 77)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "binInput[3..0]" (rect 0 0 63 11)(font "Arial" )) + (text "binInput[3..0]" (rect 21 27 84 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "enable" (rect 0 0 34 11)(font "Arial" )) + (text "enable" (rect 21 43 55 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 208 32) + (output) + (text "decOut_n[6..0]" (rect 0 0 73 11)(font "Arial" )) + (text "decOut_n[6..0]" (rect 126 27 199 38)(font "Arial" )) + (line (pt 208 32)(pt 192 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 192 64)) + ) +) +(symbol + (rect 608 128 640 144) + (text "VCC" (rect 7 0 28 10)(font "Arial" (font_size 6))) + (text "inst3" (rect 3 5 27 18)(font "Intel Clear" )(invisible)) + (port + (pt 16 16) + (output) + (text "1" (rect 19 7 27 18)(font "Courier New" (bold))(invisible)) + (text "1" (rect 19 7 27 18)(font "Courier New" (bold))(invisible)) + (line (pt 16 16)(pt 16 8)) + ) + (drawing + (line (pt 8 8)(pt 24 8)) + ) +) +(connector + (pt 448 152) + (pt 440 152) + (bus) +) +(connector + (pt 448 168) + (pt 440 168) + (bus) +) +(connector + (pt 448 184) + (pt 440 184) + (bus) +) +(connector + (pt 608 168) + (pt 616 168) + (bus) +) +(connector + (pt 608 152) + (pt 640 152) + (bus) +) +(connector + (pt 624 168) + (pt 640 168) +) +(connector + (pt 616 168) + (pt 616 232) + (bus) +) +(connector + (pt 616 232) + (pt 640 232) + (bus) +) +(connector + (pt 624 248) + (pt 640 248) +) +(connector + (pt 624 144) + (pt 624 168) +) +(connector + (pt 624 168) + (pt 624 248) +) +(connector + (pt 856 232) + (pt 848 232) + (bus) +) +(connector + (pt 848 152) + (pt 856 152) + (bus) +) +(junction (pt 624 168)) diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.bsf b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.bsf new file mode 100644 index 0000000..2cc9938 --- /dev/null +++ b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.bsf @@ -0,0 +1,51 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 224 96) + (text "Bin7SegDecoder" (rect 5 0 71 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "binInput[3..0]" (rect 0 0 49 12)(font "Arial" )) + (text "binInput[3..0]" (rect 21 27 70 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "enable" (rect 0 0 24 12)(font "Arial" )) + (text "enable" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 208 32) + (output) + (text "decOut_n[6..0]" (rect 0 0 59 12)(font "Arial" )) + (text "decOut_n[6..0]" (rect 128 27 187 39)(font "Arial" )) + (line (pt 208 32)(pt 192 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 192 64)(line_width 1)) + ) +) diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.vhd b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.vhd new file mode 100644 index 0000000..96f7b6b --- /dev/null +++ b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/Bin7SegDecoder.vhd @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity Bin7SegDecoder is + port + ( + binInput : in std_logic_vector(3 downto 0); + enable : in std_logic; + decOut_n : out std_logic_vector(6 downto 0) + ); +end Bin7SegDecoder; + +architecture Behavioral of Bin7SegDecoder is +begin + decOut_n <= "1111111" when (enable = '0' ) else -- disabled + "1111001" when (binInput = "0001") else --1 + "0100100" when (binInput = "0010") else --2 + "0110000" when (binInput = "0011") else --3 + "0011001" when (binInput = "0100") else --4 + "0010010" when (binInput = "0101") else --5 + "0000010" when (binInput = "0110") else --6 + "1111000" when (binInput = "0111") else --7 + "0000000" when (binInput = "1000") else --8 + "0010000" when (binInput = "1001") else --9 + "0001000" when (binInput = "1010") else --A + "0000011" when (binInput = "1011") else --b + "1000110" when (binInput = "1100") else --C + "0100001" when (binInput = "1101") else --d + "0000110" when (binInput = "1110") else --E + "0001110" when (binInput = "1111") else --F + "1000000"; --0 +end Behavioral; diff --git a/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/output_files/ALUDisplayDemo.sof b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/output_files/ALUDisplayDemo.sof new file mode 100644 index 0000000..8651d79 Binary files /dev/null and b/1ano/2semestre/lsd/pratica03/ALUDisplayDemo/output_files/ALUDisplayDemo.sof differ