diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Bin7SegDecoder.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Bin7SegDecoder.vhd new file mode 100644 index 0000000..96f7b6b --- /dev/null +++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Bin7SegDecoder.vhd @@ -0,0 +1,32 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity Bin7SegDecoder is + port + ( + binInput : in std_logic_vector(3 downto 0); + enable : in std_logic; + decOut_n : out std_logic_vector(6 downto 0) + ); +end Bin7SegDecoder; + +architecture Behavioral of Bin7SegDecoder is +begin + decOut_n <= "1111111" when (enable = '0' ) else -- disabled + "1111001" when (binInput = "0001") else --1 + "0100100" when (binInput = "0010") else --2 + "0110000" when (binInput = "0011") else --3 + "0011001" when (binInput = "0100") else --4 + "0010010" when (binInput = "0101") else --5 + "0000010" when (binInput = "0110") else --6 + "1111000" when (binInput = "0111") else --7 + "0000000" when (binInput = "1000") else --8 + "0010000" when (binInput = "1001") else --9 + "0001000" when (binInput = "1010") else --A + "0000011" when (binInput = "1011") else --b + "1000110" when (binInput = "1100") else --C + "0100001" when (binInput = "1101") else --d + "0000110" when (binInput = "1110") else --E + "0001110" when (binInput = "1111") else --F + "1000000"; --0 +end Behavioral; diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Counter.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Counter.vhd new file mode 100644 index 0000000..467fcc4 --- /dev/null +++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/Counter.vhd @@ -0,0 +1,42 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity Counter is + port + ( + clk : in std_logic; + reset : in std_logic; + count : out std_logic_vector(3 downto 0) + ); +end Counter; + +architecture Behavioral of Counter is + signal up : std_logic := '1'; + signal s_count : unsigned(3 downto 0) := to_unsigned(0, 4); +begin + process(clk, reset) + begin + if (reset = '1') then + s_count <= to_unsigned(0, 4); + up <= '1'; + elsif (rising_edge(clk)) then + if (up = '1') then + if (std_logic_vector(s_count) = "1111") then + s_count <= s_count - 1; + up <= '0'; + else + s_count <= s_count + 1; + end if; + else + if (std_logic_vector(s_count) = "0000") then + s_count <= s_count + 1; + up <= '1'; + else + s_count <= s_count - 1; + end if; + end if; + end if; + end process; + count <= std_logic_vector(s_count); +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/FreqDivider.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/FreqDivider.vhd new file mode 100644 index 0000000..a0b77ec --- /dev/null +++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/FreqDivider.vhd @@ -0,0 +1,36 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity FreqDivider is + generic(divFactor : positive := 10); + port + ( + clkIn : in std_logic; + multi : in positive := 1; + clkOut : out std_logic + ); +end FreqDivider; + +architecture Behavioral of FreqDivider is + subtype TCounter is natural range 0 to divFactor - 1; + signal s_divFactor : positive := 10; + signal s_divCounter : TCounter := 0; +begin + s_divFactor <= divFactor / multi; + assert(divFactor >= 2); + process(clkIn) + begin + if (rising_edge(clkIn)) then + if (s_divCounter >= (s_divFactor - 1)) then + clkOut <= '0'; + s_divCounter <= 0; + else + if (s_divCounter = (s_divFactor / 2 - 1)) then + clkOut <= '1'; + end if; + s_divCounter <= s_divCounter + 1; + end if; + end if; + end process; +end Behavioral; diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/HexToDec4Bit.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/HexToDec4Bit.vhd new file mode 100644 index 0000000..c0f8f1a --- /dev/null +++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/HexToDec4Bit.vhd @@ -0,0 +1,80 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity HexToDec4Bit is + port + ( + hexIn : in std_logic_vector(3 downto 0); + cin : in std_logic; + decOut0 : out std_logic_vector(3 downto 0); + decOut1 : out std_logic_vector(3 downto 0) + ); +end HexToDec4Bit; + +architecture Behavioral of HexToDec4Bit is +begin + process (hexIn, cin) is + begin + if cin = '1' then + if hexIn = "0000" then + decOut0 <= "0110"; + elsif hexIn = "0001" then + decOut0 <= "0111"; + elsif hexIn = "0010" then + decOut0 <= "1000"; + elsif hexIn = "0011" then + decOut0 <= "1001"; + elsif hexIn = "0100" then + decOut0 <= "0000"; + elsif hexIn = "0101" then + decOut0 <= "0001"; + elsif hexIn = "0110" then + decOut0 <= "0010"; + elsif hexIn = "0111" then + decOut0 <= "0011"; + elsif hexIn = "1000" then + decOut0 <= "0100"; + elsif hexIn = "1001" then + decOut0 <= "0101"; + elsif hexIn = "1010" then + decOut0 <= "0110"; + elsif hexIn = "1011" then + decOut0 <= "0111"; + elsif hexIn = "1100" then + decOut0 <= "1000"; + elsif hexIn = "1101" then + decOut0 <= "1001"; + else + decOut0 <= "0000"; + end if; + + if hexIn < "0100" then + decOut1 <= "0001"; + elsif hexIn < "1110" then + decOut1 <= "0010"; + else + decOut1 <= "0011"; + end if; + else + if hexIn < "1010" then + decOut0 <= hexIn; + decOut1 <= "0000"; + else + if hexIn = "1010" then + decOut0 <= "0000"; + elsif hexIn = "1011" then + decOut0 <= "0001"; + elsif hexIn = "1100" then + decOut0 <= "0010"; + elsif hexIn = "1101" then + decOut0 <= "0011"; + elsif hexIn = "1110" then + decOut0 <= "0100"; + else + decOut0 <= "0101"; + end if; + decOut1 <= "0001"; + end if; + end if; + end process; +end Behavioral; diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/LedDisplayer.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/LedDisplayer.vhd new file mode 100644 index 0000000..02788c8 --- /dev/null +++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/LedDisplayer.vhd @@ -0,0 +1,31 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity LedDisplayer is + port + ( + count : in std_logic_vector(3 downto 0); + ledOut : out std_logic_vector(14 downto 0) + ); +end LedDisplayer; + +architecture Behavioral of LedDisplayer is +begin + with count select + ledOut <= "000000000000000" when "0000", + "000000000000001" when "0001", + "000000000000011" when "0010", + "000000000000111" when "0011", + "000000000001111" when "0100", + "000000000011111" when "0101", + "000000000111111" when "0110", + "000000001111111" when "0111", + "000000011111111" when "1000", + "000000111111111" when "1001", + "000001111111111" when "1010", + "000011111111111" when "1011", + "000111111111111" when "1100", + "001111111111111" when "1101", + "011111111111111" when "1110", + "111111111111111" when "1111"; +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/MiniProj_Demo.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/MiniProj_Demo.vhd new file mode 100644 index 0000000..b5669ef --- /dev/null +++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/MiniProj_Demo.vhd @@ -0,0 +1,84 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity MiniProj_Demo is + port + ( + CLOCK_50 : in std_logic; + KEY : in std_logic_vector(1 downto 0); + LEDR : out std_logic_vector(14 downto 0); + HEX0 : out std_logic_vector(6 downto 0); + HEX1 : out std_logic_vector(6 downto 0) + ); +end MiniProj_Demo; + +architecture Shell of MiniProj_Demo is + signal s_clk_def, s_clk_div : std_logic; + signal s_speed : positive := 4; + signal s_reset : std_logic; + + signal s_count : std_logic_vector(3 downto 0); + + signal s_display0, s_display1 : std_logic_vector(3 downto 0); +begin + s_clk_def <= CLOCK_50; + s_reset <= not KEY(0); + + speed_select : entity work.SpeedSelect(Behavioral) + port map + ( + toggle => not KEY(1), + reset => s_reset, + speed => s_speed + ); + + freq_divider : entity work.FreqDivider(Behavioral) + generic map (divFactor => 50_000_000) + port map + ( + clkIn => s_clk_def, + multi => s_speed, + clkOut => s_clk_div + ); + + counter : entity work.Counter(Behavioral) + port map + ( + clk => s_clk_div, + reset => s_reset, + count => s_count + ); + + led_display : entity work.LedDisplayer(Behavioral) + port map + ( + count => s_count, + ledOut => LEDR + ); + + hex_to_dec : entity work.HexToDec4Bit(Behavioral) + port map + ( + hexIn => s_count, + cin => '0', + decOut0 => s_display0, + decOut1 => s_display1 + ); + + display0 : entity work.Bin7SegDecoder(Behavioral) + port map + ( + enable => '1', + binInput => s_display0, + decOut_n => HEX0 + ); + + display1 : entity work.Bin7SegDecoder(Behavioral) + port map + ( + enable => '1', + binInput => s_display1, + decOut_n => HEX1 + ); + +end Shell; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/SpeedSelect.vhd b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/SpeedSelect.vhd new file mode 100644 index 0000000..3377c4b --- /dev/null +++ b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/SpeedSelect.vhd @@ -0,0 +1,31 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity SpeedSelect is + port + ( + toggle : in std_logic; + reset : in std_logic; + speed : out positive := 4 + ); +end SpeedSelect; + +architecture Behavioral of SpeedSelect is + signal current_speed : positive := 4; +begin + process(toggle, reset) + begin + if (reset = '1') then + current_speed <= 4; + else + if (toggle = '1') then + if (current_speed = 1) then + current_speed <= 4; + else + current_speed <= 1; + end if; + end if; + end if; + end process; + speed <= current_speed; +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/output_files/MiniProj_Demo.sof b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/output_files/MiniProj_Demo.sof new file mode 100644 index 0000000..ba44e70 Binary files /dev/null and b/1ano/2semestre/lsd/projects/MiniProj_Demo_21-22/output_files/MiniProj_Demo.sof differ