diff --git a/1ano/2semestre/lsd/projects/BreadMachine/LICENSE b/1ano/2semestre/lsd/projects/BreadMachine/LICENSE new file mode 100644 index 0000000..1b260f6 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2023 Tiago Garcia + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/1ano/2semestre/lsd/projects/BreadMachine/LSD_2022-23_RegrasProjFinais.pdf b/1ano/2semestre/lsd/projects/BreadMachine/LSD_2022-23_RegrasProjFinais.pdf new file mode 100644 index 0000000..b0c7119 Binary files /dev/null and b/1ano/2semestre/lsd/projects/BreadMachine/LSD_2022-23_RegrasProjFinais.pdf differ diff --git a/1ano/2semestre/lsd/projects/BreadMachine/LSD_2022_2023_Proj_7.pdf b/1ano/2semestre/lsd/projects/BreadMachine/LSD_2022_2023_Proj_7.pdf new file mode 100644 index 0000000..5ca8fe5 Binary files /dev/null and b/1ano/2semestre/lsd/projects/BreadMachine/LSD_2022_2023_Proj_7.pdf differ diff --git a/1ano/2semestre/lsd/projects/BreadMachine/README.md b/1ano/2semestre/lsd/projects/BreadMachine/README.md new file mode 100644 index 0000000..3451cf9 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/README.md @@ -0,0 +1,2 @@ +# BreadMachine +Simple bread machine diff --git a/1ano/2semestre/lsd/projects/BreadMachine/report/images/esquema-placa.png b/1ano/2semestre/lsd/projects/BreadMachine/report/images/esquema-placa.png new file mode 100644 index 0000000..43a8ef7 Binary files /dev/null and b/1ano/2semestre/lsd/projects/BreadMachine/report/images/esquema-placa.png differ diff --git a/1ano/2semestre/lsd/projects/BreadMachine/report/images/state-machine.png b/1ano/2semestre/lsd/projects/BreadMachine/report/images/state-machine.png new file mode 100644 index 0000000..04f7407 Binary files /dev/null and b/1ano/2semestre/lsd/projects/BreadMachine/report/images/state-machine.png differ diff --git a/1ano/2semestre/lsd/projects/BreadMachine/report/images/top-level-design.png b/1ano/2semestre/lsd/projects/BreadMachine/report/images/top-level-design.png new file mode 100644 index 0000000..932880a Binary files /dev/null and b/1ano/2semestre/lsd/projects/BreadMachine/report/images/top-level-design.png differ diff --git a/1ano/2semestre/lsd/projects/BreadMachine/report/images/ua.pdf b/1ano/2semestre/lsd/projects/BreadMachine/report/images/ua.pdf new file mode 100644 index 0000000..460cb18 Binary files /dev/null and b/1ano/2semestre/lsd/projects/BreadMachine/report/images/ua.pdf differ diff --git a/1ano/2semestre/lsd/projects/BreadMachine/report/relatorio-projeto.pdf b/1ano/2semestre/lsd/projects/BreadMachine/report/relatorio-projeto.pdf new file mode 100644 index 0000000..2b2e766 Binary files /dev/null and b/1ano/2semestre/lsd/projects/BreadMachine/report/relatorio-projeto.pdf differ diff --git a/1ano/2semestre/lsd/projects/BreadMachine/report/src/Makefile b/1ano/2semestre/lsd/projects/BreadMachine/report/src/Makefile new file mode 100644 index 0000000..cf1ac68 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/report/src/Makefile @@ -0,0 +1,17 @@ +.PHONY: all clean cleanall + +all: documento.pdf + +documento.pdf: documento.tex bibliografia.bib + pdflatex documento.tex + biber documento + pdflatex documento.tex + pdflatex documento.tex + mv documento.pdf ../ + +clean: + rm -f *.aux *.blg *.bbl *.toc *.log *.lof *.lot *.log.xml *.bcf *.out *.run.xml + +cleanall: clean + rm -f documento.pdf ../documento.pdf + diff --git a/1ano/2semestre/lsd/projects/BreadMachine/report/src/arquitetura-e-implementacao.tex b/1ano/2semestre/lsd/projects/BreadMachine/report/src/arquitetura-e-implementacao.tex new file mode 100644 index 0000000..b366bd5 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/report/src/arquitetura-e-implementacao.tex @@ -0,0 +1,75 @@ +O Top-Level da máquina é composto por 3 componentes principais que depois se ramificam em subcomponentes mais pequenos. + +A figura~\ref{fig:top-level} representa uma ilustração gráfica do Top-Level da máquina implementado em \ac{vhdl}. + +\begin{figure}[h] + \center + \includegraphics[scale=.25]{../images/top-level-design}\caption{Ilustração do Top-Level da Máquina} + \label{fig:top-level} +\end{figure} + +\section{Debouncers} +\label{sec:debouncers} +Este componente é responsável por fazer o Debounce dos botões.\ Isto é necessário pois quando um botão é pressionado gera centenas de sinais, o que pode muitas vezes causar problemas. + +O bloco recebe o valor do relógio geral da máquina bem como os valores dos botões a ser afetados. + +Dentro do bloco os valores dos botões são distribuídos entre 3 debouncers onde são processados para gerar os sinais pretendidos. + +Sai deste bloco os sinais dos botões já corrigidos para que seja emitido apenas 1 sinal positivo por clique. + +\section{BreadMachineFSM} +\label{sec:fsm} +Este é o componente principal da máquina e é o responsável pelo processamento do funcionamento da mesma. + +Entram neste componente o sinal do relógio da máquina, os sinais dos botões de `Reiniciar', `Start/Stop' e `Tempo Extra', recebe também o sinal do interruptor do `Selecionador Programa' e, por último, o valor do vetor gerado pelos interruptores do `Selecionador Atraso'. + +Como saídas irá ter o sinal para indicar se a máquina se encontra no estado `Progress' ou `Extra'.\ Faz também parte das saídas o vetor de indicação da `Fase da Fabricação' que está a decorrer no momento.\ Estas saídas são diretamente ligadas aos LEDS da máquina: 1 LED vermelho e 3 LEDS verdes, respetivamente. + +O funcionamento da máquina de estados será descrito com recurso à figura~\ref{fig:state-machine}. + +\pagebreak + +\begin{figure} + \centering + \includegraphics[scale=.4]{../images/state-machine} + \caption{Esquema da Máquina de Estados} + \label{fig:state-machine} +\end{figure} + +\begin{enumerate} + \item \textbf{Reset} + \\$\hookrightarrow$ A máquina volta sempre ao estado de Reset quando o botão `Reset' é pressionado. + \item \textbf{(Delay/Progress/Extra) $\leftrightarrow$ OnHold} + \\$\hookrightarrow$ Quando o botão de `Start/Stop' é utilizado e o estado é `Delay', `Progress' ou `Extra', muda o estado para `OnHold' para pausar a máquina. + \\$\hookrightarrow$ Quando o botão de `Start/Stop' é utilizado e o estado atual é `OnHold', retoma o estado para o qual a máquina se previamente encontrava (`Delay', `Progress' ou `Extra'). + \item \textbf{OnHold $\rightarrow$ OnHold} + \\$\hookrightarrow$ Atualiza o valor do start\_stop negando o mesmo.\ Fica neste estado enquanto o valor do start\_stop for `0' e sai do estado quando passar para `1'. + \item \textbf{Reset $\rightarrow$ Standby} + \\$\hookrightarrow$ Assim que a máquina é reiniciada, o estado muda automaticamente para Standby após a reinicialização de todos os valores. + \item \textbf{Standby $\rightarrow$ Delay} + \\$\hookrightarrow$ Quando o botão de `Start/Stop' é pressionado, muda de estado para `Delay' começando o timer do atraso inicial com o valor escolhido. + \item \textbf{Delay $\rightarrow$ Progress} + \\$\hookrightarrow$ Assim que o tempo do atraso inicial chegar a 0, o estado passa automaticamente de `Delay' para `Progress'. + \item \textbf{Progress $\rightarrow$ Finish} + \\$\hookrightarrow$ Assim que o tempo da programação chegar a 0, o estado passa automaticamente de `Progress' para `Finish'. + \\$\hookrightarrow$ Neste estado, a máquina não se encontra com nenhuma mudança visual imediata, fica a aguardar por um dos botões.\ Usando o botão `Tempo Extra' poderá ser definido o tempo extra a aplicar à máquina posteriormente no estado `Extra'. + \item \textbf{Finish $\rightarrow$ Extra} + \\$\hookrightarrow$ Esta mudança é realizada quando o botão `Start/Stop' é pressionado e o tempo extra não se encontra a 0. + \item \textbf{Extra $\rightarrow$ Finish} + \\$\hookrightarrow$ Assim que o tempo do tempo extra chegar a 0, o estado passa automaticamente de `Extra' para `Finish'. + \item \textbf{Finish $\rightarrow$ Reset} + \\$\hookrightarrow$ Esta mudança é realizada quando o botão `Start/Stop' é pressionado e o tempo extra encontra-se a 0.\ Este passo reinicializa a máquina automaticamente. +\end{enumerate} + +\textbf{Nota:} Os passos 2, 3, 8 e 9 podem ocorrer um número de vezes indefinido durante uma execução completa da máquina. + +\section{DisplaysManager} +\label{sec:displays-manager} +Este último componente é o responsável pela gestão dos displays para que os números dos tempos da máquina sejam corretamente visualizados. + +O bloco recebe separadamente os valores dos 3 tempos: `Atraso Inicial', `Tempo Normal' e `Tempo Extra'. + +O tempo extra é diretamente processado para a codificação dos displays, enquanto que o atraso inicial e o tempo normal têm de ser convertidos em numeração decimal (gerando 2 valores cada) para depois serem codificados.\ Este passo produz 5 valores diferentes. + +Esses 5 valores são então distribuídos pelos 5 displays da máquina. \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/BreadMachine/report/src/bibliografia.bib b/1ano/2semestre/lsd/projects/BreadMachine/report/src/bibliografia.bib new file mode 100644 index 0000000..d7a8a9a --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/report/src/bibliografia.bib @@ -0,0 +1,7 @@ +@misc{glisc, + author={{Grey Literature International Steering Committee}}, + title={{GLISC}}, + month={oct}, + year={2014}, + note = "[Online; acedido em Outubro 2014]" +} diff --git a/1ano/2semestre/lsd/projects/BreadMachine/report/src/documento.tex b/1ano/2semestre/lsd/projects/BreadMachine/report/src/documento.tex new file mode 100644 index 0000000..f7d83b0 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/report/src/documento.tex @@ -0,0 +1,141 @@ +\documentclass{report} +\usepackage[T1]{fontenc} % Fontes T1 +\usepackage[utf8]{inputenc} % Input UTF8 +\usepackage[backend=biber, style=ieee]{biblatex} % para usar bibliografia +\usepackage{csquotes} +\usepackage[portuguese]{babel} %Usar língua portuguesa +\usepackage{blindtext} % Gerar texto automaticamente +\usepackage[printonlyused]{acronym} +\usepackage{hyperref} % para autoref +\usepackage{graphicx} +\usepackage{indentfirst} +\usepackage{float} +\usepackage{geometry} + +\geometry{ + paper=a4paper, + margin=45pt, + includefoot +} + +\bibliography{bibliografia} + + +\begin{document} +%% +% Definições +% +\def\titulo{Máquina de Pão} +\def\data{DATA} +\def\autores{Tiago Garcia, José Fernandes} +\def\autorescontactos{(114184) tiago.rgarcia@ua.pt, (114472) jbfernandes@ua.pt} +\def\versao{VERSAO 1} +\def\departamento{Dept. de Eletrónica, Telecomunicações e Informática} +\def\empresa{Universidade de Aveiro} +% +%%%%%% CAPA %%%%%% +% +\begin{titlepage} + +\begin{center} +% +\vspace*{50mm} +% +{\Huge \titulo}\\ +% +\vspace{10mm} +% +{\Large \empresa}\\ +% +\vspace{10mm} +% +{\LARGE \autores}\\ +% +\vspace{30mm} +% +\begin{figure}[h] +\center +\includegraphics{../images/ua}\label{fig:ua-logo} +\end{figure} +% +\vspace{30mm} +\end{center} +% +\begin{flushright} +\versao +\end{flushright} +\end{titlepage} + +%% Página de Título %% +\title{% +{\Huge\textbf{\titulo}}\\ +{\Large \departamento\\ \empresa} +} +% +\author{% + \autores \\ + \autorescontactos +} +% +\date{\today} +% +\maketitle + +\pagenumbering{roman} + +\tableofcontents +\listoftables % descomentar se necessário +\listoffigures % descomentar se necessário + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\clearpage +\pagenumbering{arabic} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\chapter{Introdução} +\label{ch:introducao} + +Como projeto final da cadeira de \ac{lsd} foi-nos proposto o projeto da máquina de pão automática. + +Para tal, usamos \ac{vhdl} para simular o seu comportamento na placa FPGA Terasic DE2-115.\ Haverão 3 secções de displays, uma para o tempo do programa, outra para o tempo extra e outra para o atraso até ao ínicio da execução do programa.\ Haverá também um interruptor para selecionar o programa a ser executado, 7 interruptores para escolher o atraso inicial (introduzido em binário) e ainda 3 butões, o `Start/Stop', outro para reiniciar a máquina e o último para adicionar o possível tempo extra.\\ + +\chapter{Manual de Utilização} +\label{ch:manual-de-utilizacao} +\input{manual-de-utilizacao} + +\chapter{Arquitetura e Implementação} +\label{ch:arquitetura-e-implementacao} +\input{arquitetura-e-implementacao} + +\chapter{Validações} +\label{ch:validacoes} +No decorrer do nosso projeto fomos confrontados com diversas adversidades no que toca a simulação e validação.\ Como tal, a principal maneira de verificação foi prática e feita com a placa, já que o trabalho funciona maioritariamente em segundos, um tempo dificil de se trabalhar tanto no simulador, como na testbench. + +\chapter{Conclusões e Contribuições} +\label{ch:conclusoes-e-contribuicoes} + +\section{Conclusões} +\label{sec:conclusoes} +Após uma breve reflexão observámos que com este trabalho foram desenvolvidas novas capacidades em VHDL, lógica de estruturação (aplicada durante o planeamento das funções), otimização (de forma a simplificar o trabalho da melhor forma possivel) e ainda capacidades a nível de trabalho em grupo.\ Vimos também algumas das capacidades da placa e o potencial da disciplina, o que nos despertou interesse em saber mais e talvez desenvolver algo por conta própria.\ No geral, foram cumpridos todos os objetivos requeridos e ainda foram implementadas novas funcionalidades. + +Autoavaliamos o nosso trabalho com 18 valores. + +\section{Contribuições dos autores} +\label{sec:contribuicoes-dos-autores} +Neste projeto, ambos os elementos do grupo trabalharam de igual forma e com semelhante nível de empenho e por isso cada elemento do grupo tem uma percentagem de participação de 50\%. + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\chapter*{Acrónimos} +\begin{acronym} + \acro{ua}[UA]{Universidade de Aveiro} + \acro{leci}[LECI]{Licenciatura em Engenharia de Computadores e Informática} + \acro{lsd}[LSD]{Laboratório de Sistemas Digitais} + \acro{vhdl}[VHDL]{VHSIC Hardware Description Language} +\end{acronym} + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\printbibliography + +\end{document} diff --git a/1ano/2semestre/lsd/projects/BreadMachine/report/src/manual-de-utilizacao.tex b/1ano/2semestre/lsd/projects/BreadMachine/report/src/manual-de-utilizacao.tex new file mode 100644 index 0000000..3d3328b --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/report/src/manual-de-utilizacao.tex @@ -0,0 +1,69 @@ +\section{Programas} +\label{sec:programas} + +\begin{table}[H] + \centering + \label{tab:programas} + \begin{tabular}{|c|c|} + \hline Pão Caseiro & Pão Rústico \\ \hline + \begin{tabular}{c|c} + Fase da Fabricação & Tempo (segundos) \\ + Amassar & 10 \\ + Levedar & 4 \\ + Cozer & 10 \\ + \end{tabular} + & + \begin{tabular}{c|c} + Fase da Fabricação & Tempo (segundos) \\ + Amassar & 15 \\ + Levedar & 8 \\ + Cozer & 10 \\ + \end{tabular} \\ \hline + \end{tabular} + \caption{Programas de Pão} +\end{table} + +\section{Funcionamento} +\label{sec:funcionamento} + +A máquina inicializa permitindo o utilizador selecionar o programa a ser executado.\ Para tal, deve colocar o interruptor `Selecionador Programa' na posição do programa que deseja.\ O `Pão Caseiro' será a posição inicial do interruptor e o `Pão Rústico' será a outra posição.\ Sempre que a máquina é reiniciada estas posições são reatribuídas.\ Os programas, bem como as suas durações, são descritos em cima: Tabela~\ref{tab:programas}. + +O utilizador pode também escolher o atraso inicial a ser aplicado e, para isso, terá de usar os 7 interruptores do `Selecionador Atraso' para indicar o número, este terá de ser introduzido em binário e a máquina irá converter para decimal.\ Este valor poderá variar entre 0 e 90 segundos e qualquer valor superior a isso será interpretado como 90. + +Após a seleção do programa e do atraso inicial o utilizador poderá clicar no botão `Start/Stop' para iniciar a máquina.\ O programa irá começar assim que o atraso inicial chegar a 0.\ Poderá ver a fase em que o programa se encontra com os `LEDS Display Fase': +\begin{itemize} + \item 3 LEDS ligados $\rightarrow$ Amassar + \item 2 LEDS ligados $\rightarrow$ Levedar + \item 1 LED ligado~~~~$\rightarrow$ Cozer ou Tempo Extra + \item 0 LEDS ligados $\rightarrow$ Standby, Atraso Inicial ou Espera da Confirmação do Tempo Extra/Reinicialização +\end{itemize} + +O tempo, tanto do atraso como da programação normal poderá ser pausado e continuado em qualquer momento ao longo da sua execução. + +Após o final da programação normal o utilizador terá a possibilidade de adicionar tempo extra utilizando o botão `Tempo Extra'.\ Para iniciar o mesmo, o utilizador deverá clicar no botão `Start/Stop'.\ Tal como o atraso inicial e o tempo do programa, o tempo extra também poderá ser pausado e continuado em qualquer momento.\ Se o botão de `Start/Stop' for pressionado com o tempo extra a 0 então a máquina irá ser reiniciada.\ O utilizador pode usar o tempo extra o número de vezes que desejar. + +O `LED Display Execução' estará ligado durante a execução do programa normal e do tempo extra. + +A máquina poderá também ser reinicada em qualquer momento usando o botão `Reset'. + +\section{Esquema da Máquina} +\label{sec:esquema-da-maquina} + +\begin{figure}[H] + \center + \includegraphics[scale=.4]{../images/esquema-placa}\caption{Ilustração do Esquema da Máquina} + \label{fig:esquema-placa} +\end{figure} + +\begin{itemize} + \item \textbf{Display: Atraso Inicial} $\rightarrow$ Display para mostrar o tempo que irá decorrer antes do início da execução do programa. + \item \textbf{Display: Tempo Extra} $\rightarrow$ Display para mostrar o tempo extra do programa. + \item \textbf{Display: Tempo Programa} $\rightarrow$ Display para mostrar o tempo de execução do programa. + \item \textbf{LED: Display Execução} $\rightarrow$ LED para indicar que o programa está a ser executado. + \item \textbf{LEDS: Display Fases} $\rightarrow$ LEDS para indicar a fase do programa que está a ser executada. + \item \textbf{Switch: Selecionador Atraso} $\rightarrow$ Série de interruptores para selecionar o tempo de atraso inicial. + \item \textbf{Switch: Selecionador Programa} $\rightarrow$ Interruptor para selecionar o programa a ser executado. + \item \textbf{Botão: Reset} $\rightarrow$ Botão para reiniciar a máquina. + \item \textbf{Botão: `Start/Stop'} $\rightarrow$ Botão para iniciar ou parar a execução do programa. + \item \textbf{Botão: Tempo Extra} $\rightarrow$ Botão para adicionar tempo extra ao programa. +\end{itemize} \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/Bin7SegDecoder.vhd b/1ano/2semestre/lsd/projects/BreadMachine/src/Bin7SegDecoder.vhd new file mode 100644 index 0000000..4fde787 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/Bin7SegDecoder.vhd @@ -0,0 +1,26 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity Bin7SegDecoder is + port + ( + binInput : in std_logic_vector(3 downto 0); + enable : in std_logic; + decOut_n : out std_logic_vector(6 downto 0) + ); +end Bin7SegDecoder; + +architecture Behavioral of Bin7SegDecoder is +begin + decOut_n <= "1111111" when (enable = '0' ) else -- disabled + "1111001" when (binInput = "0001") else --1 + "0100100" when (binInput = "0010") else --2 + "0110000" when (binInput = "0011") else --3 + "0011001" when (binInput = "0100") else --4 + "0010010" when (binInput = "0101") else --5 + "0000010" when (binInput = "0110") else --6 + "1111000" when (binInput = "0111") else --7 + "0000000" when (binInput = "1000") else --8 + "0010000" when (binInput = "1001") else --9 + "1000000"; --0 +end Behavioral; diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/BinToDec.vhd b/1ano/2semestre/lsd/projects/BreadMachine/src/BinToDec.vhd new file mode 100644 index 0000000..4c4e04f --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/BinToDec.vhd @@ -0,0 +1,20 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity BinToDec is + port + ( + binIn : in std_logic_vector(6 downto 0); + decOut0 : out std_logic_vector(3 downto 0); + decOut1 : out std_logic_vector(3 downto 0) + ); +end BinToDec; + +architecture Behavioral of BinToDec is + signal s_binIn : unsigned(6 downto 0); +begin + s_binIn <= unsigned(binIn); + decOut0 <= std_logic_vector(s_binIn rem 10)(3 downto 0); + decOut1 <= std_logic_vector(s_binIn / 10)(3 downto 0); +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachine.vhd b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachine.vhd new file mode 100644 index 0000000..87e43ab --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachine.vhd @@ -0,0 +1,85 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity BreadMachine is + port + ( + CLOCK_50 : in std_logic; + KEY : in std_logic_vector(3 downto 0); + SW : in std_logic_vector(17 downto 0); + + LEDR : out std_logic_vector(0 downto 0); + LEDG : out std_logic_vector(2 downto 0); + + HEX2 : out std_logic_vector(6 downto 0); + HEX3 : out std_logic_vector(6 downto 0); + HEX4 : out std_logic_vector(6 downto 0); + HEX6 : out std_logic_vector(6 downto 0); + HEX7 : out std_logic_vector(6 downto 0) + ); +end BreadMachine; + +architecture Demo of BreadMachine is + + -- global main signals + signal s_reset : std_logic := '0'; + + -- processed signals + signal s_program, s_timeAdj, s_startStop, s_finished : std_logic; + + signal current_delay, current_time : std_logic_vector(6 downto 0); + signal s_extra_time : std_logic_vector(3 downto 0); + + signal s_display7, s_display6, s_display1, s_display0 : std_logic_vector(3 downto 0); + + signal s_phase : std_logic_vector(1 downto 0); + +begin + -- Debounces all the keys + keys_debouncer : entity work.Debouncers(Debounce) + port map + ( + clock => CLOCK_50, + + reset_btn => KEY(3), + start_stop_btn => KEY(1), + time_adjust_btn => KEY(0), + + reset_out => s_reset, + start_stop_out => s_startStop, + time_adjust_out => s_timeAdj + ); + + fsm : entity work.BreadMachineFSM(Behavioral) + port map + ( + clock => CLOCK_50, + reset => s_reset, + delayer_sw => SW(17 downto 11), + program_sw => SW(0), + time_adj_but => s_timeAdj, + start_stop_but => s_startStop, + + in_progress => LEDR(0), + leds_phase => LEDG, + + current_delay => current_delay, + current_time => current_time, + extra_time => s_extra_time + ); + + displays : entity work.DisplaysManager(Behavioral) + port map + ( + bin_delay => current_delay, + bin_total => current_time, + bin_extra => s_extra_time, + + D_HEX2 => HEX2, + D_HEX3 => HEX3, + D_HEX4 => HEX4, + D_HEX6 => HEX6, + D_HEX7 => HEX7 + ); +end Demo; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachine.vwf b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachine.vwf new file mode 100644 index 0000000..52f39f0 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachine.vwf @@ -0,0 +1,2076 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off BreadMachine -c BreadMachine --vector_source="/home/tiagorg/repos/BreadMachine/src/BreadMachine.vwf" --testbench_file="/home/tiagorg/repos/BreadMachine/src/simulation/qsim/BreadMachine.vwf.vht" +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off BreadMachine -c BreadMachine --vector_source="/home/tiagorg/repos/BreadMachine/src/BreadMachine.vwf" --testbench_file="/home/tiagorg/repos/BreadMachine/src/simulation/qsim/BreadMachine.vwf.vht" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/BreadMachine/src/simulation/qsim/" BreadMachine -c BreadMachine +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/BreadMachine/src/simulation/qsim/" BreadMachine -c BreadMachine +onerror {exit -code 1} +vlib work +vcom -work work BreadMachine.vho +vcom -work work BreadMachine.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.BreadMachine_vhd_vec_tst +vcd file -direction BreadMachine.msim.vcd +vcd add -internal BreadMachine_vhd_vec_tst/* +vcd add -internal BreadMachine_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vcom -work work BreadMachine.vho +vcom -work work BreadMachine.vwf.vht +vsim -novopt -c -t 1ps -sdfmax BreadMachine_vhd_vec_tst/i1=BreadMachine_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.BreadMachine_vhd_vec_tst +vcd file -direction BreadMachine.msim.vcd +vcd add -internal BreadMachine_vhd_vec_tst/* +vcd add -internal BreadMachine_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +vhdl +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("CLOCK_50") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("HEX2") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 7; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("HEX2[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX2"; +} + +SIGNAL("HEX2[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX2"; +} + +SIGNAL("HEX2[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX2"; +} + +SIGNAL("HEX2[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX2"; +} + +SIGNAL("HEX2[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX2"; +} + +SIGNAL("HEX2[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX2"; +} + +SIGNAL("HEX2[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX2"; +} + +SIGNAL("HEX3") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 7; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("HEX3[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX3"; +} + +SIGNAL("HEX3[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX3"; +} + +SIGNAL("HEX3[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX3"; +} + +SIGNAL("HEX3[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX3"; +} + +SIGNAL("HEX3[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX3"; +} + +SIGNAL("HEX3[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX3"; +} + +SIGNAL("HEX3[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX3"; +} + +SIGNAL("HEX4") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 7; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("HEX4[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX4"; +} + +SIGNAL("HEX4[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX4"; +} + +SIGNAL("HEX4[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX4"; +} + +SIGNAL("HEX4[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX4"; +} + +SIGNAL("HEX4[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX4"; +} + +SIGNAL("HEX4[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX4"; +} + +SIGNAL("HEX4[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX4"; +} + +SIGNAL("HEX6") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 7; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("HEX6[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX6"; +} + +SIGNAL("HEX6[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX6"; +} + +SIGNAL("HEX6[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX6"; +} + +SIGNAL("HEX6[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX6"; +} + +SIGNAL("HEX6[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX6"; +} + +SIGNAL("HEX6[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX6"; +} + +SIGNAL("HEX6[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX6"; +} + +SIGNAL("HEX7") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 7; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("HEX7[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX7"; +} + +SIGNAL("HEX7[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX7"; +} + +SIGNAL("HEX7[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX7"; +} + +SIGNAL("HEX7[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX7"; +} + +SIGNAL("HEX7[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX7"; +} + +SIGNAL("HEX7[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX7"; +} + +SIGNAL("HEX7[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "HEX7"; +} + +SIGNAL("KEY") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("KEY[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "KEY"; +} + +SIGNAL("KEY[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "KEY"; +} + +SIGNAL("KEY[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "KEY"; +} + +SIGNAL("KEY[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "KEY"; +} + +SIGNAL("LEDG") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 3; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDG[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDG"; +} + +SIGNAL("LEDG[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDG"; +} + +SIGNAL("LEDG[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "LEDG"; +} + +SIGNAL("LEDR") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDR[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 18; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[17]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[16]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[15]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[14]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("CLOCK_50") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("HEX2[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX2[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX2[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX2[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX2[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX2[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX2[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX3[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX3[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX3[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX3[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX3[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX3[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX3[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX4[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX4[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX4[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX4[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX4[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX4[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX4[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX6[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX6[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX6[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX6[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX6[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX6[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX6[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX7[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX7[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX7[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX7[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX7[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX7[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("HEX7[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("KEY[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 560.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 360.0; + } +} + +TRANSITION_LIST("KEY[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("KEY[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 960.0; + } +} + +TRANSITION_LIST("KEY[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("LEDG[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDG[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDG[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDR[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[17]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[16]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[15]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[14]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[13]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[12]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[11]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[10]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "CLOCK_50"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; + CHILDREN = 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[17]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[16]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[15]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[14]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "KEY"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 0; + CHILDREN = 21, 22, 23, 24; +} + +DISPLAY_LINE +{ + CHANNEL = "KEY[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 20; +} + +DISPLAY_LINE +{ + CHANNEL = "KEY[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 22; + TREE_LEVEL = 1; + PARENT = 20; +} + +DISPLAY_LINE +{ + CHANNEL = "KEY[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 23; + TREE_LEVEL = 1; + PARENT = 20; +} + +DISPLAY_LINE +{ + CHANNEL = "KEY[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 24; + TREE_LEVEL = 1; + PARENT = 20; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 25; + TREE_LEVEL = 0; + CHILDREN = 26, 27, 28; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 27; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 28; + TREE_LEVEL = 1; + PARENT = 25; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 29; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDR[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 30; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX2"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 31; + TREE_LEVEL = 0; + CHILDREN = 32, 33, 34, 35, 36, 37, 38; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX2[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 32; + TREE_LEVEL = 1; + PARENT = 31; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX2[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 33; + TREE_LEVEL = 1; + PARENT = 31; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX2[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 34; + TREE_LEVEL = 1; + PARENT = 31; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX2[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 35; + TREE_LEVEL = 1; + PARENT = 31; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX2[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 36; + TREE_LEVEL = 1; + PARENT = 31; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX2[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 37; + TREE_LEVEL = 1; + PARENT = 31; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX2[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 38; + TREE_LEVEL = 1; + PARENT = 31; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX3"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 39; + TREE_LEVEL = 0; + CHILDREN = 40, 41, 42, 43, 44, 45, 46; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX3[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 40; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX3[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 41; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX3[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 42; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX3[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 43; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX3[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 44; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX3[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 45; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX3[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 46; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX4"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 47; + TREE_LEVEL = 0; + CHILDREN = 48, 49, 50, 51, 52, 53, 54; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX4[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 48; + TREE_LEVEL = 1; + PARENT = 47; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX4[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 49; + TREE_LEVEL = 1; + PARENT = 47; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX4[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 50; + TREE_LEVEL = 1; + PARENT = 47; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX4[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 51; + TREE_LEVEL = 1; + PARENT = 47; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX4[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 52; + TREE_LEVEL = 1; + PARENT = 47; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX4[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 53; + TREE_LEVEL = 1; + PARENT = 47; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX4[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 54; + TREE_LEVEL = 1; + PARENT = 47; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX6"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 55; + TREE_LEVEL = 0; + CHILDREN = 56, 57, 58, 59, 60, 61, 62; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX6[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 56; + TREE_LEVEL = 1; + PARENT = 55; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX6[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 57; + TREE_LEVEL = 1; + PARENT = 55; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX6[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 58; + TREE_LEVEL = 1; + PARENT = 55; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX6[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 59; + TREE_LEVEL = 1; + PARENT = 55; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX6[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 60; + TREE_LEVEL = 1; + PARENT = 55; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX6[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 61; + TREE_LEVEL = 1; + PARENT = 55; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX6[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 62; + TREE_LEVEL = 1; + PARENT = 55; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX7"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 63; + TREE_LEVEL = 0; + CHILDREN = 64, 65, 66, 67, 68, 69, 70; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX7[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 64; + TREE_LEVEL = 1; + PARENT = 63; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX7[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 65; + TREE_LEVEL = 1; + PARENT = 63; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX7[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 66; + TREE_LEVEL = 1; + PARENT = 63; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX7[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 67; + TREE_LEVEL = 1; + PARENT = 63; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX7[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 68; + TREE_LEVEL = 1; + PARENT = 63; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX7[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 69; + TREE_LEVEL = 1; + PARENT = 63; +} + +DISPLAY_LINE +{ + CHANNEL = "HEX7[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 70; + TREE_LEVEL = 1; + PARENT = 63; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineBDF.bdf b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineBDF.bdf new file mode 100644 index 0000000..e584b06 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineBDF.bdf @@ -0,0 +1,616 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 312 336 480 352) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[17..0]" (rect 5 0 53 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 72 336 136 352)) +) +(pin + (input) + (rect 152 192 320 208) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "CLOCK_50" (rect 5 0 62 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 80 208 136 224)) +) +(pin + (input) + (rect 152 264 320 280) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "KEY[3..0]" (rect 5 0 52 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 72 280 136 296)) +) +(pin + (output) + (rect 864 232 1040 248) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDG[2..0]" (rect 90 0 144 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1056 248 1112 264)) +) +(pin + (output) + (rect 864 216 1040 232) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDR[0]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1056 232 1120 248)) +) +(pin + (output) + (rect 864 408 1040 424) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "HEX3[6..0]" (rect 116 0 170 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1144 424 1200 440)) +) +(pin + (output) + (rect 864 424 1040 440) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "HEX4[6..0]" (rect 116 0 170 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1144 440 1208 456)) +) +(pin + (output) + (rect 864 392 1040 408) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "HEX2[6..0]" (rect 116 1 170 14)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1144 408 1208 424)) +) +(pin + (output) + (rect 864 440 1040 456) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "HEX6[6..0]" (rect 117 0 171 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1144 456 1208 472)) +) +(pin + (output) + (rect 864 456 1040 472) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "HEX7[6..0]" (rect 116 0 170 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1144 472 1216 488)) +) +(symbol + (rect 368 208 592 320) + (text "Debouncers" (rect 5 0 66 11)(font "Arial" )) + (text "keys_debouncer" (rect 8 96 90 107)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 27 11)(font "Arial" )) + (text "clock" (rect 21 27 48 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "reset_btn" (rect 0 0 47 11)(font "Arial" )) + (text "reset_btn" (rect 21 43 68 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "start_stop_btn" (rect 0 0 71 11)(font "Arial" )) + (text "start_stop_btn" (rect 21 59 92 70)(font "Arial" )) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "time_adjust_btn" (rect 0 0 79 11)(font "Arial" )) + (text "time_adjust_btn" (rect 21 75 100 86)(font "Arial" )) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 224 32) + (output) + (text "reset_out" (rect 0 0 47 11)(font "Arial" )) + (text "reset_out" (rect 164 27 211 38)(font "Arial" )) + (line (pt 224 32)(pt 208 32)) + ) + (port + (pt 224 48) + (output) + (text "start_stop_out" (rect 0 0 71 11)(font "Arial" )) + (text "start_stop_out" (rect 143 43 214 54)(font "Arial" )) + (line (pt 224 48)(pt 208 48)) + ) + (port + (pt 224 64) + (output) + (text "time_adjust_out" (rect 0 0 79 11)(font "Arial" )) + (text "time_adjust_out" (rect 137 59 216 70)(font "Arial" )) + (line (pt 224 64)(pt 208 64)) + ) + (drawing + (rectangle (rect 16 16 208 96)) + ) +) +(symbol + (rect 616 192 856 336) + (text "BreadMachineFSM" (rect 5 0 99 11)(font "Arial" )) + (text "fsm" (rect 8 128 28 141)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 27 11)(font "Arial" )) + (text "clock" (rect 21 27 48 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "reset" (rect 0 0 25 11)(font "Arial" )) + (text "reset" (rect 21 43 46 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "start_stop_but" (rect 0 0 71 11)(font "Arial" )) + (text "start_stop_but" (rect 21 59 92 70)(font "Arial" )) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "time_adj_but" (rect 0 0 64 11)(font "Arial" )) + (text "time_adj_but" (rect 21 75 85 86)(font "Arial" )) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 0 96) + (input) + (text "delayer_sw[6..0]" (rect 0 0 80 11)(font "Arial" )) + (text "delayer_sw[6..0]" (rect 21 91 101 102)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "program_sw" (rect 0 0 62 11)(font "Arial" )) + (text "program_sw" (rect 21 107 83 118)(font "Arial" )) + (line (pt 0 112)(pt 16 112)) + ) + (port + (pt 240 32) + (output) + (text "in_progress" (rect 0 0 59 11)(font "Arial" )) + (text "in_progress" (rect 170 27 229 38)(font "Arial" )) + (line (pt 240 32)(pt 224 32)) + ) + (port + (pt 240 48) + (output) + (text "leds_phase[2..0]" (rect 0 0 81 11)(font "Arial" )) + (text "leds_phase[2..0]" (rect 151 43 232 54)(font "Arial" )) + (line (pt 240 48)(pt 224 48)(line_width 3)) + ) + (port + (pt 240 64) + (output) + (text "current_delay[6..0]" (rect 0 0 92 11)(font "Arial" )) + (text "current_delay[6..0]" (rect 142 59 234 70)(font "Arial" )) + (line (pt 240 64)(pt 224 64)(line_width 3)) + ) + (port + (pt 240 80) + (output) + (text "current_time[6..0]" (rect 0 0 86 11)(font "Arial" )) + (text "current_time[6..0]" (rect 147 75 233 86)(font "Arial" )) + (line (pt 240 80)(pt 224 80)(line_width 3)) + ) + (port + (pt 240 96) + (output) + (text "extra_time[3..0]" (rect 0 0 76 11)(font "Arial" )) + (text "extra_time[3..0]" (rect 155 91 231 102)(font "Arial" )) + (line (pt 240 96)(pt 224 96)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 224 128)) + ) +) +(symbol + (rect 640 368 856 512) + (text "DisplaysManager" (rect 5 0 91 11)(font "Arial" )) + (text "displays" (rect 8 128 50 141)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "bin_delay[6..0]" (rect 0 0 71 11)(font "Arial" )) + (text "bin_delay[6..0]" (rect 21 27 92 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "bin_total[6..0]" (rect 0 0 66 11)(font "Arial" )) + (text "bin_total[6..0]" (rect 21 43 87 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "bin_extra[3..0]" (rect 0 0 70 11)(font "Arial" )) + (text "bin_extra[3..0]" (rect 21 59 91 70)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 216 32) + (output) + (text "D_HEX2[6..0]" (rect 0 0 67 11)(font "Arial" )) + (text "D_HEX2[6..0]" (rect 139 27 206 38)(font "Arial" )) + (line (pt 216 32)(pt 200 32)(line_width 3)) + ) + (port + (pt 216 48) + (output) + (text "D_HEX3[6..0]" (rect 0 0 67 11)(font "Arial" )) + (text "D_HEX3[6..0]" (rect 139 43 206 54)(font "Arial" )) + (line (pt 216 48)(pt 200 48)(line_width 3)) + ) + (port + (pt 216 64) + (output) + (text "D_HEX4[6..0]" (rect 0 0 67 11)(font "Arial" )) + (text "D_HEX4[6..0]" (rect 139 59 206 70)(font "Arial" )) + (line (pt 216 64)(pt 200 64)(line_width 3)) + ) + (port + (pt 216 80) + (output) + (text "D_HEX6[6..0]" (rect 0 0 67 11)(font "Arial" )) + (text "D_HEX6[6..0]" (rect 139 75 206 86)(font "Arial" )) + (line (pt 216 80)(pt 200 80)(line_width 3)) + ) + (port + (pt 216 96) + (output) + (text "D_HEX7[6..0]" (rect 0 0 67 11)(font "Arial" )) + (text "D_HEX7[6..0]" (rect 139 91 206 102)(font "Arial" )) + (line (pt 216 96)(pt 200 96)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 200 128)) + ) +) +(connector + (pt 592 240) + (pt 616 240) +) +(connector + (pt 592 256) + (pt 616 256) +) +(connector + (pt 592 272) + (pt 616 272) +) +(connector + (pt 616 224) + (pt 608 224) +) +(connector + (pt 608 224) + (pt 608 200) +) +(connector + (pt 368 240) + (pt 360 240) +) +(connector + (pt 360 240) + (pt 360 200) +) +(connector + (text "KEY[3]" (rect 333 256 368 269)(font "Intel Clear" )) + (pt 368 256) + (pt 328 256) +) +(connector + (text "KEY[1]" (rect 333 272 368 285)(font "Intel Clear" )) + (pt 368 272) + (pt 328 272) +) +(connector + (pt 320 272) + (pt 328 272) + (bus) +) +(connector + (pt 328 256) + (pt 328 272) + (bus) +) +(connector + (pt 328 272) + (pt 328 288) + (bus) +) +(connector + (text "KEY[0]" (rect 334 288 369 301)(font "Intel Clear" )) + (pt 368 288) + (pt 328 288) +) +(connector + (pt 856 224) + (pt 864 224) +) +(connector + (pt 856 240) + (pt 864 240) + (bus) +) +(connector + (pt 856 288) + (pt 864 288) + (bus) +) +(connector + (pt 616 288) + (pt 600 288) + (bus) +) +(connector + (pt 616 304) + (pt 608 304) +) +(connector + (pt 608 304) + (pt 608 344) +) +(connector + (text "SW[0]" (rect 543 344 576 357)(font "Intel Clear" )) + (pt 608 344) + (pt 536 344) +) +(connector + (pt 600 288) + (pt 600 336) + (bus) +) +(connector + (pt 536 344) + (pt 536 336) + (bus) +) +(connector + (text "SW[17..0]" (rect 488 328 538 341)(font "Intel Clear" )) + (pt 480 344) + (pt 536 344) + (bus) +) +(connector + (pt 360 200) + (pt 608 200) +) +(connector + (pt 320 200) + (pt 360 200) +) +(connector + (text "SW[17..11]" (rect 536 320 592 333)(font "Intel Clear" )) + (pt 600 336) + (pt 536 336) + (bus) +) +(connector + (pt 856 256) + (pt 880 256) + (bus) +) +(connector + (pt 856 272) + (pt 872 272) + (bus) +) +(connector + (pt 864 400) + (pt 856 400) + (bus) +) +(connector + (pt 864 416) + (pt 856 416) + (bus) +) +(connector + (pt 864 432) + (pt 856 432) + (bus) +) +(connector + (pt 864 448) + (pt 856 448) + (bus) +) +(connector + (pt 864 464) + (pt 856 464) + (bus) +) +(connector + (pt 880 256) + (pt 880 360) + (bus) +) +(connector + (pt 880 360) + (pt 632 360) + (bus) +) +(connector + (pt 872 352) + (pt 624 352) + (bus) +) +(connector + (pt 872 272) + (pt 872 352) + (bus) +) +(connector + (pt 864 288) + (pt 864 344) + (bus) +) +(connector + (pt 864 344) + (pt 616 344) + (bus) +) +(connector + (pt 632 360) + (pt 632 400) + (bus) +) +(connector + (pt 624 352) + (pt 624 416) + (bus) +) +(connector + (pt 616 344) + (pt 616 432) + (bus) +) +(connector + (pt 640 400) + (pt 632 400) + (bus) +) +(connector + (pt 640 416) + (pt 624 416) + (bus) +) +(connector + (pt 640 432) + (pt 616 432) + (bus) +) +(junction (pt 360 200)) +(junction (pt 328 272)) +(junction (pt 536 344)) diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineFSM.bsf b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineFSM.bsf new file mode 100644 index 0000000..0331554 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineFSM.bsf @@ -0,0 +1,107 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 256 160) + (text "BreadMachineFSM" (rect 5 0 81 12)(font "Arial" )) + (text "inst" (rect 8 128 20 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 20 12)(font "Arial" )) + (text "clock" (rect 21 27 41 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "reset" (rect 0 0 20 12)(font "Arial" )) + (text "reset" (rect 21 43 41 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "start_stop_but" (rect 0 0 57 12)(font "Arial" )) + (text "start_stop_but" (rect 21 59 78 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "time_adj_but" (rect 0 0 50 12)(font "Arial" )) + (text "time_adj_but" (rect 21 75 71 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "delayer_sw[6..0]" (rect 0 0 66 12)(font "Arial" )) + (text "delayer_sw[6..0]" (rect 21 91 87 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "program_sw" (rect 0 0 50 12)(font "Arial" )) + (text "program_sw" (rect 21 107 71 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 1)) + ) + (port + (pt 240 32) + (output) + (text "in_progress" (rect 0 0 47 12)(font "Arial" )) + (text "in_progress" (rect 172 27 219 39)(font "Arial" )) + (line (pt 240 32)(pt 224 32)(line_width 1)) + ) + (port + (pt 240 48) + (output) + (text "leds_phase[2..0]" (rect 0 0 64 12)(font "Arial" )) + (text "leds_phase[2..0]" (rect 155 43 219 55)(font "Arial" )) + (line (pt 240 48)(pt 224 48)(line_width 3)) + ) + (port + (pt 240 64) + (output) + (text "current_delay[6..0]" (rect 0 0 75 12)(font "Arial" )) + (text "current_delay[6..0]" (rect 144 59 219 71)(font "Arial" )) + (line (pt 240 64)(pt 224 64)(line_width 3)) + ) + (port + (pt 240 80) + (output) + (text "current_time[6..0]" (rect 0 0 70 12)(font "Arial" )) + (text "current_time[6..0]" (rect 149 75 219 87)(font "Arial" )) + (line (pt 240 80)(pt 224 80)(line_width 3)) + ) + (port + (pt 240 96) + (output) + (text "extra_time[3..0]" (rect 0 0 62 12)(font "Arial" )) + (text "extra_time[3..0]" (rect 157 91 219 103)(font "Arial" )) + (line (pt 240 96)(pt 224 96)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 224 128)(line_width 1)) + ) +) diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineFSM.vhd b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineFSM.vhd new file mode 100644 index 0000000..63652e5 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineFSM.vhd @@ -0,0 +1,190 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity BreadMachineFSM is + port + ( + clock : in std_logic; + reset : in std_logic; + start_stop_but : in std_logic; + time_adj_but : in std_logic; + delayer_sw : in std_logic_vector(6 downto 0); + program_sw : in std_logic; + + in_progress : out std_logic; + leds_phase : out std_logic_vector(2 downto 0); + + current_delay : out std_logic_vector(6 downto 0); + current_time : out std_logic_vector(6 downto 0); + extra_time : out std_logic_vector(3 downto 0) + ); +end BreadMachineFSM; + +architecture Behavioral of BreadMachineFSM is + -- Defines the times for each phase for each program + subtype Bin6Time is std_logic_vector(6 downto 0); + type Times is array (0 to 2) of Bin6Time; + constant Program1 : Times := ("0001010", "0000100", "0001010"); + constant Program2 : Times := ("0001111", "0001000", "0001010"); + + -- Defines the current program config + signal Current_Program : Times; + signal initial_program : std_logic; + + -- General states signal + signal s_reset : std_logic := '1'; + signal s_in_progress, s_extra_time_started, s_awaiting_finish : std_logic := '0'; + + -- Current delayer signals + signal s_delay_time : Bin6Time; + signal s_current_delay : Bin6Time; + signal delayer_enable, delayer_new : std_logic := '0'; + + -- Current total time signals + signal s_total_time : Bin6Time; + signal current_total_time : Bin6Time; + signal total_time_enable, total_time_new : std_logic := '0'; + + -- Current extra time signals + signal s_extra_time : Bin6Time := "0000000"; + signal current_extra_time : Bin6Time; + signal extra_time_enable, extra_time_new : std_logic := '0'; +begin + -- Gets the total time for this program + s_total_time <= std_logic_vector(unsigned(Current_Program(0)) + unsigned(Current_Program(1)) + unsigned(Current_Program(2))); + + -- Delay timer + s_delay_time <= "1011010" when (unsigned(delayer_sw) > to_unsigned(90, 7)) else delayer_sw; + delayer : entity work.TimerModule(Behavioral) + port map + ( + clock => clock, + reset => reset, + timerEnable => delayer_enable, + timerNew => delayer_new, + timerValue => s_delay_time, + timerOut => s_current_delay + ); + + -- Total time timer + totaltimetimer : entity work.TimerModule(Behavioral) + port map + ( + clock => clock, + reset => reset, + timerEnable => total_time_enable, + timerNew => total_time_new, + timerValue => s_total_time, + timerOut => current_total_time + ); + + -- Extra time timer + extratimetimer : entity work.TimerModule(Behavioral) + port map + ( + clock => clock, + reset => reset, + timerEnable => extra_time_enable, + timerNew => extra_time_new, + timerValue => s_extra_time, + timerOut => current_extra_time + ); + + process (clock, reset, start_stop_but, time_adj_but) + begin + if (rising_edge(clock)) then + if (reset = '1' or s_reset = '1') then + Current_Program <= Program1; + initial_program <= program_sw; + s_extra_time <= "0000000"; + + delayer_enable <= '0'; + total_time_enable <= '0'; + extra_time_enable <= '0'; + + s_reset <= '0'; + s_in_progress <= '0'; + else + if (s_in_progress = '0') then + delayer_new <= '1'; + total_time_new <= '1'; + extra_time_new <= '0'; + + if (program_sw = initial_program) then + Current_Program <= Program1; + else + Current_Program <= Program2; + end if; + + if (start_stop_but = '1') then + delayer_new <= '0'; + + s_awaiting_finish <= '0'; + s_extra_time_started <= '0'; + s_in_progress <= '1'; + + delayer_enable <= '1'; + end if; + else + if (start_stop_but = '1') then + if (s_awaiting_finish = '1') then + extra_time_new <= '0'; + if (current_extra_time = "0000000") then + s_reset <= '1'; + else + s_extra_time_started <= '1'; + extra_time_enable <= '1'; + end if; + else + if (s_current_delay = "0000000") then + total_time_enable <= not total_time_enable; + extra_time_enable <= not extra_time_enable; + else + delayer_enable <= not delayer_enable; + end if; + end if; + end if; + + if (s_current_delay = "0000000" and total_time_new = '1') then + total_time_new <= '0'; + total_time_enable <= '1'; + end if; + + if (current_total_time = "0000000") then + extra_time_new <= '1'; + s_awaiting_finish <= '1'; + total_time_enable <= '0'; + end if; + + if (s_extra_time_started = '1') then + extra_time_new <= '0'; + if (current_extra_time = "0000000") then + s_extra_time <= "0000000"; + s_awaiting_finish <= '1'; + extra_time_new <= '1'; + s_extra_time_started <= '0'; + extra_time_enable <= '0'; + else + s_awaiting_finish <= '0'; + end if; + end if; + + if (current_total_time = "0000000" and unsigned(s_extra_time) < to_unsigned(5, 7) and time_adj_but = '1') then + s_extra_time <= std_logic_vector(unsigned(s_extra_time) + 1); + end if; + end if; + end if; + end if; + end process; + + extra_time <= current_extra_time(3 downto 0); + current_time <= current_total_time; + current_delay <= s_current_delay; + + in_progress <= not s_awaiting_finish when (s_current_delay = "0000000" and s_in_progress = '1') else '0'; + leds_phase <= "111" when s_current_delay = "0000000" and s_in_progress = '1' and (unsigned(current_total_time) > (unsigned(Current_Program(1)) + unsigned(Current_Program(2)))) else + "011" when s_current_delay = "0000000" and s_in_progress = '1' and (unsigned(current_total_time) > unsigned(Current_Program(2))) else + "001" when s_current_delay = "0000000" and s_in_progress = '1' and (unsigned(current_total_time) > to_unsigned(0, 7) or (s_extra_time_started = '1' and s_awaiting_finish = '0')) else + "000"; +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineFSM_TB.vhd b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineFSM_TB.vhd new file mode 100644 index 0000000..21ece4d --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachineFSM_TB.vhd @@ -0,0 +1,94 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity BreadMachineFSM_TB is +end BreadMachineFSM_TB; + +architecture Stimulus of BreadMachineFSM_TB is + -- Sinais para ligar às entradas da UUT + signal s_clock, s_reset, s_start_stop_but, s_time_adj_but, s_program_sw : std_logic; + signal s_delayer_sw : std_logic_vector(6 downto 0); + + -- Sinal para ligar às saídas da UUT + signal s_in_progress : std_logic; + signal s_leds_phase : std_logic_vector(2 downto 0); + signal s_extra_time : std_logic_vector(3 downto 0); + signal s_current_time, s_current_delay : std_logic_vector(6 downto 0); +begin + -- Instanciação da Unit Under Test (UUT) + uut: entity work.BreadMachineFSM(Behavioral) + port map + ( + clock => s_clock, + reset => s_reset, + start_stop_but => s_start_stop_but, + time_adj_but => s_time_adj_but, + delayer_sw => s_delayer_sw, + program_sw => s_program_sw, + + in_progress => s_in_progress, + leds_phase => s_leds_phase, + + current_delay => s_current_delay, + current_time => s_current_time, + extra_time => s_extra_time + ); + + clock_proc : process + begin + s_clock <= '0'; + wait for 10 ns; + s_clock <= '1'; + wait for 10 ns; + end process; + + --Process stim + stim_proc : process + begin + s_delayer_sw <= "0000010"; + wait for 1 sec; + s_program_sw <= '0'; + wait for 1 sec; + s_program_sw <= '1'; + wait for 1 sec; + s_program_sw <= '0'; + wait for 1 sec; + s_start_stop_but <= '1'; + wait for 1 sec; + s_start_stop_but <= '0'; + wait for 1 sec; + s_delayer_sw <= "1111111"; + s_time_adj_but <= '1'; + wait for 1 sec; + s_time_adj_but <= '0'; + wait for 1 sec; + s_start_stop_but <= '0'; + wait for 1 sec; + s_start_stop_but <= '1'; + wait for 10 sec; + s_start_stop_but <= '0'; + wait for 1 sec; + s_start_stop_but <= '1'; + wait for 15 sec; + s_time_adj_but <= '1'; + wait for 1 sec; + s_time_adj_but <= '0'; + wait for 1 sec; + s_time_adj_but <= '1'; + wait for 1 sec; + s_time_adj_but <= '0'; + wait for 1 sec; + s_time_adj_but <= '1'; + wait for 1 sec; + s_time_adj_but <= '0'; + wait for 1 sec; + s_start_stop_but <= '1'; + wait for 2 sec; + s_start_stop_but <= '0'; + wait for 1 sec; + s_start_stop_but <= '1'; + wait for 2 sec; + s_start_stop_but <= '1'; + end process; +end Stimulus; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachine_nativelink_simulation.rpt b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachine_nativelink_simulation.rpt new file mode 100644 index 0000000..742341d --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/BreadMachine_nativelink_simulation.rpt @@ -0,0 +1,24 @@ +Info: Start Nativelink Simulation process +Info: NativeLink has detected VHDL design -- VHDL simulation models will be used + +========= EDA Simulation Settings ===================== + +Sim Mode : RTL +Family : cycloneive +Quartus root : /home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/ +Quartus sim root : /home/tiagorg/intelFPGA_lite/20.1/quartus/eda/sim_lib +Simulation Tool : modelsim-altera +Simulation Language : vhdl +Version : 93 +Simulation Mode : GUI +Sim Output File : +Sim SDF file : +Sim dir : simulation/modelsim + +======================================================= + +Info: Starting NativeLink simulation with ModelSim-Altera software +Sourced NativeLink script /home/tiagorg/intelFPGA_lite/20.1/quartus/common/tcl/internal/nativelink/modelsim.tcl +Warning: File BreadMachine_run_msim_rtl_vhdl.do already exists - backing up current file as BreadMachine_run_msim_rtl_vhdl.do.bak7 +Info: Spawning ModelSim-Altera Simulation software +Info: NativeLink simulation flow was successful diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/Debouncer.vhd b/1ano/2semestre/lsd/projects/BreadMachine/src/Debouncer.vhd new file mode 100644 index 0000000..4ed7d3b --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/Debouncer.vhd @@ -0,0 +1,67 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity Debouncer is + generic + ( + kHzClkFreq : positive := 50_000; + mSecMinInWidth : positive := 100; + inPolarity : std_logic := '0'; + outPolarity : std_logic := '1' + ); + port + ( + refClk : in std_logic; + dirtyIn : in std_logic; + pulsedOut : out std_logic + ); +end Debouncer; + +architecture Behavioral of Debouncer is + constant MIN_IN_WIDTH_CYCLES : positive := mSecMinInWidth * kHzClkFreq; + subtype TCounter is natural range 0 to MIN_IN_WIDTH_CYCLES; + signal s_debounceCnt : TCounter := 0; + signal s_dirtyIn, s_previousIn, s_pulsedOut : std_logic; +begin + + in_sync_proc : process(refClk) + begin + if (rising_edge(refClk)) then + if (inPolarity = '1') then + s_dirtyIn <= dirtyIn; + else + s_dirtyIn <= not dirtyIn; + end if; + s_previousIn <= s_dirtyIn; + end if; + end process; + + count_proc : process(refClk) + begin + if (rising_edge(refClk)) then + if ((s_dirtyIn = '0') or + (s_debounceCnt > MIN_IN_WIDTH_CYCLES)) then + s_debounceCnt <= 0; + s_pulsedOut <= '0'; + elsif (s_dirtyIn = '1') then + if (s_previousIn = '0') then + s_debounceCnt <= MIN_IN_WIDTH_CYCLES; + s_pulsedOut <= '0'; + else + if (s_debounceCnt >= 1) then + s_debounceCnt <= s_debounceCnt - 1; + end if; + if (s_debounceCnt = 1) then + s_pulsedOut <= '1'; + else + s_pulsedOut <= '0'; + end if; + end if; + end if; + end if; + end process; + + pulsedOut <= s_pulsedOut when (outPolarity = '1') else not s_pulsedOut; + +end Behavioral; diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/Debouncers.bsf b/1ano/2semestre/lsd/projects/BreadMachine/src/Debouncers.bsf new file mode 100644 index 0000000..7da6ae9 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/Debouncers.bsf @@ -0,0 +1,79 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 240 128) + (text "Debouncers" (rect 5 0 53 12)(font "Arial" )) + (text "inst" (rect 8 96 20 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 20 12)(font "Arial" )) + (text "clock" (rect 21 27 41 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "reset_btn" (rect 0 0 37 12)(font "Arial" )) + (text "reset_btn" (rect 21 43 58 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "start_stop_btn" (rect 0 0 57 12)(font "Arial" )) + (text "start_stop_btn" (rect 21 59 78 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "time_adjust_btn" (rect 0 0 62 12)(font "Arial" )) + (text "time_adjust_btn" (rect 21 75 83 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 224 32) + (output) + (text "reset_out" (rect 0 0 37 12)(font "Arial" )) + (text "reset_out" (rect 166 27 203 39)(font "Arial" )) + (line (pt 224 32)(pt 208 32)(line_width 1)) + ) + (port + (pt 224 48) + (output) + (text "start_stop_out" (rect 0 0 57 12)(font "Arial" )) + (text "start_stop_out" (rect 146 43 203 55)(font "Arial" )) + (line (pt 224 48)(pt 208 48)(line_width 1)) + ) + (port + (pt 224 64) + (output) + (text "time_adjust_out" (rect 0 0 62 12)(font "Arial" )) + (text "time_adjust_out" (rect 141 59 203 71)(font "Arial" )) + (line (pt 224 64)(pt 208 64)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 208 96)(line_width 1)) + ) +) diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/Debouncers.vhd b/1ano/2semestre/lsd/projects/BreadMachine/src/Debouncers.vhd new file mode 100644 index 0000000..818473c --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/Debouncers.vhd @@ -0,0 +1,47 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity Debouncers is + port + ( + clock : in std_logic; + + reset_btn : in std_logic; + start_stop_btn : in std_logic; + time_adjust_btn : in std_logic; + + reset_out : out std_logic; + start_stop_out : out std_logic; + time_adjust_out : out std_logic + ); +end Debouncers; + +architecture Debounce of Debouncers is + +begin + + reset_debouncer : entity work.Debouncer(Behavioral) + port map + ( + refClk => clock, + dirtyIn => reset_btn, + pulsedOut => reset_out + ); + + timeAdjust_debouncer : entity work.Debouncer(Behavioral) + port map + ( + refClk => clock, + dirtyIn => time_adjust_btn, + pulsedOut => time_adjust_out + ); + + startStop_debouncer : entity work.Debouncer(Behavioral) + port map + ( + refClk => clock, + dirtyIn => start_stop_btn, + pulsedOut => start_stop_out + ); + +end Debounce; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/DisplaysManager.bsf b/1ano/2semestre/lsd/projects/BreadMachine/src/DisplaysManager.bsf new file mode 100644 index 0000000..92ad598 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/DisplaysManager.bsf @@ -0,0 +1,86 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 232 160) + (text "DisplaysManager" (rect 5 0 74 12)(font "Arial" )) + (text "inst" (rect 8 128 20 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "bin_delay[6..0]" (rect 0 0 57 12)(font "Arial" )) + (text "bin_delay[6..0]" (rect 21 27 78 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "bin_total[6..0]" (rect 0 0 51 12)(font "Arial" )) + (text "bin_total[6..0]" (rect 21 43 72 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "bin_extra[3..0]" (rect 0 0 56 12)(font "Arial" )) + (text "bin_extra[3..0]" (rect 21 59 77 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 216 32) + (output) + (text "D_HEX2[6..0]" (rect 0 0 57 12)(font "Arial" )) + (text "D_HEX2[6..0]" (rect 138 27 195 39)(font "Arial" )) + (line (pt 216 32)(pt 200 32)(line_width 3)) + ) + (port + (pt 216 48) + (output) + (text "D_HEX3[6..0]" (rect 0 0 57 12)(font "Arial" )) + (text "D_HEX3[6..0]" (rect 138 43 195 55)(font "Arial" )) + (line (pt 216 48)(pt 200 48)(line_width 3)) + ) + (port + (pt 216 64) + (output) + (text "D_HEX4[6..0]" (rect 0 0 59 12)(font "Arial" )) + (text "D_HEX4[6..0]" (rect 136 59 195 71)(font "Arial" )) + (line (pt 216 64)(pt 200 64)(line_width 3)) + ) + (port + (pt 216 80) + (output) + (text "D_HEX6[6..0]" (rect 0 0 57 12)(font "Arial" )) + (text "D_HEX6[6..0]" (rect 138 75 195 87)(font "Arial" )) + (line (pt 216 80)(pt 200 80)(line_width 3)) + ) + (port + (pt 216 96) + (output) + (text "D_HEX7[6..0]" (rect 0 0 57 12)(font "Arial" )) + (text "D_HEX7[6..0]" (rect 138 91 195 103)(font "Arial" )) + (line (pt 216 96)(pt 200 96)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 200 128)(line_width 1)) + ) +) diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/DisplaysManager.vhd b/1ano/2semestre/lsd/projects/BreadMachine/src/DisplaysManager.vhd new file mode 100644 index 0000000..f089ad6 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/DisplaysManager.vhd @@ -0,0 +1,79 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity DisplaysManager is + port + ( + bin_delay : in std_logic_vector(6 downto 0); + bin_total : in std_logic_vector(6 downto 0); + bin_extra : in std_logic_vector(3 downto 0); + + D_HEX2 : out std_logic_vector(6 downto 0); + D_HEX3 : out std_logic_vector(6 downto 0); + D_HEX4 : out std_logic_vector(6 downto 0); + D_HEX6 : out std_logic_vector(6 downto 0); + D_HEX7 : out std_logic_vector(6 downto 0) + ); +end DisplaysManager; + +architecture Behavioral of DisplaysManager is + + signal s_display2, s_display3, s_display6, s_display7 : std_logic_vector(3 downto 0); + +begin + binToDec_delay : entity work.BinToDec(Behavioral) + port map + ( + binIn => bin_delay, + decOut0 => s_display6, + decOut1 => s_display7 + ); + + display6 : entity work.Bin7SegDecoder(Behavioral) + port map + ( + binInput => s_display6, + enable => '1', + decOut_n => D_HEX6 + ); + + display7 : entity work.Bin7SegDecoder(Behavioral) + port map + ( + binInput => s_display7, + enable => '1', + decOut_n => D_HEX7 + ); + + binToDec_normal : entity work.BinToDec(Behavioral) + port map + ( + binIn => bin_total, + decOut0 => s_display2, + decOut1 => s_display3 + ); + + display2 : entity work.Bin7SegDecoder(Behavioral) + port map + ( + binInput => s_display2, + enable => '1', + decOut_n => D_HEX2 + ); + + display3 : entity work.Bin7SegDecoder(Behavioral) + port map + ( + binInput => s_display3, + enable => '1', + decOut_n => D_HEX3 + ); + + extra_time_display : entity work.Bin7SegDecoder(Behavioral) + port map + ( + binInput => bin_extra, + enable => '1', + decOut_n => D_HEX4 + ); +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/PulseGen.vhd b/1ano/2semestre/lsd/projects/BreadMachine/src/PulseGen.vhd new file mode 100644 index 0000000..233ccf8 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/PulseGen.vhd @@ -0,0 +1,33 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity PulseGen is + generic (MAX : positive := 50_000_000); + port + ( + clock : in STD_LOGIC; + reset : in STD_LOGIC; + pulse : out STD_LOGIC + ); +end PulseGen; + +architecture Behavioral of PulseGen is + signal s_cnt : natural range 0 to MAX-1; +begin + process(clock) + begin + if (rising_edge(clock)) then + pulse <= '0'; + if (reset = '1') then + s_cnt <= 0; + else + s_cnt <= s_cnt + 1; + if (s_cnt = MAX-1) then + s_cnt <= 0; + pulse <= '1'; + end if; + end if; + end if; + end process; +end Behavioral; diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/TimerModule.vhd b/1ano/2semestre/lsd/projects/BreadMachine/src/TimerModule.vhd new file mode 100644 index 0000000..4ab4ba2 --- /dev/null +++ b/1ano/2semestre/lsd/projects/BreadMachine/src/TimerModule.vhd @@ -0,0 +1,53 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity TimerModule is + port + ( + clock : in std_logic; + reset : in std_logic; + timerEnable : in std_logic; + timerNew : in std_logic; + timerValue : in std_logic_vector(6 downto 0); + timerOut : out std_logic_vector(6 downto 0) + ); +end TimerModule; + +architecture Behavioral of TimerModule is + + signal s_clock, s_reset, s_pulse : std_logic; + signal s_count : unsigned(6 downto 0); + +begin + s_clock <= clock; + s_reset <= reset; + + pulse_gen : entity work.PulseGen(Behavioral) + generic map (MAX => 50_000_000) + port map + ( + clock => s_clock, + reset => s_reset, + pulse => s_pulse + ); + + process(s_clock, timerNew, timerEnable) + begin + if (rising_edge(s_clock)) then + if (s_reset = '1') then + s_count <= unsigned(timerValue); + else + if ( timerNew = '1' ) then + s_count <= unsigned(timerValue); + else + if ( s_pulse = '1' and timerEnable = '1' and s_count > 0 ) then + s_count <= s_count - 1; + end if; + end if; + end if; + end if; + end process; + + timerOut <= std_logic_vector(s_count); +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/projects/BreadMachine/src/output_files/BreadMachine.sof b/1ano/2semestre/lsd/projects/BreadMachine/src/output_files/BreadMachine.sof new file mode 100644 index 0000000..de97c94 Binary files /dev/null and b/1ano/2semestre/lsd/projects/BreadMachine/src/output_files/BreadMachine.sof differ