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[LSD] compilation cache

This commit is contained in:
TiagoRG 2023-03-22 12:51:53 +00:00
parent 2de5e44e7f
commit c1976d312f
33 changed files with 85 additions and 297 deletions
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1ano/2semestre/lsd/pratica04/RegisterDemo/RegisterDemo.qws
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1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.db_info
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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016 Version_Index = 520278016
Creation_Time = Wed Mar 22 09:08:32 2023 Creation_Time = Wed Mar 22 10:17:38 2023

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1ano/2semestre/lsd/pratica04/RegisterDemo/db/RegisterDemo.tmw_info
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start_full_compilation:s:00:00:45 start_full_compilation:s
start_analysis_synthesis:s:00:00:14-start_full_compilation start_assembler:s-start_full_compilation
start_analysis_elaboration:s-start_full_compilation start_timing_analyzer:s-start_full_compilation
start_fitter:s:00:00:18-start_full_compilation start_eda_netlist_writer:s-start_full_compilation
start_assembler:s:00:00:07-start_full_compilation
start_timing_analyzer:s:00:00:04-start_full_compilation
start_eda_netlist_writer:s:00:00:02-start_full_compilation

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1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.cdf Normal file
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/* Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP4CE115F29) Path("/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/") File("CmpN_Demo.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qws
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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(0).cnf.cdb
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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(0).cnf.hdb
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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(2).cnf.cdb
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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.bpm
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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.logdb
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v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,0;26;26;0;0;26;26;0;0;0;0;0;0;8;0;0;0;18;8;0;18;0;0;8;0;26;26;26;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,26;0;0;26;26;0;0;26;26;26;26;26;26;18;26;26;26;8;18;26;8;26;26;18;26;0;0;0;26;26,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,LEDG[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LEDG[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LEDG[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LEDG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[11],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[17],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[12],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[16],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[13],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[14],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[10],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[15],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,

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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.rdb
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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.db_info
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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016 Version_Index = 520278016
Creation_Time = Mon Mar 20 13:24:17 2023 Creation_Time = Wed Mar 22 11:12:21 2023

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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hif
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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.bpm
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v1

25
1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318848866 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679483663042 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318848866 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:27:28 2023 " "Processing started: Mon Mar 20 13:27:28 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318848866 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318848866 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679483663043 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 11:14:22 2023 " "Processing started: Wed Mar 22 11:14:22 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679483663043 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679483663043 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318848866 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679483663043 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679318848987 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679483663209 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679318848987 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679483663209 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CmpN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file CmpN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CmpN-Behavioral " "Found design unit 1: CmpN-Behavioral" { } { { "CmpN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd" 18 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318853643 ""} { "Info" "ISGN_ENTITY_NAME" "1 CmpN " "Found entity 1: CmpN" { } { { "CmpN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318853643 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318853643 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CmpN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file CmpN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CmpN-Behavioral " "Found design unit 1: CmpN-Behavioral" { } { { "CmpN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd" 18 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679483669409 ""} { "Info" "ISGN_ENTITY_NAME" "1 CmpN " "Found entity 1: CmpN" { } { { "CmpN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679483669409 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679483669409 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CmpN_Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file CmpN_Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CmpN_Demo " "Found entity 1: CmpN_Demo" { } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318853643 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318853643 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CmpN_Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file CmpN_Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CmpN_Demo " "Found entity 1: CmpN_Demo" { } { { "CmpN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679483669415 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679483669415 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "CmpN_Demo " "Elaborating entity \"CmpN_Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679318853668 ""} { "Info" "ISGN_START_ELABORATION_TOP" "CmpN " "Elaborating entity \"CmpN\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679483669445 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CmpN CmpN:inst " "Elaborating entity \"CmpN\" for hierarchy \"CmpN:inst\"" { } { { "CmpN_Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 216 600 792 328 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318853671 ""} { "Error" "EVRFX_VHDL_FORMAL_HAS_NO_VALUE" "N CmpN.vhd(5) " "VHDL error at CmpN.vhd(5): formal port or parameter \"N\" must have actual or default value" { } { { "CmpN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd" 5 0 0 } } } 0 10346 "VHDL error at %2!s!: formal port or parameter \"%1!s!\" must have actual or default value" 0 0 "Analysis & Synthesis" 0 -1 1679483669445 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CmpN CmpN:inst3 " "Elaborating entity \"CmpN\" for hierarchy \"CmpN:inst3\"" { } { { "CmpN_Demo.bdf" "inst3" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf" { { 384 600 792 496 "inst3" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318853671 ""} { "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Can't elaborate top-level user hierarchy" { } { } 0 12153 "Can't elaborate top-level user hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679483669446 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1679318853980 ""} { "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "424 " "Peak virtual memory: 424 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679483669500 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Mar 22 11:14:29 2023 " "Processing ended: Wed Mar 22 11:14:29 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679483669500 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679483669500 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Total CPU time (on all processors): 00:00:18" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679483669500 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679483669500 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1679318854268 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318854268 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "42 " "Implemented 42 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Implemented 18 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679318854283 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679318854283 ""} { "Info" "ICUT_CUT_TM_LCELLS" "16 " "Implemented 16 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679318854283 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679318854283 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "434 " "Peak virtual memory: 434 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318854286 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:27:34 2023 " "Processing ended: Mon Mar 20 13:27:34 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318854286 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318854286 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318854286 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318854286 ""}

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@ -1 +0,0 @@
v1

2
1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.smart_action.txt
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@ -1 +1 @@
DONE SOURCE

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1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tmw_info
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@ -1,7 +0,0 @@
start_full_compilation:s:00:00:17
start_analysis_synthesis:s:00:00:06-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:06-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:02-start_full_compilation
start_eda_netlist_writer:s:00:00:01-start_full_compilation

51
1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.flow.rpt
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@ -1,5 +1,5 @@
Flow report for CmpN_Demo Flow report for CmpN_Demo
Mon Mar 20 13:27:44 2023 Wed Mar 22 11:14:29 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -41,22 +41,22 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+------------------------------------+---------------------------------------------+ +------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Mon Mar 20 13:27:44 2023 ; ; Flow Status ; Flow Failed - Wed Mar 22 11:14:29 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; CmpN_Demo ; ; Revision Name ; CmpN_Demo ;
; Top-level Entity Name ; CmpN_Demo ; ; Top-level Entity Name ; CmpN ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
; Device ; EP4CE115F29C7 ; ; Device ; EP4CE115F29C7 ;
; Timing Models ; Final ; ; Timing Models ; Final ;
; Total logic elements ; 16 / 114,480 ( < 1 % ) ; ; Total logic elements ; N/A until Partition Merge ;
; Total combinational functions ; 16 / 114,480 ( < 1 % ) ; ; Total combinational functions ; N/A until Partition Merge ;
; Dedicated logic registers ; 0 / 114,480 ( 0 % ) ; ; Dedicated logic registers ; N/A until Partition Merge ;
; Total registers ; 0 ; ; Total registers ; N/A until Partition Merge ;
; Total pins ; 26 / 529 ( 5 % ) ; ; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; 0 ; ; Total virtual pins ; N/A until Partition Merge ;
; Total memory bits ; 0 / 3,981,312 ( 0 % ) ; ; Total memory bits ; N/A until Partition Merge ;
; Embedded Multiplier 9-bit elements ; 0 / 532 ( 0 % ) ; ; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; 0 / 4 ( 0 % ) ; ; Total PLLs ; N/A until Partition Merge ;
+------------------------------------+---------------------------------------------+ +------------------------------------+---------------------------------------------+
@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 03/20/2023 13:27:28 ; ; Start date & time ; 03/22/2023 11:14:23 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; CmpN_Demo ; ; Revision Name ; CmpN_Demo ;
+-------------------+---------------------+ +-------------------+---------------------+
@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 198516037997543.167931884823616 ; -- ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 198516037997543.167948366314280 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@ -87,12 +87,13 @@ https://fpgasoftware.intel.com/eula.
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; ; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ; ; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; CmpN ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ; ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; CmpN ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ; ; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; CmpN ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; ; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; ; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; TOP_LEVEL_ENTITY ; CmpN ; CmpN_Demo ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
@ -101,12 +102,8 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 434 MB ; 00:00:13 ; ; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 424 MB ; 00:00:18 ;
; Fitter ; 00:00:06 ; 1.0 ; 1153 MB ; 00:00:09 ; ; Total ; 00:00:07 ; -- ; -- ; 00:00:18 ;
; Assembler ; 00:00:02 ; 1.0 ; 367 MB ; 00:00:02 ;
; Timing Analyzer ; 00:00:00 ; 1.0 ; 536 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 611 MB ; 00:00:00 ;
; Total ; 00:00:14 ; -- ; -- ; 00:00:25 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
@ -116,10 +113,6 @@ https://fpgasoftware.intel.com/eula.
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+----------------+------------+----------------+ +----------------------+------------------+----------------+------------+----------------+
; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; ; Analysis & Synthesis ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
; Fitter ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ;
+----------------------+------------------+----------------+------------+----------------+ +----------------------+------------------+----------------+------------+----------------+
@ -127,10 +120,6 @@ https://fpgasoftware.intel.com/eula.
; Flow Log ; ; Flow Log ;
------------ ------------
quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo
quartus_fit --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo
quartus_asm --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo
quartus_sta CmpN_Demo -c CmpN_Demo
quartus_eda --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo

177
1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for CmpN_Demo Analysis & Synthesis report for CmpN_Demo
Mon Mar 20 13:27:34 2023 Wed Mar 22 11:14:29 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -10,15 +10,7 @@ Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
2. Analysis & Synthesis Summary 2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings 3. Analysis & Synthesis Settings
4. Parallel Compilation 4. Parallel Compilation
5. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Messages
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. General Register Statistics
9. Parameter Settings for User Entity Instance: CmpN:inst
10. Parameter Settings for User Entity Instance: CmpN:inst3
11. Post-Synthesis Netlist Statistics for Top Partition
12. Elapsed Time Per Partition
13. Analysis & Synthesis Messages
@ -45,20 +37,20 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+ +------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Mar 20 13:27:34 2023 ; ; Analysis & Synthesis Status ; Failed - Wed Mar 22 11:14:29 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; CmpN_Demo ; ; Revision Name ; CmpN_Demo ;
; Top-level Entity Name ; CmpN_Demo ; ; Top-level Entity Name ; CmpN ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
; Total logic elements ; 16 ; ; Total logic elements ; N/A until Partition Merge ;
; Total combinational functions ; 16 ; ; Total combinational functions ; N/A until Partition Merge ;
; Dedicated logic registers ; 0 ; ; Dedicated logic registers ; N/A until Partition Merge ;
; Total registers ; 0 ; ; Total registers ; N/A until Partition Merge ;
; Total pins ; 26 ; ; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; 0 ; ; Total virtual pins ; N/A until Partition Merge ;
; Total memory bits ; 0 ; ; Total memory bits ; N/A until Partition Merge ;
; Embedded Multiplier 9-bit elements ; 0 ; ; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; 0 ; ; Total PLLs ; N/A until Partition Merge ;
+------------------------------------+---------------------------------------------+ +------------------------------------+---------------------------------------------+
@ -68,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
; Option ; Setting ; Default Value ; ; Option ; Setting ; Default Value ;
+------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------------------------------+--------------------+--------------------+
; Device ; EP4CE115F29C7 ; ; ; Device ; EP4CE115F29C7 ; ;
; Top-level entity name ; CmpN_Demo ; CmpN_Demo ; ; Top-level entity name ; CmpN ; CmpN_Demo ;
; Family name ; Cyclone IV E ; Cyclone V ; ; Family name ; Cyclone IV E ; Cyclone V ;
; Use smart compilation ; Off ; Off ; ; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
@ -164,129 +156,13 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+ +----------------------------+-------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------+---------+
; CmpN.vhd ; yes ; User VHDL File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd ; ;
; CmpN_Demo.bdf ; yes ; User Block Diagram/Schematic File ; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf ; ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------+---------+
+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+--------------+
; Resource ; Usage ;
+---------------------------------------------+--------------+
; Estimated Total logic elements ; 16 ;
; ; ;
; Total combinational functions ; 16 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 12 ;
; -- 3 input functions ; 2 ;
; -- <=2 input functions ; 2 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 16 ;
; -- arithmetic mode ; 0 ;
; ; ;
; Total registers ; 0 ;
; -- Dedicated logic registers ; 0 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 26 ;
; ; ;
; Embedded Multiplier 9-bit elements ; 0 ;
; ; ;
; Maximum fan-out node ; SW[17]~input ;
; Maximum fan-out ; 4 ;
; Total fan-out ; 92 ;
; Average fan-out ; 1.35 ;
+---------------------------------------------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+-------------+--------------+
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+-------------+--------------+
; |CmpN_Demo ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 26 ; 0 ; |CmpN_Demo ; CmpN_Demo ; work ;
; |CmpN:inst3| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CmpN_Demo|CmpN:inst3 ; CmpN ; work ;
; |CmpN:inst| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |CmpN_Demo|CmpN:inst ; CmpN ; work ;
+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------+-------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: CmpN:inst ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------+
; N ; 4 ; Signed Integer ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------+
; Parameter Settings for User Entity Instance: CmpN:inst3 ;
+----------------+-------+--------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------+
; n ; 5 ; Signed Integer ;
+----------------+-------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+-----------------------+-----------------------------+
; Type ; Count ;
+-----------------------+-----------------------------+
; boundary_port ; 26 ;
; cycloneiii_lcell_comb ; 18 ;
; normal ; 18 ;
; 1 data inputs ; 2 ;
; 2 data inputs ; 2 ;
; 3 data inputs ; 2 ;
; 4 data inputs ; 12 ;
; ; ;
; Max LUT depth ; 3.00 ;
; Average LUT depth ; 2.92 ;
+-----------------------+-----------------------------+
+-------------------------------+
; Elapsed Time Per Partition ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top ; 00:00:00 ;
+----------------+--------------+
+-------------------------------+ +-------------------------------+
; Analysis & Synthesis Messages ; ; Analysis & Synthesis Messages ;
+-------------------------------+ +-------------------------------+
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis Info: Running Quartus Prime Analysis & Synthesis
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Mon Mar 20 13:27:28 2023 Info: Processing started: Wed Mar 22 11:14:22 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CmpN_Demo -c CmpN_Demo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
@ -295,20 +171,13 @@ Info (12021): Found 2 design units, including 1 entities, in source file CmpN.vh
Info (12023): Found entity 1: CmpN File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd Line: 5 Info (12023): Found entity 1: CmpN File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd Line: 5
Info (12021): Found 1 design units, including 1 entities, in source file CmpN_Demo.bdf Info (12021): Found 1 design units, including 1 entities, in source file CmpN_Demo.bdf
Info (12023): Found entity 1: CmpN_Demo Info (12023): Found entity 1: CmpN_Demo
Info (12127): Elaborating entity "CmpN_Demo" for the top level hierarchy Info (12127): Elaborating entity "CmpN" for the top level hierarchy
Info (12128): Elaborating entity "CmpN" for hierarchy "CmpN:inst" Error (10346): VHDL error at CmpN.vhd(5): formal port or parameter "N" must have actual or default value File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd Line: 5
Info (12128): Elaborating entity "CmpN" for hierarchy "CmpN:inst3" Error (12153): Can't elaborate top-level user hierarchy
Info (286030): Timing-Driven Synthesis is running Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Error: Peak virtual memory: 424 megabytes
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL Error: Processing ended: Wed Mar 22 11:14:29 2023
Info (21057): Implemented 42 device resources after synthesis - the final resource count might be different Error: Elapsed time: 00:00:07
Info (21058): Implemented 18 input pins Error: Total CPU time (on all processors): 00:00:18
Info (21059): Implemented 8 output pins
Info (21061): Implemented 16 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 434 megabytes
Info: Processing ended: Mon Mar 20 13:27:34 2023
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:13

22
1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.map.summary
View File

@ -1,14 +1,14 @@
Analysis & Synthesis Status : Successful - Mon Mar 20 13:27:34 2023 Analysis & Synthesis Status : Failed - Wed Mar 22 11:14:29 2023
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : CmpN_Demo Revision Name : CmpN_Demo
Top-level Entity Name : CmpN_Demo Top-level Entity Name : CmpN
Family : Cyclone IV E Family : Cyclone IV E
Total logic elements : 16 Total logic elements : N/A until Partition Merge
Total combinational functions : 16 Total combinational functions : N/A until Partition Merge
Dedicated logic registers : 0 Dedicated logic registers : N/A until Partition Merge
Total registers : 0 Total registers : N/A until Partition Merge
Total pins : 26 Total pins : N/A until Partition Merge
Total virtual pins : 0 Total virtual pins : N/A until Partition Merge
Total memory bits : 0 Total memory bits : N/A until Partition Merge
Embedded Multiplier 9-bit elements : 0 Embedded Multiplier 9-bit elements : N/A until Partition Merge
Total PLLs : 0 Total PLLs : N/A until Partition Merge