diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qws b/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qws deleted file mode 100644 index 2187946..0000000 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.qws and /dev/null differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd b/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd index dee651e..74d55de 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd @@ -13,7 +13,7 @@ architecture Behavioral of FreqDivider is signal s_halfWay : unsigned(31 downto 0); signal k : std_logic_vector(31 downto 0); begin - k <= x"01AD7840"; + k <= x"02AD7840"; s_halfWay <= unsigned(k); process(clkIn) diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(3).cnf.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(3).cnf.cdb index 9255689..4937d32 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(3).cnf.cdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(3).cnf.cdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(3).cnf.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(3).cnf.hdb index ed3abe0..b59c381 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(3).cnf.hdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.(3).cnf.hdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.qmsg index df5a6f4..584d4fe 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.qmsg +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.qmsg @@ -1,7 +1,7 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679489466777 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679489466777 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 12:51:06 2023 " "Processing started: Wed Mar 22 12:51:06 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679489466777 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679489466777 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679489466777 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679489466896 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679489468340 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679489468400 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679489468583 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 12:51:08 2023 " "Processing ended: Wed Mar 22 12:51:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679489468583 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679489468583 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679489468583 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679489468583 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013329122 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013329122 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:22:09 2023 " "Processing started: Tue Mar 28 15:22:09 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013329122 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1680013329122 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1680013329122 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1680013329245 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1680013330690 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1680013330760 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013330941 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:22:10 2023 " "Processing ended: Tue Mar 28 15:22:10 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013330941 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013330941 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013330941 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1680013330941 ""} diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.rdb index 82b61dd..89034e9 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.rdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm.rdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm_labs.ddb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm_labs.ddb index ad2ecf4..316fa44 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm_labs.ddb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.asm_labs.ddb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.bpm b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.bpm index 62cd3ef..31adcc4 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.bpm and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.bpm differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.cdb index e414fdf..3143b68 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.cdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.cdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.hdb index 136ad17..95ab5f2 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.hdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.hdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.idb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.idb index cd98d7d..af2ff91 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.idb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.idb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.rdb index 438571c..ca80e8a 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.rdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.cmp.rdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.db_info b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.db_info index 6086ac1..d051e94 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.db_info +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Version_Index = 520278016 -Creation_Time = Wed Mar 22 12:53:16 2023 +Creation_Time = Tue Mar 28 15:21:18 2023 diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.eda.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.eda.qmsg index 07ad203..ff64f95 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.eda.qmsg +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.eda.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679489470445 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679489470445 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 12:51:10 2023 " "Processing started: Wed Mar 22 12:51:10 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679489470445 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679489470445 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679489470445 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1679489470596 ""} -{ "Info" "IWSC_DONE_HDL_GENERATION" "AccN_Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/ simulation " "Generated file AccN_Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1679489470629 ""} -{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679489470641 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 12:51:10 2023 " "Processing ended: Wed Mar 22 12:51:10 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679489470641 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679489470641 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679489470641 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1679489470641 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013333031 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013333031 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:22:12 2023 " "Processing started: Tue Mar 28 15:22:12 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013333031 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1680013333031 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1680013333031 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1680013333182 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "AccN_Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/ simulation " "Generated file AccN_Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1680013333223 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013333233 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:22:13 2023 " "Processing ended: Tue Mar 28 15:22:13 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013333233 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013333233 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013333233 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1680013333233 ""} diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.fit.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.fit.qmsg index 4493092..7c83203 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.fit.qmsg +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.fit.qmsg @@ -1,48 +1,48 @@ -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1679489458279 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1679489458279 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "AccN_Demo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"AccN_Demo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1679489458281 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679489458327 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1679489458327 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1679489458546 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1679489458549 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679489458578 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679489458578 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679489458578 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679489458578 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679489458578 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679489458578 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679489458578 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679489458578 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1679489458578 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1679489458578 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 787 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679489458580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 789 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679489458580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 791 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679489458580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 793 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679489458580 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 795 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1679489458580 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1679489458580 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1679489458581 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AccN_Demo.sdc " "Synopsys Design Constraints File file not found: 'AccN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1679489459083 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1679489459083 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1679489459085 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1679489459085 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1679489459085 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1679489459093 ""} } { { "AccN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 312 128 296 328 "CLOCK_50" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 782 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1679489459093 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "FreqDivider:inst2\|clkOut " "Automatically promoted node FreqDivider:inst2\|clkOut " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1679489459093 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FreqDivider:inst2\|clkOut~4 " "Destination node FreqDivider:inst2\|clkOut~4" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 7 -1 0 } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 669 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1679489459093 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1679489459093 ""} } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 7 -1 0 } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1679489459093 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1679489459208 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679489459208 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1679489459208 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679489459209 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1679489459209 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1679489459209 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1679489459209 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1679489459210 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1679489459210 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1679489459211 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1679489459211 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1679489459242 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1679489459242 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679489459249 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1679489459251 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1679489460601 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679489460675 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1679489460701 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1679489462894 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679489462894 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1679489463023 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X104_Y37 X115_Y48 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48"} { { 12 { 0 ""} 104 37 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1679489464993 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1679489464993 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1679489465370 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1679489465370 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679489465371 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1679489465441 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679489465446 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679489465594 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1679489465595 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1679489465724 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1679489465952 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1679489466121 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1679489466157 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 488 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 488 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1158 " "Peak virtual memory: 1158 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679489466278 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 12:51:06 2023 " "Processing ended: Wed Mar 22 12:51:06 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679489466278 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679489466278 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679489466278 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1679489466278 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1680013320041 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1680013320041 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "AccN_Demo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"AccN_Demo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1680013320044 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1680013320084 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1680013320084 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1680013320315 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1680013320319 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1680013320377 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1680013320377 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 785 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1680013320381 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 787 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1680013320381 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 789 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1680013320381 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 791 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1680013320381 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 793 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1680013320381 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1680013320381 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1680013320383 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AccN_Demo.sdc " "Synopsys Design Constraints File file not found: 'AccN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1680013320917 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1680013320917 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1680013320919 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1680013320919 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1680013320920 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Automatically promoted node CLOCK_50~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1680013320929 ""} } { { "AccN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 312 128 296 328 "CLOCK_50" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 780 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1680013320929 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "FreqDivider:inst2\|clkOut " "Automatically promoted node FreqDivider:inst2\|clkOut " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1680013320929 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "FreqDivider:inst2\|clkOut~4 " "Destination node FreqDivider:inst2\|clkOut~4" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 7 -1 0 } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 668 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1680013320929 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1680013320929 ""} } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 7 -1 0 } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 0 { 0 ""} 0 599 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1680013320929 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1680013321052 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1680013321052 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1680013321053 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1680013321053 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1680013321053 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1680013321054 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1680013321054 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1680013321054 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1680013321055 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1680013321055 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1680013321055 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCDAT " "Node \"AUD_ADCDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK2_50 " "Node \"CLOCK2_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK3_50 " "Node \"CLOCK3_50\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_INT_N " "Node \"ENET0_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_LINK100 " "Node \"ENET0_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDIO " "Node \"ENET0_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CLK " "Node \"ENET0_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_COL " "Node \"ENET0_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_CRS " "Node \"ENET0_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[0\] " "Node \"ENET0_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[1\] " "Node \"ENET0_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[2\] " "Node \"ENET0_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DATA\[3\] " "Node \"ENET0_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_DV " "Node \"ENET0_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RX_ER " "Node \"ENET0_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_CLK " "Node \"ENET0_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_INT_N " "Node \"ENET1_INT_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_INT_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_LINK100 " "Node \"ENET1_LINK100\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDIO " "Node \"ENET1_MDIO\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDIO" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CLK " "Node \"ENET1_RX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_COL " "Node \"ENET1_RX_COL\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_COL" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_CRS " "Node \"ENET1_RX_CRS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_CRS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[0\] " "Node \"ENET1_RX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[1\] " "Node \"ENET1_RX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[2\] " "Node \"ENET1_RX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DATA\[3\] " "Node \"ENET1_RX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_DV " "Node \"ENET1_RX_DV\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_DV" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RX_ER " "Node \"ENET1_RX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_CLK " "Node \"ENET1_TX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENETCLK_25 " "Node \"ENETCLK_25\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RY " "Node \"FL_RY\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN0 " "Node \"HSMC_CLKIN0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "IRDA_RXD " "Node \"IRDA_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[0\] " "Node \"KEY\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[2\] " "Node \"KEY\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "KEY\[3\] " "Node \"KEY\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "KEY\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[0\] " "Node \"LEDG\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_INT " "Node \"OTG_INT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_WP_N " "Node \"SD_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKIN " "Node \"SMA_CLKIN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_CLK27 " "Node \"TD_CLK27\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[0\] " "Node \"TD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[1\] " "Node \"TD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[2\] " "Node \"TD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[3\] " "Node \"TD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[4\] " "Node \"TD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[5\] " "Node \"TD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[6\] " "Node \"TD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_DATA\[7\] " "Node \"TD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_HS " "Node \"TD_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_VS " "Node \"TD_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RTS " "Node \"UART_RTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_RXD " "Node \"UART_RXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1680013321087 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1680013321087 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680013321094 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1680013321099 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1680013322456 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680013322532 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1680013322566 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1680013325163 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680013325164 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1680013325288 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X104_Y37 X115_Y48 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48"} { { 12 { 0 ""} 104 37 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1680013327218 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1680013327218 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1680013327645 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1680013327645 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680013327646 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.07 " "Total time spent on timing analysis during the Fitter is 0.07 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1680013327723 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1680013327729 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1680013327885 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1680013327885 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1680013328010 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1680013328248 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1680013328423 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1680013328462 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 488 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 488 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1160 " "Peak virtual memory: 1160 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013328595 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:22:08 2023 " "Processing ended: Tue Mar 28 15:22:08 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013328595 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013328595 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013328595 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1680013328595 ""} diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.hif b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.hif index 0ace5cf..9decd85 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.hif and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.hif differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.bpm b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.bpm index 622ddb6..6d9e8a6 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.bpm and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.bpm differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.cdb index 3f57a89..337f4dd 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.cdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.cdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.hdb index 451790c..7db9e3e 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.hdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.hdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.kpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.kpt index a8c5040..92d0555 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.kpt and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.kpt differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.qmsg index 8134f60..456acc1 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.qmsg +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.qmsg @@ -1,19 +1,19 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679489452339 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679489452339 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 12:50:52 2023 " "Processing started: Wed Mar 22 12:50:52 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679489452339 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489452339 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489452339 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679489452467 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679489452467 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FreqDivider.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FreqDivider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FreqDivider-Behavioral " "Found design unit 1: FreqDivider-Behavioral" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457065 ""} { "Info" "ISGN_ENTITY_NAME" "1 FreqDivider " "Found entity 1: FreqDivider" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457065 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457065 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AccN_Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file AccN_Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AccN_Demo " "Found entity 1: AccN_Demo" { } { { "AccN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457065 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457065 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AccN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AccN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AccN-Behavioral " "Found design unit 1: AccN-Behavioral" { } { { "AccN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457065 ""} { "Info" "ISGN_ENTITY_NAME" "1 AccN " "Found entity 1: AccN" { } { { "AccN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457065 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457065 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RegN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file RegN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RegN-Behavioral " "Found design unit 1: RegN-Behavioral" { } { { "RegN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457066 ""} { "Info" "ISGN_ENTITY_NAME" "1 RegN " "Found entity 1: RegN" { } { { "RegN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457066 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AdderN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AdderN-Behavioral " "Found design unit 1: AdderN-Behavioral" { } { { "AdderN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457066 ""} { "Info" "ISGN_ENTITY_NAME" "1 AdderN " "Found entity 1: AdderN" { } { { "AdderN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679489457066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457066 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "AccN_Demo " "Elaborating entity \"AccN_Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679489457092 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AccN AccN:inst " "Elaborating entity \"AccN\" for hierarchy \"AccN:inst\"" { } { { "AccN_Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 216 512 720 328 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679489457095 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AdderN AccN:inst\|AdderN:adder A:behavioral " "Elaborating entity \"AdderN\" using architecture \"A:behavioral\" for hierarchy \"AccN:inst\|AdderN:adder\"" { } { { "AccN.vhd" "adder" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 18 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679489457096 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "RegN AccN:inst\|RegN:reg A:behavioral " "Elaborating entity \"RegN\" using architecture \"A:behavioral\" for hierarchy \"AccN:inst\|RegN:reg\"" { } { { "AccN.vhd" "reg" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 27 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679489457096 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FreqDivider FreqDivider:inst2 " "Elaborating entity \"FreqDivider\" for hierarchy \"FreqDivider:inst2\"" { } { { "AccN_Demo.bdf" "inst2" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 288 304 448 368 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679489457097 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1679489457435 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1679489457750 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679489457750 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "114 " "Implemented 114 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679489457767 ""} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Implemented 17 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679489457767 ""} { "Info" "ICUT_CUT_TM_LCELLS" "77 " "Implemented 77 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679489457767 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679489457767 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "456 " "Peak virtual memory: 456 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679489457770 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 12:50:57 2023 " "Processing ended: Wed Mar 22 12:50:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679489457770 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679489457770 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679489457770 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679489457770 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013313781 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013313781 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:21:53 2023 " "Processing started: Tue Mar 28 15:21:53 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013313781 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013313781 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013313781 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1680013313918 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1680013313918 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FreqDivider.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FreqDivider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FreqDivider-Behavioral " "Found design unit 1: FreqDivider-Behavioral" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318577 ""} { "Info" "ISGN_ENTITY_NAME" "1 FreqDivider " "Found entity 1: FreqDivider" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/FreqDivider.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318577 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318577 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AccN_Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file AccN_Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 AccN_Demo " "Found entity 1: AccN_Demo" { } { { "AccN_Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AccN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AccN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AccN-Behavioral " "Found design unit 1: AccN-Behavioral" { } { { "AccN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} { "Info" "ISGN_ENTITY_NAME" "1 AccN " "Found entity 1: AccN" { } { { "AccN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RegN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file RegN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RegN-Behavioral " "Found design unit 1: RegN-Behavioral" { } { { "RegN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} { "Info" "ISGN_ENTITY_NAME" "1 RegN " "Found entity 1: RegN" { } { { "RegN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/RegN.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdderN.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AdderN.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AdderN-Behavioral " "Found design unit 1: AdderN-Behavioral" { } { { "AdderN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} { "Info" "ISGN_ENTITY_NAME" "1 AdderN " "Found entity 1: AdderN" { } { { "AdderN.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AdderN.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1680013318578 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013318578 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "AccN_Demo " "Elaborating entity \"AccN_Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1680013318605 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AccN AccN:inst " "Elaborating entity \"AccN\" for hierarchy \"AccN:inst\"" { } { { "AccN_Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 216 512 720 328 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318607 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AdderN AccN:inst\|AdderN:adder A:behavioral " "Elaborating entity \"AdderN\" using architecture \"A:behavioral\" for hierarchy \"AccN:inst\|AdderN:adder\"" { } { { "AccN.vhd" "adder" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 18 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318608 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "RegN AccN:inst\|RegN:reg A:behavioral " "Elaborating entity \"RegN\" using architecture \"A:behavioral\" for hierarchy \"AccN:inst\|RegN:reg\"" { } { { "AccN.vhd" "reg" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN.vhd" 27 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318608 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FreqDivider FreqDivider:inst2 " "Elaborating entity \"FreqDivider\" for hierarchy \"FreqDivider:inst2\"" { } { { "AccN_Demo.bdf" "inst2" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/AccN_Demo.bdf" { { 288 304 448 368 "inst2" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013318609 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1680013318992 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1680013319320 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1680013319320 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "112 " "Implemented 112 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "20 " "Implemented 20 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1680013319375 ""} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Implemented 17 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1680013319375 ""} { "Info" "ICUT_CUT_TM_LCELLS" "75 " "Implemented 75 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1680013319375 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1680013319375 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "453 " "Peak virtual memory: 453 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013319378 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:21:59 2023 " "Processing ended: Tue Mar 28 15:21:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013319378 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013319378 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013319378 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1680013319378 ""} diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.rdb index f0f623d..63e1f6c 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.rdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map.rdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.cdb index 0e53f14..8abfc79 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.cdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.cdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.hdb index 156d718..9093b5e 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.hdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.map_bb.hdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.pre_map.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.pre_map.hdb index 39e0da9..ec337fa 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.pre_map.hdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.pre_map.hdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.quiproj.3500.rdr.flock b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.quiproj.3500.rdr.flock new file mode 100644 index 0000000..e69de29 diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.routing.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.routing.rdb index d0c685a..56723b5 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.routing.rdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.routing.rdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv.hdb index bbe41f2..4d99fb8 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv.hdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv.hdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv_sg.cdb index 6489cee..b4e8ff4 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv_sg.cdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.rtlv_sg.cdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.qmsg b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.qmsg index 45435a8..5a8360d 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.qmsg +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.qmsg @@ -1,42 +1,42 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679489469028 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679489469028 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 22 12:51:08 2023 " "Processing started: Wed Mar 22 12:51:08 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679489469028 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469028 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta AccN_Demo -c AccN_Demo " "Command: quartus_sta AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469028 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679489469048 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679489469105 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679489469105 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469147 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469147 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AccN_Demo.sdc " "Synopsys Design Constraints File file not found: 'AccN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1679489469438 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469439 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name FreqDivider:inst2\|clkOut FreqDivider:inst2\|clkOut " "create_clock -period 1.000 -name FreqDivider:inst2\|clkOut FreqDivider:inst2\|clkOut" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1679489469439 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1679489469439 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469439 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469440 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469440 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679489469440 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1679489469443 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679489469449 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679489469449 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.190 " "Worst-case setup slack is -4.190" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.190 -78.512 CLOCK_50 " " -4.190 -78.512 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.348 -17.156 FreqDivider:inst2\|clkOut " " -1.348 -17.156 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469450 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.548 " "Worst-case hold slack is 0.548" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.548 0.000 FreqDivider:inst2\|clkOut " " 0.548 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.654 0.000 CLOCK_50 " " 0.654 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469450 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469450 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469451 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469451 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469452 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469452 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469452 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -21.845 FreqDivider:inst2\|clkOut " " -1.285 -21.845 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469452 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469452 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679489469467 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679489469479 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679489469637 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469651 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679489469653 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679489469653 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.751 " "Worst-case setup slack is -3.751" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.751 -67.496 CLOCK_50 " " -3.751 -67.496 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.082 -13.558 FreqDivider:inst2\|clkOut " " -1.082 -13.558 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469654 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469654 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.494 " "Worst-case hold slack is 0.494" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.494 0.000 FreqDivider:inst2\|clkOut " " 0.494 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469655 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.597 0.000 CLOCK_50 " " 0.597 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469655 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469655 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469656 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469657 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -21.845 FreqDivider:inst2\|clkOut " " -1.285 -21.845 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469658 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469658 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679489469674 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679489469714 ""} -{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679489469714 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679489469714 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.596 " "Worst-case setup slack is -1.596" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469716 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469716 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.596 -21.945 CLOCK_50 " " -1.596 -21.945 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469716 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.171 -0.699 FreqDivider:inst2\|clkOut " " -0.171 -0.699 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469716 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469716 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.247 " "Worst-case hold slack is 0.247" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469718 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469718 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.247 0.000 FreqDivider:inst2\|clkOut " " 0.247 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469718 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.298 0.000 CLOCK_50 " " 0.298 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469718 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469718 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469719 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679489469720 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.002 CLOCK_50 " " -3.000 -38.002 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469722 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -17.000 FreqDivider:inst2\|clkOut " " -1.000 -17.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679489469722 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679489469722 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679489469957 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679489469957 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "537 " "Peak virtual memory: 537 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679489469981 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 22 12:51:09 2023 " "Processing ended: Wed Mar 22 12:51:09 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679489469981 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679489469981 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679489469981 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679489469981 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1680013331463 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1680013331463 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 28 15:22:11 2023 " "Processing started: Tue Mar 28 15:22:11 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1680013331463 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331463 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta AccN_Demo -c AccN_Demo " "Command: quartus_sta AccN_Demo -c AccN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331463 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1680013331484 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1680013331541 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1680013331541 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331582 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331582 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AccN_Demo.sdc " "Synopsys Design Constraints File file not found: 'AccN_Demo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1680013331871 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331871 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name FreqDivider:inst2\|clkOut FreqDivider:inst2\|clkOut " "create_clock -period 1.000 -name FreqDivider:inst2\|clkOut FreqDivider:inst2\|clkOut" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1680013331871 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1680013331871 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331871 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331872 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013331872 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1680013331873 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1680013331876 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1680013331883 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1680013331883 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.308 " "Worst-case setup slack is -4.308" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.308 -65.920 CLOCK_50 " " -4.308 -65.920 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.349 -16.351 FreqDivider:inst2\|clkOut " " -1.349 -16.351 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331883 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331883 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.543 " "Worst-case hold slack is 0.543" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.543 0.000 FreqDivider:inst2\|clkOut " " 0.543 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.653 0.000 CLOCK_50 " " 0.653 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331884 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331884 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013331885 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013331885 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -21.845 FreqDivider:inst2\|clkOut " " -1.285 -21.845 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013331885 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013331885 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1680013331901 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1680013331913 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1680013332202 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013332217 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1680013332219 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1680013332219 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.850 " "Worst-case setup slack is -3.850" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.850 -55.792 CLOCK_50 " " -3.850 -55.792 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.081 -12.785 FreqDivider:inst2\|clkOut " " -1.081 -12.785 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332220 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332220 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.489 " "Worst-case hold slack is 0.489" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.489 0.000 FreqDivider:inst2\|clkOut " " 0.489 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.598 0.000 CLOCK_50 " " 0.598 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332221 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332221 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332223 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332224 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -21.845 FreqDivider:inst2\|clkOut " " -1.285 -21.845 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332225 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332225 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1680013332250 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1680013332290 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1680013332290 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1680013332290 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.676 " "Worst-case setup slack is -1.676" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.676 -16.763 CLOCK_50 " " -1.676 -16.763 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.170 -0.504 FreqDivider:inst2\|clkOut " " -0.170 -0.504 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332292 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332292 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.244 " "Worst-case hold slack is 0.244" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.244 0.000 FreqDivider:inst2\|clkOut " " 0.244 0.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.297 0.000 CLOCK_50 " " 0.297 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332294 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332294 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332295 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1680013332296 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.036 CLOCK_50 " " -3.000 -38.036 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -17.000 FreqDivider:inst2\|clkOut " " -1.000 -17.000 FreqDivider:inst2\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1680013332298 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1680013332298 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1680013332526 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1680013332526 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "537 " "Peak virtual memory: 537 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1680013332549 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 28 15:22:12 2023 " "Processing ended: Tue Mar 28 15:22:12 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1680013332549 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1680013332549 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1680013332549 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1680013332549 ""} diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.rdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.rdb index 3c78a87..24ed10f 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.rdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta.rdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta_cmp.7_slow_1200mv_85c.tdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta_cmp.7_slow_1200mv_85c.tdb index c88e992..a4fd6d9 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta_cmp.7_slow_1200mv_85c.tdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.sta_cmp.7_slow_1200mv_85c.tdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.fast_1200mv_0c.ddb index dbdc374..7c67389 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.fast_1200mv_0c.ddb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.fast_1200mv_0c.ddb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_0c.ddb index 428e066..97a1442 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_0c.ddb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_0c.ddb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_85c.ddb index cd3a2a4..4060691 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_85c.ddb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tiscmp.slow_1200mv_85c.ddb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tmw_info b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tmw_info index 1bd50f7..6862dd4 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tmw_info +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.tmw_info @@ -1,4 +1,7 @@ -start_full_compilation:s -start_assembler:s-start_full_compilation -start_timing_analyzer:s-start_full_compilation -start_eda_netlist_writer:s-start_full_compilation +start_full_compilation:s:00:00:20 +start_analysis_synthesis:s:00:00:06-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:09-start_full_compilation +start_assembler:s:00:00:02-start_full_compilation +start_timing_analyzer:s:00:00:02-start_full_compilation +start_eda_netlist_writer:s:00:00:01-start_full_compilation diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.vpr.ammdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.vpr.ammdb index 75e2867..eb44e27 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.vpr.ammdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/db/AccN_Demo.vpr.ammdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.ammdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.ammdb index b6a8b8c..2bce3d4 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.ammdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.ammdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.cdb index b5be437..f2a311a 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.cdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.cdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.hdb index 56d6930..09f6e7a 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.hdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.hdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.rcfdb index 06c0635..edd8a3e 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.rcfdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.cmp.rcfdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.cdb index 3433f18..b207d3b 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.cdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.cdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.dpi index ed824ae..9f96a0f 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.dpi and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.dpi differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.cdb index 4b09b2d..6925e92 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.cdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.cdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.hdb index f30818d..4d61c86 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.hdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hbdb.hdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hdb index 693875c..d60bc8e 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.hdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.kpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.kpt index de22dd1..2c5cc71 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.kpt and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.root_partition.map.kpt differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.rrp.hdb b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.rrp.hdb index 9bc46fd..58bb8d8 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.rrp.hdb and b/1ano/2semestre/lsd/pratica05/AccN_Demo/incremental_db/compiled_partitions/AccN_Demo.rrp.hdb differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.asm.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.asm.rpt index 6c437f5..67906fc 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.asm.rpt +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.asm.rpt @@ -1,5 +1,5 @@ Assembler report for AccN_Demo -Wed Mar 22 12:51:08 2023 +Tue Mar 28 15:22:10 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Mar 22 12:51:08 2023 ; +; Assembler Status ; Successful - Tue Mar 28 15:22:10 2023 ; ; Revision Name ; AccN_Demo ; ; Top-level Entity Name ; AccN_Demo ; ; Family ; Cyclone IV E ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+------------------------+ ; Option ; Setting ; +----------------+------------------------+ -; JTAG usercode ; 0x0056F0F9 ; -; Checksum ; 0x0056F0F9 ; +; JTAG usercode ; 0x0056E597 ; +; Checksum ; 0x0056E597 ; +----------------+------------------------+ @@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Wed Mar 22 12:51:06 2023 + Info: Processing started: Tue Mar 28 15:22:09 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Peak virtual memory: 367 megabytes - Info: Processing ended: Wed Mar 22 12:51:08 2023 - Info: Elapsed time: 00:00:02 + Info: Processing ended: Tue Mar 28 15:22:10 2023 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:02 diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.done b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.done index b137804..e94abf6 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.done +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.done @@ -1 +1 @@ -Wed Mar 22 12:51:10 2023 +Tue Mar 28 15:22:13 2023 diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.eda.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.eda.rpt index 5c0c055..d5c4514 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.eda.rpt +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for AccN_Demo -Wed Mar 22 12:51:10 2023 +Tue Mar 28 15:22:13 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Wed Mar 22 12:51:10 2023 ; +; EDA Netlist Writer Status ; Successful - Tue Mar 28 15:22:13 2023 ; ; Revision Name ; AccN_Demo ; ; Top-level Entity Name ; AccN_Demo ; ; Family ; Cyclone IV E ; @@ -81,14 +81,14 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Wed Mar 22 12:51:10 2023 + Info: Processing started: Tue Mar 28 15:22:12 2023 Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off AccN_Demo -c AccN_Demo Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file AccN_Demo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 612 megabytes - Info: Processing ended: Wed Mar 22 12:51:10 2023 - Info: Elapsed time: 00:00:00 + Info: Processing ended: Tue Mar 28 15:22:13 2023 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.rpt index 8681c61..8b4c794 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.rpt +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.rpt @@ -1,5 +1,5 @@ Fitter report for AccN_Demo -Wed Mar 22 12:51:06 2023 +Tue Mar 28 15:22:08 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -69,15 +69,15 @@ https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+---------------------------------------------+ -; Fitter Status ; Successful - Wed Mar 22 12:51:06 2023 ; +; Fitter Status ; Successful - Tue Mar 28 15:22:08 2023 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Revision Name ; AccN_Demo ; ; Top-level Entity Name ; AccN_Demo ; ; Family ; Cyclone IV E ; ; Device ; EP4CE115F29C7 ; ; Timing Models ; Final ; -; Total logic elements ; 78 / 114,480 ( < 1 % ) ; -; Total combinational functions ; 77 / 114,480 ( < 1 % ) ; +; Total logic elements ; 76 / 114,480 ( < 1 % ) ; +; Total combinational functions ; 75 / 114,480 ( < 1 % ) ; ; Dedicated logic registers ; 50 / 114,480 ( < 1 % ) ; ; Total registers ; 50 ; ; Total pins ; 37 / 529 ( 7 % ) ; @@ -662,8 +662,8 @@ https://fpgasoftware.intel.com/eula. ; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; +---------------------+--------------------+----------------------------+--------------------------+ ; Placement (by node) ; ; ; ; -; -- Requested ; 0.00 % ( 0 / 214 ) ; 0.00 % ( 0 / 214 ) ; 0.00 % ( 0 / 214 ) ; -; -- Achieved ; 0.00 % ( 0 / 214 ) ; 0.00 % ( 0 / 214 ) ; 0.00 % ( 0 / 214 ) ; +; -- Requested ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ; +; -- Achieved ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ; 0.00 % ( 0 / 212 ) ; ; ; ; ; ; ; Routing (by net) ; ; ; ; ; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; @@ -686,7 +686,7 @@ https://fpgasoftware.intel.com/eula. +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ ; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ -; Top ; 0.00 % ( 0 / 204 ) ; N/A ; Source File ; N/A ; ; +; Top ; 0.00 % ( 0 / 202 ) ; N/A ; Source File ; N/A ; ; ; hard_block:auto_generated_inst ; 0.00 % ( 0 / 10 ) ; N/A ; Source File ; N/A ; ; +--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ @@ -702,19 +702,19 @@ The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre +---------------------------------------------+------------------------+ ; Resource ; Usage ; +---------------------------------------------+------------------------+ -; Total logic elements ; 78 / 114,480 ( < 1 % ) ; -; -- Combinational with no register ; 28 ; +; Total logic elements ; 76 / 114,480 ( < 1 % ) ; +; -- Combinational with no register ; 26 ; ; -- Register only ; 1 ; ; -- Combinational with a register ; 49 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 12 ; -; -- 3 input functions ; 21 ; -; -- <=2 input functions ; 44 ; +; -- 4 input functions ; 15 ; +; -- 3 input functions ; 27 ; +; -- <=2 input functions ; 33 ; ; -- Register only ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 30 ; +; -- normal mode ; 28 ; ; -- arithmetic mode ; 47 ; ; ; ; ; Total registers* ; 50 / 117,053 ( < 1 % ) ; @@ -743,8 +743,8 @@ The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre ; Peak interconnect usage (total/H/V) ; 1.2% / 0.9% / 1.7% ; ; Maximum fan-out ; 33 ; ; Highest non-global fan-out ; 17 ; -; Total fan-out ; 394 ; -; Average fan-out ; 1.84 ; +; Total fan-out ; 401 ; +; Average fan-out ; 1.90 ; +---------------------------------------------+------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. @@ -757,19 +757,19 @@ The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre +---------------------------------------------+-----------------------+--------------------------------+ ; Difficulty Clustering Region ; Low ; Low ; ; ; ; ; -; Total logic elements ; 78 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ; -; -- Combinational with no register ; 28 ; 0 ; +; Total logic elements ; 76 / 114480 ( < 1 % ) ; 0 / 114480 ( 0 % ) ; +; -- Combinational with no register ; 26 ; 0 ; ; -- Register only ; 1 ; 0 ; ; -- Combinational with a register ; 49 ; 0 ; ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -; -- 4 input functions ; 12 ; 0 ; -; -- 3 input functions ; 21 ; 0 ; -; -- <=2 input functions ; 44 ; 0 ; +; -- 4 input functions ; 15 ; 0 ; +; -- 3 input functions ; 27 ; 0 ; +; -- <=2 input functions ; 33 ; 0 ; ; -- Register only ; 1 ; 0 ; ; ; ; ; ; Logic elements by mode ; ; ; -; -- normal mode ; 30 ; 0 ; +; -- normal mode ; 28 ; 0 ; ; -- arithmetic mode ; 47 ; 0 ; ; ; ; ; ; Total registers ; 50 ; 0 ; @@ -792,8 +792,8 @@ The pin-out file can be found in /home/tiagorg/repos/uaveiro-leci/1ano/2semestre ; -- Registered Output Connections ; 0 ; 0 ; ; ; ; ; ; Internal Connections ; ; ; -; -- Total Connections ; 389 ; 5 ; -; -- Registered Connections ; 112 ; 0 ; +; -- Total Connections ; 396 ; 5 ; +; -- Registered Connections ; 113 ; 0 ; ; ; ; ; ; External Connections ; ; ; ; -- Top ; 0 ; 0 ; @@ -1749,10 +1749,10 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------+-------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------+-------------+--------------+ -; |AccN_Demo ; 78 (0) ; 50 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; 28 (0) ; 1 (0) ; 49 (0) ; |AccN_Demo ; AccN_Demo ; work ; +; |AccN_Demo ; 76 (0) ; 50 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; 26 (0) ; 1 (0) ; 49 (0) ; |AccN_Demo ; AccN_Demo ; work ; ; |AccN:inst| ; 17 (0) ; 17 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 17 (0) ; |AccN_Demo|AccN:inst ; AccN ; work ; ; |RegN:reg| ; 17 (17) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 17 (17) ; |AccN_Demo|AccN:inst|RegN:reg ; RegN ; work ; -; |FreqDivider:inst2| ; 61 (61) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 1 (1) ; 32 (32) ; |AccN_Demo|FreqDivider:inst2 ; FreqDivider ; work ; +; |FreqDivider:inst2| ; 59 (59) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 (26) ; 1 (1) ; 32 (32) ; |AccN_Demo|FreqDivider:inst2 ; FreqDivider ; work ; +----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -1881,48 +1881,48 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------------------------------------------+-------------------+---------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+--------------------------+---------------+---------+--------------+--------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+--------------------------+---------------+---------+--------------+--------+----------------------+------------------+---------------------------+ -; CLOCK_50 ; PIN_Y2 ; 33 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ; -; FreqDivider:inst2|clkOut ; FF_X23_Y36_N3 ; 17 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ; -; KEY[1] ; PIN_M21 ; 17 ; Async. clear ; no ; -- ; -- ; -- ; -; SW[17] ; PIN_Y23 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; -+--------------------------+---------------+---------+--------------+--------+----------------------+------------------+---------------------------+ ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++--------------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++--------------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_Y2 ; 33 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ; +; FreqDivider:inst2|clkOut ; FF_X56_Y71_N23 ; 17 ; Clock ; yes ; Global Clock ; GCLK12 ; -- ; +; KEY[1] ; PIN_M21 ; 17 ; Async. clear ; no ; -- ; -- ; -- ; +; SW[17] ; PIN_Y23 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; ++--------------------------+----------------+---------+--------------+--------+----------------------+------------------+---------------------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+--------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+--------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; CLOCK_50 ; PIN_Y2 ; 33 ; 1 ; Global Clock ; GCLK4 ; -- ; -; FreqDivider:inst2|clkOut ; FF_X23_Y36_N3 ; 17 ; 7 ; Global Clock ; GCLK0 ; -- ; -+--------------------------+---------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++--------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++--------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_Y2 ; 33 ; 0 ; Global Clock ; GCLK4 ; -- ; +; FreqDivider:inst2|clkOut ; FF_X56_Y71_N23 ; 17 ; 9 ; Global Clock ; GCLK12 ; -- ; ++--------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -+------------------------------------------------+ -; Routing Usage Summary ; -+-----------------------+------------------------+ -; Routing Resource Type ; Usage ; -+-----------------------+------------------------+ -; Block interconnects ; 92 / 342,891 ( < 1 % ) ; -; C16 interconnects ; 66 / 10,120 ( < 1 % ) ; -; C4 interconnects ; 99 / 209,544 ( < 1 % ) ; -; Direct links ; 27 / 342,891 ( < 1 % ) ; -; Global clocks ; 2 / 20 ( 10 % ) ; -; Local interconnects ; 62 / 119,088 ( < 1 % ) ; -; R24 interconnects ; 42 / 9,963 ( < 1 % ) ; -; R4 interconnects ; 94 / 289,782 ( < 1 % ) ; -+-----------------------+------------------------+ ++-------------------------------------------------+ +; Routing Usage Summary ; ++-----------------------+-------------------------+ +; Routing Resource Type ; Usage ; ++-----------------------+-------------------------+ +; Block interconnects ; 89 / 342,891 ( < 1 % ) ; +; C16 interconnects ; 65 / 10,120 ( < 1 % ) ; +; C4 interconnects ; 104 / 209,544 ( < 1 % ) ; +; Direct links ; 29 / 342,891 ( < 1 % ) ; +; Global clocks ; 2 / 20 ( 10 % ) ; +; Local interconnects ; 61 / 119,088 ( < 1 % ) ; +; R24 interconnects ; 40 / 9,963 ( < 1 % ) ; +; R4 interconnects ; 92 / 289,782 ( < 1 % ) ; ++-----------------------+-------------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +---------------------------------------------+-----------------------------+ -; Number of Logic Elements (Average = 13.00) ; Number of LABs (Total = 6) ; +; Number of Logic Elements (Average = 12.67) ; Number of LABs (Total = 6) ; +---------------------------------------------+-----------------------------+ ; 1 ; 0 ; ; 2 ; 0 ; @@ -1934,12 +1934,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 8 ; 1 ; ; 9 ; 1 ; ; 10 ; 0 ; -; 11 ; 0 ; +; 11 ; 1 ; ; 12 ; 0 ; ; 13 ; 0 ; -; 14 ; 1 ; -; 15 ; 1 ; -; 16 ; 2 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 3 ; +---------------------------------------------+-----------------------------+ @@ -1957,7 +1957,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+-----------------------------+ -; Number of Signals Sourced (Average = 21.33) ; Number of LABs (Total = 6) ; +; Number of Signals Sourced (Average = 20.83) ; Number of LABs (Total = 6) ; +----------------------------------------------+-----------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -1975,10 +1975,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 13 ; 0 ; ; 14 ; 0 ; ; 15 ; 0 ; -; 16 ; 1 ; +; 16 ; 2 ; ; 17 ; 0 ; ; 18 ; 1 ; -; 19 ; 1 ; +; 19 ; 0 ; ; 20 ; 0 ; ; 21 ; 0 ; ; 22 ; 1 ; @@ -1993,7 +1993,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +--------------------------------------------------+-----------------------------+ -; Number of Signals Sourced Out (Average = 10.83) ; Number of LABs (Total = 6) ; +; Number of Signals Sourced Out (Average = 10.50) ; Number of LABs (Total = 6) ; +--------------------------------------------------+-----------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -2001,9 +2001,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 3 ; 0 ; ; 4 ; 0 ; ; 5 ; 0 ; -; 6 ; 0 ; +; 6 ; 1 ; ; 7 ; 0 ; -; 8 ; 3 ; +; 8 ; 2 ; ; 9 ; 1 ; ; 10 ; 0 ; ; 11 ; 0 ; @@ -2018,7 +2018,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+-----------------------------+ -; Number of Distinct Inputs (Average = 12.67) ; Number of LABs (Total = 6) ; +; Number of Distinct Inputs (Average = 12.33) ; Number of LABs (Total = 6) ; +----------------------------------------------+-----------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; @@ -2035,9 +2035,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; 12 ; 0 ; ; 13 ; 1 ; ; 14 ; 0 ; -; 15 ; 0 ; +; 15 ; 1 ; ; 16 ; 0 ; -; 17 ; 1 ; +; 17 ; 0 ; ; 18 ; 0 ; ; 19 ; 0 ; ; 20 ; 0 ; @@ -2198,39 +2198,39 @@ This will disable optimization of problematic paths and expose them for further +---------------------------------+--------------------------+-------------------+ ; Source Register ; Destination Register ; Delay Added in ns ; +---------------------------------+--------------------------+-------------------+ -; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 4.200 ; -; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; 1.751 ; -; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; 1.751 ; +; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 4.173 ; +; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; 1.574 ; +; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; 1.574 ; +---------------------------------+--------------------------+-------------------+ Note: This table only shows the top 33 path(s) that have the largest delay added for hold. @@ -2765,7 +2765,7 @@ Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 +Info (170192): Fitter placement operations ending: elapsed time is 00:00:03 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources Info (170196): Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X104_Y37 to location X115_Y48 @@ -2777,13 +2777,13 @@ Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 488 warnings - Info: Peak virtual memory: 1158 megabytes - Info: Processing ended: Wed Mar 22 12:51:06 2023 - Info: Elapsed time: 00:00:08 + Info: Peak virtual memory: 1160 megabytes + Info: Processing ended: Tue Mar 28 15:22:08 2023 + Info: Elapsed time: 00:00:09 Info: Total CPU time (on all processors): 00:00:14 diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.summary b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.summary index 2ed49d7..480ec20 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.summary +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.fit.summary @@ -1,12 +1,12 @@ -Fitter Status : Successful - Wed Mar 22 12:51:06 2023 +Fitter Status : Successful - Tue Mar 28 15:22:08 2023 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition Revision Name : AccN_Demo Top-level Entity Name : AccN_Demo Family : Cyclone IV E Device : EP4CE115F29C7 Timing Models : Final -Total logic elements : 78 / 114,480 ( < 1 % ) - Total combinational functions : 77 / 114,480 ( < 1 % ) +Total logic elements : 76 / 114,480 ( < 1 % ) + Total combinational functions : 75 / 114,480 ( < 1 % ) Dedicated logic registers : 50 / 114,480 ( < 1 % ) Total registers : 50 Total pins : 37 / 529 ( 7 % ) diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.flow.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.flow.rpt index 0ee2649..6a1c94a 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.flow.rpt +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.flow.rpt @@ -1,5 +1,5 @@ Flow report for AccN_Demo -Wed Mar 22 12:51:10 2023 +Tue Mar 28 15:22:13 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -41,15 +41,15 @@ https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+---------------------------------------------+ -; Flow Status ; Successful - Wed Mar 22 12:51:10 2023 ; +; Flow Status ; Successful - Tue Mar 28 15:22:13 2023 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Revision Name ; AccN_Demo ; ; Top-level Entity Name ; AccN_Demo ; ; Family ; Cyclone IV E ; ; Device ; EP4CE115F29C7 ; ; Timing Models ; Final ; -; Total logic elements ; 78 / 114,480 ( < 1 % ) ; -; Total combinational functions ; 77 / 114,480 ( < 1 % ) ; +; Total logic elements ; 76 / 114,480 ( < 1 % ) ; +; Total combinational functions ; 75 / 114,480 ( < 1 % ) ; ; Dedicated logic registers ; 50 / 114,480 ( < 1 % ) ; ; Total registers ; 50 ; ; Total pins ; 37 / 529 ( 7 % ) ; @@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/22/2023 12:50:52 ; +; Start date & time ; 03/28/2023 15:21:53 ; ; Main task ; Compilation ; ; Revision Name ; AccN_Demo ; +-------------------+---------------------+ @@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 198516037997543.167948945207130 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 198516037997543.168001331303800 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -101,12 +101,12 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 451 MB ; 00:00:13 ; -; Fitter ; 00:00:08 ; 1.0 ; 1158 MB ; 00:00:13 ; -; Assembler ; 00:00:02 ; 1.0 ; 367 MB ; 00:00:02 ; +; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 447 MB ; 00:00:13 ; +; Fitter ; 00:00:09 ; 1.0 ; 1160 MB ; 00:00:14 ; +; Assembler ; 00:00:01 ; 1.0 ; 367 MB ; 00:00:02 ; ; Timing Analyzer ; 00:00:01 ; 1.0 ; 537 MB ; 00:00:01 ; -; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:00 ; -; Total ; 00:00:16 ; -- ; -- ; 00:00:29 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:00 ; +; Total ; 00:00:18 ; -- ; -- ; 00:00:30 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.rpt index 9983832..dddc5de 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.rpt +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for AccN_Demo -Wed Mar 22 12:50:57 2023 +Tue Mar 28 15:21:59 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -46,13 +46,13 @@ https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Mar 22 12:50:57 2023 ; +; Analysis & Synthesis Status ; Successful - Tue Mar 28 15:21:59 2023 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Revision Name ; AccN_Demo ; ; Top-level Entity Name ; AccN_Demo ; ; Family ; Cyclone IV E ; -; Total logic elements ; 77 ; -; Total combinational functions ; 77 ; +; Total logic elements ; 75 ; +; Total combinational functions ; 75 ; ; Dedicated logic registers ; 50 ; ; Total registers ; 50 ; ; Total pins ; 37 ; @@ -185,16 +185,16 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------+----------------+ ; Resource ; Usage ; +---------------------------------------------+----------------+ -; Estimated Total logic elements ; 77 ; +; Estimated Total logic elements ; 75 ; ; ; ; -; Total combinational functions ; 77 ; +; Total combinational functions ; 75 ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 12 ; -; -- 3 input functions ; 21 ; -; -- <=2 input functions ; 44 ; +; -- 4 input functions ; 15 ; +; -- 3 input functions ; 27 ; +; -- <=2 input functions ; 33 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 30 ; +; -- normal mode ; 28 ; ; -- arithmetic mode ; 47 ; ; ; ; ; Total registers ; 50 ; @@ -207,8 +207,8 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Maximum fan-out node ; CLOCK_50~input ; ; Maximum fan-out ; 33 ; -; Total fan-out ; 386 ; -; Average fan-out ; 1.92 ; +; Total fan-out ; 394 ; +; Average fan-out ; 1.98 ; +---------------------------------------------+----------------+ @@ -217,10 +217,10 @@ https://fpgasoftware.intel.com/eula. +----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+-------------+--------------+ ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; +----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+-------------+--------------+ -; |AccN_Demo ; 77 (0) ; 50 (0) ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; |AccN_Demo ; AccN_Demo ; work ; +; |AccN_Demo ; 75 (0) ; 50 (0) ; 0 ; 0 ; 0 ; 0 ; 37 ; 0 ; |AccN_Demo ; AccN_Demo ; work ; ; |AccN:inst| ; 17 (0) ; 17 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|AccN:inst ; AccN ; work ; ; |RegN:reg| ; 17 (17) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|AccN:inst|RegN:reg ; RegN ; work ; -; |FreqDivider:inst2| ; 60 (60) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|FreqDivider:inst2 ; FreqDivider ; work ; +; |FreqDivider:inst2| ; 58 (58) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |AccN_Demo|FreqDivider:inst2 ; FreqDivider ; work ; +----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -279,18 +279,18 @@ Note: In order to hide this table in the UI and the text report file, please set ; cycloneiii_ff ; 50 ; ; ENA CLR ; 17 ; ; plain ; 33 ; -; cycloneiii_lcell_comb ; 77 ; +; cycloneiii_lcell_comb ; 75 ; ; arith ; 47 ; ; 2 data inputs ; 31 ; ; 3 data inputs ; 16 ; -; normal ; 30 ; +; normal ; 28 ; ; 1 data inputs ; 1 ; -; 2 data inputs ; 12 ; -; 3 data inputs ; 5 ; -; 4 data inputs ; 12 ; +; 2 data inputs ; 1 ; +; 3 data inputs ; 11 ; +; 4 data inputs ; 15 ; ; ; ; -; Max LUT depth ; 4.40 ; -; Average LUT depth ; 3.08 ; +; Max LUT depth ; 4.50 ; +; Average LUT depth ; 3.02 ; +-----------------------+-----------------------------+ @@ -309,7 +309,7 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Wed Mar 22 12:50:52 2023 + Info: Processing started: Tue Mar 28 15:21:53 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AccN_Demo -c AccN_Demo Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected @@ -335,14 +335,14 @@ Info (12128): Elaborating entity "FreqDivider" for hierarchy "FreqDivider:inst2" Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL -Info (21057): Implemented 114 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 112 device resources after synthesis - the final resource count might be different Info (21058): Implemented 20 input pins Info (21059): Implemented 17 output pins - Info (21061): Implemented 77 logic cells + Info (21061): Implemented 75 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning - Info: Peak virtual memory: 456 megabytes - Info: Processing ended: Wed Mar 22 12:50:57 2023 - Info: Elapsed time: 00:00:05 + Info: Peak virtual memory: 453 megabytes + Info: Processing ended: Tue Mar 28 15:21:59 2023 + Info: Elapsed time: 00:00:06 Info: Total CPU time (on all processors): 00:00:13 diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.summary b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.summary index a7d0365..af4a45a 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.summary +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.map.summary @@ -1,10 +1,10 @@ -Analysis & Synthesis Status : Successful - Wed Mar 22 12:50:57 2023 +Analysis & Synthesis Status : Successful - Tue Mar 28 15:21:59 2023 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition Revision Name : AccN_Demo Top-level Entity Name : AccN_Demo Family : Cyclone IV E -Total logic elements : 77 - Total combinational functions : 77 +Total logic elements : 75 + Total combinational functions : 75 Dedicated logic registers : 50 Total registers : 50 Total pins : 37 diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof index b9be371..100e4ae 100644 Binary files a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof and b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sof differ diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.rpt b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.rpt index 9c09c67..1efe068 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.rpt +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for AccN_Demo -Wed Mar 22 12:51:09 2023 +Tue Mar 28 15:22:12 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -130,8 +130,8 @@ https://fpgasoftware.intel.com/eula. +------------+-----------------+--------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+--------------------------+------+ -; 192.68 MHz ; 192.68 MHz ; CLOCK_50 ; ; -; 425.89 MHz ; 425.89 MHz ; FreqDivider:inst2|clkOut ; ; +; 188.39 MHz ; 188.39 MHz ; CLOCK_50 ; ; +; 425.71 MHz ; 425.71 MHz ; FreqDivider:inst2|clkOut ; ; +------------+-----------------+--------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -147,8 +147,8 @@ HTML report is unavailable in plain text report export. +--------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+--------+---------------+ -; CLOCK_50 ; -4.190 ; -78.512 ; -; FreqDivider:inst2|clkOut ; -1.348 ; -17.156 ; +; CLOCK_50 ; -4.308 ; -65.920 ; +; FreqDivider:inst2|clkOut ; -1.349 ; -16.351 ; +--------------------------+--------+---------------+ @@ -157,8 +157,8 @@ HTML report is unavailable in plain text report export. +--------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+-------+---------------+ -; FreqDivider:inst2|clkOut ; 0.548 ; 0.000 ; -; CLOCK_50 ; 0.654 ; 0.000 ; +; FreqDivider:inst2|clkOut ; 0.543 ; 0.000 ; +; CLOCK_50 ; 0.653 ; 0.000 ; +--------------------------+-------+---------------+ @@ -189,106 +189,106 @@ No paths to report. +--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ -; -4.190 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.077 ; 5.111 ; -; -4.160 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.077 ; 5.081 ; -; -4.138 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.077 ; 5.059 ; -; -4.120 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.077 ; 5.041 ; -; -4.100 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 5.020 ; -; -4.099 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 5.019 ; -; -4.017 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.077 ; 4.938 ; -; -4.003 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.077 ; 4.924 ; -; -3.991 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.910 ; -; -3.984 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 4.904 ; -; -3.983 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.902 ; -; -3.974 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.893 ; -; -3.868 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.077 ; 4.789 ; -; -3.846 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.077 ; 4.767 ; -; -3.824 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 4.744 ; -; -3.777 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.696 ; -; -3.774 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.077 ; 4.695 ; -; -3.755 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 4.675 ; -; -3.744 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.077 ; 4.665 ; -; -3.732 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 4.651 ; -; -3.612 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.529 ; -; -3.607 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 4.527 ; -; -3.600 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.517 ; -; -3.598 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.515 ; -; -3.590 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 4.510 ; -; -3.505 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 4.425 ; -; -3.493 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.410 ; -; -3.466 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 4.386 ; -; -3.459 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.510 ; 3.947 ; -; -3.332 ; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.249 ; -; -3.217 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.134 ; -; -3.154 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.511 ; 3.641 ; -; -3.146 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 4.066 ; -; -3.129 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.511 ; 3.616 ; -; -3.127 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.513 ; 3.612 ; -; -3.116 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.510 ; 3.604 ; -; -3.066 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.510 ; 3.554 ; -; -3.025 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.513 ; 3.510 ; -; -2.995 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.513 ; 3.480 ; -; -2.968 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.888 ; -; -2.926 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.846 ; -; -2.924 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.844 ; -; -2.896 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.816 ; -; -2.893 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.513 ; 3.378 ; -; -2.863 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.511 ; 3.350 ; -; -2.863 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.513 ; 3.348 ; -; -2.854 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.511 ; 3.341 ; -; -2.835 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.755 ; -; -2.827 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.746 ; -; -2.825 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.744 ; -; -2.818 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.737 ; -; -2.816 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.735 ; -; -2.812 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.731 ; -; -2.804 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.721 ; -; -2.801 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.511 ; 3.288 ; -; -2.765 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.685 ; -; -2.761 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.513 ; 3.246 ; -; -2.753 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.673 ; -; -2.751 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.671 ; -; -2.731 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.513 ; 3.216 ; -; -2.724 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.644 ; -; -2.720 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.640 ; -; -2.720 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.639 ; -; -2.719 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.639 ; -; -2.718 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.637 ; -; -2.716 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.510 ; 3.204 ; -; -2.712 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.632 ; -; -2.709 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.627 ; -; -2.707 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.625 ; -; -2.703 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.623 ; -; -2.701 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.619 ; -; -2.699 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.617 ; -; -2.692 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.610 ; -; -2.690 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.608 ; -; -2.683 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.600 ; -; -2.679 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.598 ; -; -2.675 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.595 ; -; -2.673 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.592 ; -; -2.673 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.593 ; -; -2.664 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.581 ; -; -2.653 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.573 ; -; -2.651 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.571 ; -; -2.635 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.555 ; -; -2.633 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.553 ; -; -2.624 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.543 ; -; -2.623 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.542 ; -; -2.622 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.541 ; -; -2.621 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.540 ; -; -2.614 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.533 ; -; -2.613 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.532 ; -; -2.591 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.510 ; -; -2.591 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.511 ; -; -2.575 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.494 ; -; -2.575 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.495 ; -; -2.566 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.079 ; 3.485 ; -; -2.564 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.481 ; -; -2.551 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.468 ; -; -2.550 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 3.467 ; -; -2.547 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.467 ; -; -2.546 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.078 ; 3.466 ; +; -4.308 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 5.223 ; +; -4.298 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 5.213 ; +; -4.283 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.201 ; +; -4.274 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.192 ; +; -4.258 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.176 ; +; -4.178 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.096 ; +; -4.175 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 5.093 ; +; -4.162 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 5.076 ; +; -4.155 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 5.069 ; +; -4.055 ; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 4.969 ; +; -4.051 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.966 ; +; -4.048 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 4.962 ; +; -4.026 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.944 ; +; -3.936 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.851 ; +; -3.922 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.837 ; +; -3.902 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 4.816 ; +; -3.899 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.814 ; +; -3.824 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.739 ; +; -3.787 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.705 ; +; -3.621 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.538 ; +; -3.509 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.427 ; +; -3.491 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.408 ; +; -3.467 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.382 ; +; -3.376 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.294 ; +; -3.347 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.264 ; +; -3.336 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 4.254 ; +; -3.316 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.231 ; +; -3.278 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.193 ; +; -3.194 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.111 ; +; -3.137 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 4.052 ; +; -3.107 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.024 ; +; -3.096 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.081 ; 4.013 ; +; -2.825 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.740 ; +; -2.769 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.684 ; +; -2.698 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.612 ; +; -2.698 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.613 ; +; -2.694 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.609 ; +; -2.687 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.601 ; +; -2.681 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.599 ; +; -2.668 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.582 ; +; -2.647 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.561 ; +; -2.635 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.550 ; +; -2.631 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.546 ; +; -2.596 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.511 ; +; -2.596 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.511 ; +; -2.596 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.510 ; +; -2.594 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.509 ; +; -2.590 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.505 ; +; -2.590 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.508 ; +; -2.586 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.501 ; +; -2.584 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.499 ; +; -2.584 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.499 ; +; -2.571 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.489 ; +; -2.571 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.489 ; +; -2.569 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.487 ; +; -2.567 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.481 ; +; -2.567 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.482 ; +; -2.566 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.480 ; +; -2.566 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.484 ; +; -2.566 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.484 ; +; -2.564 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.482 ; +; -2.562 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.477 ; +; -2.562 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.480 ; +; -2.562 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.480 ; +; -2.560 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.478 ; +; -2.555 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.469 ; +; -2.553 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.467 ; +; -2.547 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.465 ; +; -2.536 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.450 ; +; -2.534 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.448 ; +; -2.526 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.441 ; +; -2.524 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.439 ; +; -2.520 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.085 ; 3.433 ; +; -2.520 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.434 ; +; -2.503 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.418 ; +; -2.499 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.414 ; +; -2.479 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.397 ; +; -2.479 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.397 ; +; -2.477 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.395 ; +; -2.466 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.384 ; +; -2.466 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.384 ; +; -2.465 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.379 ; +; -2.464 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.382 ; +; -2.464 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.378 ; +; -2.459 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.080 ; 3.377 ; +; -2.456 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.371 ; +; -2.453 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.368 ; +; -2.450 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.364 ; +; -2.450 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.364 ; +; -2.448 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.362 ; +; -2.443 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.357 ; +; -2.443 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.357 ; +; -2.442 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.357 ; +; -2.441 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.355 ; +; -2.436 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.350 ; +; -2.435 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.349 ; +; -2.434 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.348 ; +; -2.431 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.083 ; 3.346 ; +; -2.423 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.337 ; +; -2.421 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.084 ; 3.335 ; +--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ @@ -297,106 +297,106 @@ No paths to report. +--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ -; -1.348 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.679 ; -; -1.259 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.590 ; -; -1.243 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 2.163 ; -; -1.231 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 2.151 ; -; -1.228 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.559 ; -; -1.216 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.547 ; -; -1.213 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.544 ; -; -1.212 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 2.132 ; -; -1.197 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.528 ; -; -1.142 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 2.062 ; -; -1.127 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.458 ; -; -1.126 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.457 ; -; -1.115 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 2.017 ; -; -1.112 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 2.031 ; -; -1.111 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 2.031 ; -; -1.100 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 2.019 ; -; -1.096 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.427 ; -; -1.096 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 2.016 ; -; -1.096 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.427 ; -; -1.084 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.415 ; -; -1.081 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.412 ; -; -1.081 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.412 ; -; -1.081 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 2.000 ; -; -1.077 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 1.997 ; -; -1.065 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.396 ; -; -1.062 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.393 ; -; -1.027 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.929 ; -; -1.011 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.930 ; -; -1.009 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 1.929 ; -; -0.997 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.899 ; -; -0.995 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.326 ; -; -0.994 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.325 ; -; -0.994 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.325 ; -; -0.983 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.885 ; -; -0.983 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.885 ; -; -0.980 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.899 ; -; -0.980 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.899 ; -; -0.979 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 1.899 ; -; -0.968 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.887 ; -; -0.965 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.884 ; -; -0.964 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.295 ; -; -0.964 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 1.884 ; -; -0.964 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.295 ; -; -0.964 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.866 ; -; -0.964 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.295 ; -; -0.952 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.283 ; -; -0.949 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.280 ; -; -0.949 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.280 ; -; -0.949 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.868 ; -; -0.948 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.279 ; -; -0.946 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.865 ; -; -0.945 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 1.865 ; -; -0.933 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.264 ; -; -0.930 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.261 ; -; -0.930 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.261 ; -; -0.896 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.798 ; -; -0.895 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.797 ; -; -0.879 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.798 ; -; -0.878 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.797 ; -; -0.877 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 1.797 ; -; -0.865 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.767 ; -; -0.865 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.767 ; -; -0.863 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.194 ; -; -0.862 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.193 ; -; -0.862 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.193 ; -; -0.861 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.192 ; -; -0.855 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.757 ; -; -0.851 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.753 ; -; -0.851 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.753 ; -; -0.848 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.767 ; -; -0.848 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.767 ; -; -0.848 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.767 ; -; -0.846 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 1.766 ; -; -0.836 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.755 ; -; -0.833 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.752 ; -; -0.833 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.752 ; -; -0.832 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.734 ; -; -0.832 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.163 ; -; -0.832 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.734 ; -; -0.832 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.163 ; -; -0.831 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 1.751 ; -; -0.831 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.162 ; -; -0.821 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.331 ; 2.150 ; -; -0.817 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.148 ; -; -0.817 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.148 ; -; -0.817 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.736 ; -; -0.816 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.147 ; -; -0.814 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.733 ; -; -0.814 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.733 ; -; -0.812 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 1.732 ; -; -0.798 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.129 ; -; -0.798 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.129 ; -; -0.797 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.333 ; 2.128 ; -; -0.770 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.672 ; -; -0.764 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.666 ; -; -0.763 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.096 ; 1.665 ; -; -0.747 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.666 ; -; -0.746 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.665 ; -; -0.746 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.079 ; 1.665 ; -; -0.744 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.078 ; 1.664 ; +; -1.349 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.679 ; +; -1.260 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.590 ; +; -1.250 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 2.150 ; +; -1.229 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.559 ; +; -1.217 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.547 ; +; -1.214 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.544 ; +; -1.198 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.528 ; +; -1.160 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 2.060 ; +; -1.130 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 2.030 ; +; -1.128 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.458 ; +; -1.127 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.457 ; +; -1.118 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 2.018 ; +; -1.117 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 2.017 ; +; -1.113 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 2.031 ; +; -1.101 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 2.019 ; +; -1.099 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.999 ; +; -1.097 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.427 ; +; -1.097 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.427 ; +; -1.085 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.415 ; +; -1.082 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.412 ; +; -1.082 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.412 ; +; -1.082 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 2.000 ; +; -1.066 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.396 ; +; -1.063 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.393 ; +; -1.029 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.929 ; +; -1.028 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.928 ; +; -1.012 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.930 ; +; -0.999 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.899 ; +; -0.998 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.898 ; +; -0.996 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.326 ; +; -0.995 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.325 ; +; -0.995 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.325 ; +; -0.986 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.886 ; +; -0.985 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.885 ; +; -0.985 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.885 ; +; -0.981 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.899 ; +; -0.981 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.899 ; +; -0.969 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.887 ; +; -0.967 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.867 ; +; -0.966 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.866 ; +; -0.966 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.884 ; +; -0.965 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.295 ; +; -0.965 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.295 ; +; -0.965 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.295 ; +; -0.953 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.283 ; +; -0.950 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.280 ; +; -0.950 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.280 ; +; -0.950 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.868 ; +; -0.949 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.279 ; +; -0.947 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.865 ; +; -0.934 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.264 ; +; -0.931 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.261 ; +; -0.931 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.261 ; +; -0.898 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.798 ; +; -0.897 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.797 ; +; -0.896 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.796 ; +; -0.880 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.798 ; +; -0.879 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.797 ; +; -0.867 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.767 ; +; -0.867 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.767 ; +; -0.866 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.766 ; +; -0.864 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.194 ; +; -0.863 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.193 ; +; -0.863 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.193 ; +; -0.862 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.192 ; +; -0.857 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.757 ; +; -0.854 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.754 ; +; -0.853 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.753 ; +; -0.853 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.753 ; +; -0.849 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.767 ; +; -0.849 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.767 ; +; -0.849 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.767 ; +; -0.837 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.755 ; +; -0.835 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.735 ; +; -0.834 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.734 ; +; -0.834 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.752 ; +; -0.834 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.734 ; +; -0.834 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.752 ; +; -0.833 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.163 ; +; -0.833 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.163 ; +; -0.833 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.163 ; +; -0.832 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.162 ; +; -0.821 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.151 ; +; -0.818 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.148 ; +; -0.818 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.148 ; +; -0.818 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.736 ; +; -0.817 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.147 ; +; -0.815 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.733 ; +; -0.815 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.733 ; +; -0.802 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.132 ; +; -0.799 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.129 ; +; -0.799 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.129 ; +; -0.798 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.332 ; 2.128 ; +; -0.772 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.672 ; +; -0.766 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.666 ; +; -0.765 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.665 ; +; -0.764 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.098 ; 1.664 ; +; -0.748 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.666 ; +; -0.747 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.665 ; +; -0.747 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.080 ; 1.665 ; +--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ @@ -405,106 +405,106 @@ No paths to report. +-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ -; 0.548 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.241 ; -; 0.565 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.258 ; -; 0.641 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 0.923 ; -; 0.642 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 0.924 ; -; 0.642 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 0.924 ; -; 0.643 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 0.925 ; -; 0.643 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 0.925 ; -; 0.646 ; AccN:inst|RegN:reg|dataOut[16] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 0.928 ; -; 0.647 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 0.929 ; -; 0.657 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.923 ; -; 0.658 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 0.923 ; -; 0.659 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 0.924 ; -; 0.659 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 0.924 ; -; 0.659 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 0.924 ; -; 0.659 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 0.924 ; -; 0.660 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 0.925 ; -; 0.661 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.927 ; -; 0.663 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 0.928 ; -; 0.669 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.362 ; -; 0.671 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.365 ; -; 0.674 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.367 ; -; 0.677 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[0] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 0.942 ; -; 0.686 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.379 ; -; 0.691 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.385 ; -; 0.691 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.384 ; -; 0.792 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.486 ; -; 0.795 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.488 ; -; 0.797 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.491 ; -; 0.798 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.492 ; -; 0.800 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.493 ; -; 0.812 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.506 ; -; 0.812 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.505 ; -; 0.817 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.511 ; -; 0.817 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.511 ; -; 0.817 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.510 ; -; 0.918 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.612 ; -; 0.919 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.613 ; -; 0.921 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.614 ; -; 0.923 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.617 ; -; 0.924 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.618 ; -; 0.924 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.618 ; -; 0.926 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.619 ; -; 0.938 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.632 ; -; 0.938 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.632 ; -; 0.938 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.631 ; -; 0.943 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.637 ; -; 0.943 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.637 ; -; 0.943 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.507 ; 1.636 ; -; 0.944 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.638 ; -; 0.958 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.240 ; -; 0.959 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.241 ; -; 0.961 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.243 ; -; 0.970 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.252 ; -; 0.972 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.081 ; 1.239 ; -; 0.972 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.254 ; -; 0.973 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.255 ; -; 0.975 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.240 ; -; 0.975 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.240 ; -; 0.975 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.257 ; -; 0.977 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.242 ; -; 0.977 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.259 ; -; 0.978 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.260 ; -; 0.987 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.253 ; -; 0.989 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.254 ; -; 0.989 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.254 ; -; 0.990 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.255 ; -; 0.990 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.255 ; -; 0.992 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.081 ; 1.259 ; -; 0.994 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.259 ; -; 0.995 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.260 ; -; 0.995 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.260 ; -; 1.044 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.738 ; -; 1.045 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.739 ; -; 1.045 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.739 ; -; 1.049 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.743 ; -; 1.050 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.744 ; -; 1.050 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.744 ; -; 1.052 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.746 ; -; 1.064 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.758 ; -; 1.064 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.758 ; -; 1.065 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.759 ; -; 1.069 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.763 ; -; 1.069 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.763 ; -; 1.070 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.764 ; -; 1.070 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.508 ; 1.764 ; -; 1.079 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.361 ; -; 1.080 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.362 ; -; 1.084 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.366 ; -; 1.085 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.367 ; -; 1.093 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.081 ; 1.360 ; -; 1.096 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.361 ; -; 1.096 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.361 ; -; 1.098 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.380 ; -; 1.098 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.363 ; -; 1.099 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.381 ; -; 1.099 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.081 ; 1.366 ; -; 1.101 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.366 ; -; 1.103 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.385 ; -; 1.103 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.079 ; 1.368 ; -; 1.104 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.096 ; 1.386 ; +; 0.543 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.239 ; +; 0.563 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.259 ; +; 0.639 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.923 ; +; 0.639 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.923 ; +; 0.640 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.924 ; +; 0.640 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.924 ; +; 0.641 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.925 ; +; 0.641 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.925 ; +; 0.643 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.927 ; +; 0.644 ; AccN:inst|RegN:reg|dataOut[16] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.928 ; +; 0.645 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 0.929 ; +; 0.657 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.923 ; +; 0.658 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.924 ; +; 0.658 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.924 ; +; 0.658 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.924 ; +; 0.658 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.924 ; +; 0.659 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.925 ; +; 0.662 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.928 ; +; 0.664 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.360 ; +; 0.669 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.365 ; +; 0.670 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.366 ; +; 0.676 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[0] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 0.942 ; +; 0.684 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.380 ; +; 0.689 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.385 ; +; 0.689 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.385 ; +; 0.790 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.486 ; +; 0.791 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.487 ; +; 0.795 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.491 ; +; 0.796 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.492 ; +; 0.796 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.492 ; +; 0.810 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.506 ; +; 0.810 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.506 ; +; 0.815 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.511 ; +; 0.815 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.511 ; +; 0.816 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.512 ; +; 0.916 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.612 ; +; 0.917 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.613 ; +; 0.917 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.613 ; +; 0.921 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.617 ; +; 0.922 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.618 ; +; 0.922 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.618 ; +; 0.924 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.620 ; +; 0.936 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.632 ; +; 0.936 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.632 ; +; 0.937 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.633 ; +; 0.941 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.637 ; +; 0.941 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.637 ; +; 0.942 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.638 ; +; 0.942 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.638 ; +; 0.956 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.240 ; +; 0.957 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.241 ; +; 0.957 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.241 ; +; 0.959 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.243 ; +; 0.968 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.252 ; +; 0.969 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.253 ; +; 0.970 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.254 ; +; 0.971 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.255 ; +; 0.973 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.257 ; +; 0.974 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.240 ; +; 0.974 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.240 ; +; 0.974 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.258 ; +; 0.975 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.259 ; +; 0.976 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.242 ; +; 0.976 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.260 ; +; 0.988 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.254 ; +; 0.988 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.254 ; +; 0.989 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.255 ; +; 0.989 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.255 ; +; 0.993 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.259 ; +; 0.994 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.260 ; +; 0.994 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.260 ; +; 1.042 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.738 ; +; 1.043 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.739 ; +; 1.043 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.739 ; +; 1.045 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.741 ; +; 1.047 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.743 ; +; 1.048 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.744 ; +; 1.048 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.744 ; +; 1.050 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.746 ; +; 1.062 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.758 ; +; 1.062 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.758 ; +; 1.063 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.759 ; +; 1.063 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.759 ; +; 1.067 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.763 ; +; 1.067 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.763 ; +; 1.068 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.764 ; +; 1.068 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.510 ; 1.764 ; +; 1.077 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.361 ; +; 1.078 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.362 ; +; 1.078 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.362 ; +; 1.082 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.366 ; +; 1.083 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.367 ; +; 1.083 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.367 ; +; 1.095 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.379 ; +; 1.095 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.361 ; +; 1.095 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.361 ; +; 1.096 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.380 ; +; 1.097 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.080 ; 1.363 ; +; 1.097 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.381 ; +; 1.100 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.098 ; 1.384 ; +-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ @@ -513,106 +513,106 @@ No paths to report. +-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ -; 0.654 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.920 ; -; 0.655 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.921 ; -; 0.655 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.921 ; -; 0.656 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.922 ; -; 0.656 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.922 ; -; 0.657 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.923 ; -; 0.657 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.923 ; -; 0.658 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.924 ; -; 0.658 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.924 ; -; 0.658 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.924 ; -; 0.658 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.924 ; -; 0.659 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.925 ; -; 0.660 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.926 ; -; 0.660 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.926 ; -; 0.661 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.927 ; -; 0.661 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.927 ; -; 0.661 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.927 ; -; 0.662 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.928 ; -; 0.662 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.928 ; -; 0.662 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 0.928 ; -; 0.664 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.098 ; 0.948 ; -; 0.973 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.239 ; -; 0.973 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.239 ; -; 0.974 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.240 ; -; 0.975 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.241 ; -; 0.975 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.241 ; -; 0.975 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.241 ; -; 0.976 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.242 ; -; 0.987 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.253 ; -; 0.987 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.253 ; -; 0.988 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.254 ; -; 0.989 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.255 ; -; 0.989 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.255 ; -; 0.989 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.255 ; -; 0.992 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.258 ; -; 0.993 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.259 ; -; 0.993 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.259 ; -; 0.994 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.260 ; -; 0.994 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.260 ; -; 1.094 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.079 ; 1.359 ; -; 1.094 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.360 ; -; 1.094 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.360 ; -; 1.094 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.360 ; -; 1.095 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.361 ; -; 1.096 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.362 ; -; 1.096 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.362 ; -; 1.097 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.363 ; -; 1.099 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.365 ; -; 1.099 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.365 ; -; 1.100 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.366 ; -; 1.101 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.367 ; -; 1.101 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.367 ; -; 1.102 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.368 ; -; 1.111 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.377 ; -; 1.113 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.379 ; -; 1.113 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.379 ; -; 1.115 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.381 ; -; 1.115 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.381 ; -; 1.116 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.382 ; -; 1.118 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.384 ; -; 1.120 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.386 ; -; 1.137 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.401 ; -; 1.138 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.402 ; -; 1.151 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.415 ; -; 1.153 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.417 ; -; 1.156 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.420 ; -; 1.179 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.443 ; -; 1.192 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.456 ; -; 1.220 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.486 ; -; 1.220 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.486 ; -; 1.220 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.486 ; -; 1.222 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.488 ; -; 1.223 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.489 ; -; 1.225 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.079 ; 1.490 ; -; 1.225 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.491 ; -; 1.225 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.491 ; -; 1.226 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.492 ; -; 1.228 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.494 ; -; 1.237 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.503 ; -; 1.239 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.505 ; -; 1.239 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.505 ; -; 1.240 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.506 ; -; 1.240 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.506 ; -; 1.241 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.507 ; -; 1.242 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.508 ; -; 1.244 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.510 ; -; 1.244 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.510 ; -; 1.245 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.511 ; -; 1.248 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.512 ; -; 1.264 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.528 ; -; 1.277 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.541 ; -; 1.282 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.546 ; -; 1.284 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.548 ; -; 1.305 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.569 ; -; 1.314 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.578 ; -; 1.318 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.582 ; -; 1.328 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.594 ; -; 1.346 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.612 ; -; 1.346 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.612 ; -; 1.348 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.614 ; +; 0.653 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.920 ; +; 0.654 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.921 ; +; 0.654 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.921 ; +; 0.655 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.922 ; +; 0.655 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.922 ; +; 0.656 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.923 ; +; 0.656 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.923 ; +; 0.657 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.924 ; +; 0.657 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.924 ; +; 0.657 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.924 ; +; 0.657 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.924 ; +; 0.659 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.926 ; +; 0.660 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.927 ; +; 0.660 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.927 ; +; 0.660 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.927 ; +; 0.660 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.927 ; +; 0.661 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ; +; 0.661 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ; +; 0.661 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ; +; 0.661 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.928 ; +; 0.681 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 0.948 ; +; 0.972 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.239 ; +; 0.972 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.239 ; +; 0.973 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.240 ; +; 0.974 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.241 ; +; 0.974 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.241 ; +; 0.974 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.241 ; +; 0.985 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.252 ; +; 0.986 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.253 ; +; 0.987 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.254 ; +; 0.987 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.254 ; +; 0.988 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.255 ; +; 0.988 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.255 ; +; 0.988 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.255 ; +; 0.989 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.256 ; +; 0.990 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.257 ; +; 0.991 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.258 ; +; 0.992 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.259 ; +; 0.992 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.259 ; +; 0.993 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.260 ; +; 0.993 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.260 ; +; 0.993 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.260 ; +; 1.093 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.360 ; +; 1.093 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.360 ; +; 1.093 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.360 ; +; 1.094 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.361 ; +; 1.095 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.359 ; +; 1.095 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.362 ; +; 1.095 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.362 ; +; 1.098 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.365 ; +; 1.098 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.365 ; +; 1.099 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.366 ; +; 1.100 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.367 ; +; 1.100 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.367 ; +; 1.111 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.378 ; +; 1.112 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.379 ; +; 1.113 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.380 ; +; 1.114 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.381 ; +; 1.114 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.381 ; +; 1.114 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.381 ; +; 1.115 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.382 ; +; 1.116 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.383 ; +; 1.117 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.385 ; +; 1.118 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.385 ; +; 1.118 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.385 ; +; 1.119 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.386 ; +; 1.119 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.386 ; +; 1.139 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.405 ; +; 1.140 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.406 ; +; 1.152 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.418 ; +; 1.172 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.438 ; +; 1.182 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.448 ; +; 1.193 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.459 ; +; 1.199 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.465 ; +; 1.219 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.486 ; +; 1.219 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.486 ; +; 1.219 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.486 ; +; 1.221 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.488 ; +; 1.224 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.491 ; +; 1.224 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.491 ; +; 1.225 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.492 ; +; 1.226 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.078 ; 1.490 ; +; 1.236 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.503 ; +; 1.237 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.504 ; +; 1.238 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.505 ; +; 1.239 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.506 ; +; 1.239 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.506 ; +; 1.240 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.507 ; +; 1.240 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.507 ; +; 1.241 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.508 ; +; 1.243 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.510 ; +; 1.244 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.511 ; +; 1.244 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.511 ; +; 1.245 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.082 ; 1.513 ; +; 1.245 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.081 ; 1.512 ; +; 1.256 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.522 ; +; 1.259 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.525 ; +; 1.265 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.531 ; +; 1.266 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.532 ; +; 1.275 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.080 ; 1.541 ; +-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ @@ -627,8 +627,8 @@ No synchronizer chains to report. +------------+-----------------+--------------------------+------------------------------------------------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+--------------------------+------------------------------------------------+ -; 210.48 MHz ; 210.48 MHz ; CLOCK_50 ; ; -; 480.31 MHz ; 437.64 MHz ; FreqDivider:inst2|clkOut ; limit due to minimum period restriction (tmin) ; +; 206.19 MHz ; 206.19 MHz ; CLOCK_50 ; ; +; 480.54 MHz ; 437.64 MHz ; FreqDivider:inst2|clkOut ; limit due to minimum period restriction (tmin) ; +------------+-----------------+--------------------------+------------------------------------------------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -638,8 +638,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+--------+---------------+ -; CLOCK_50 ; -3.751 ; -67.496 ; -; FreqDivider:inst2|clkOut ; -1.082 ; -13.558 ; +; CLOCK_50 ; -3.850 ; -55.792 ; +; FreqDivider:inst2|clkOut ; -1.081 ; -12.785 ; +--------------------------+--------+---------------+ @@ -648,8 +648,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+-------+---------------+ -; FreqDivider:inst2|clkOut ; 0.494 ; 0.000 ; -; CLOCK_50 ; 0.597 ; 0.000 ; +; FreqDivider:inst2|clkOut ; 0.489 ; 0.000 ; +; CLOCK_50 ; 0.598 ; 0.000 ; +--------------------------+-------+---------------+ @@ -680,106 +680,106 @@ No paths to report. +--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ -; -3.751 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.680 ; -; -3.742 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.671 ; -; -3.718 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.647 ; -; -3.714 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.643 ; -; -3.683 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.612 ; -; -3.640 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.569 ; -; -3.603 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.532 ; -; -3.576 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.505 ; -; -3.540 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.467 ; -; -3.538 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.465 ; -; -3.531 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.458 ; -; -3.516 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.445 ; -; -3.473 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.402 ; -; -3.468 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.397 ; -; -3.441 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.370 ; -; -3.368 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.297 ; -; -3.356 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.285 ; -; -3.352 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.279 ; -; -3.347 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.276 ; -; -3.310 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.237 ; -; -3.224 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.151 ; -; -3.208 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.135 ; -; -3.198 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.127 ; -; -3.197 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.124 ; -; -3.181 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.110 ; -; -3.124 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.053 ; -; -3.107 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.034 ; -; -3.105 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 4.034 ; -; -3.028 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.467 ; 3.560 ; -; -2.960 ; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.887 ; -; -2.862 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.789 ; -; -2.787 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.716 ; -; -2.772 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.467 ; 3.304 ; -; -2.737 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.467 ; 3.269 ; -; -2.724 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.467 ; 3.256 ; -; -2.685 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.469 ; 3.215 ; -; -2.676 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.467 ; 3.208 ; -; -2.590 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.519 ; -; -2.588 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.517 ; -; -2.587 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.469 ; 3.117 ; -; -2.569 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.469 ; 3.099 ; -; -2.552 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.481 ; -; -2.516 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.445 ; -; -2.511 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.440 ; -; -2.511 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.440 ; -; -2.509 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.438 ; -; -2.509 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.438 ; -; -2.489 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.467 ; 3.021 ; -; -2.489 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.467 ; 3.021 ; -; -2.471 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.469 ; 3.001 ; -; -2.453 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.469 ; 2.983 ; -; -2.453 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.380 ; -; -2.447 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.376 ; -; -2.445 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.374 ; -; -2.433 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.362 ; -; -2.433 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.467 ; 2.965 ; -; -2.419 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.348 ; -; -2.408 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.337 ; -; -2.406 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.335 ; -; -2.401 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.330 ; -; -2.401 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.330 ; -; -2.399 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.328 ; -; -2.393 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.322 ; -; -2.379 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.467 ; 2.911 ; -; -2.362 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.291 ; -; -2.360 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.289 ; -; -2.358 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.287 ; -; -2.355 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.469 ; 2.885 ; -; -2.353 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.282 ; -; -2.351 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.280 ; -; -2.350 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.277 ; -; -2.348 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.275 ; -; -2.337 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.469 ; 2.867 ; -; -2.329 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.258 ; -; -2.327 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.256 ; -; -2.322 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.251 ; -; -2.322 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.251 ; -; -2.321 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.248 ; -; -2.320 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.249 ; -; -2.320 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.249 ; -; -2.319 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.246 ; -; -2.318 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.247 ; -; -2.314 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.243 ; -; -2.314 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.243 ; -; -2.312 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.239 ; -; -2.310 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.237 ; -; -2.300 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.229 ; -; -2.269 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.196 ; -; -2.269 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.196 ; -; -2.259 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.188 ; -; -2.258 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.187 ; -; -2.256 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.185 ; -; -2.250 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.179 ; -; -2.240 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.167 ; -; -2.239 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.168 ; -; -2.224 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.153 ; -; -2.222 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.151 ; -; -2.220 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.149 ; -; -2.219 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.148 ; -; -2.217 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.070 ; 3.146 ; +; -3.850 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.777 ; +; -3.839 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.766 ; +; -3.832 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.759 ; +; -3.821 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.745 ; +; -3.814 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.738 ; +; -3.760 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.687 ; +; -3.757 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.684 ; +; -3.693 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 4.616 ; +; -3.688 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 4.611 ; +; -3.652 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.576 ; +; -3.632 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.559 ; +; -3.604 ; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 4.527 ; +; -3.598 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 4.521 ; +; -3.540 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.464 ; +; -3.539 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.463 ; +; -3.528 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 4.451 ; +; -3.453 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.377 ; +; -3.405 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.332 ; +; -3.383 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.307 ; +; -3.246 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 4.172 ; +; -3.139 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 4.066 ; +; -3.137 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 4.063 ; +; -3.100 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 4.024 ; +; -3.036 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.963 ; +; -2.980 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.907 ; +; -2.965 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.891 ; +; -2.946 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.870 ; +; -2.904 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.828 ; +; -2.861 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.787 ; +; -2.780 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.704 ; +; -2.758 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.684 ; +; -2.744 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.073 ; 3.670 ; +; -2.437 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.361 ; +; -2.357 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.281 ; +; -2.328 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.252 ; +; -2.321 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.245 ; +; -2.316 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.244 ; +; -2.302 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.225 ; +; -2.292 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.216 ; +; -2.272 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.196 ; +; -2.256 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.183 ; +; -2.255 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.182 ; +; -2.254 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.181 ; +; -2.251 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.178 ; +; -2.250 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.177 ; +; -2.249 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.176 ; +; -2.248 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.172 ; +; -2.248 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.175 ; +; -2.247 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.174 ; +; -2.246 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.173 ; +; -2.243 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.167 ; +; -2.242 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.166 ; +; -2.238 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.162 ; +; -2.237 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.165 ; +; -2.227 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.151 ; +; -2.220 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.144 ; +; -2.219 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.143 ; +; -2.217 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.141 ; +; -2.213 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.137 ; +; -2.212 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.136 ; +; -2.211 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.135 ; +; -2.210 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.134 ; +; -2.197 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.125 ; +; -2.193 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.116 ; +; -2.193 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.117 ; +; -2.176 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.100 ; +; -2.176 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.100 ; +; -2.176 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.103 ; +; -2.175 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.102 ; +; -2.174 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.101 ; +; -2.173 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.100 ; +; -2.172 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.099 ; +; -2.171 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.072 ; 3.098 ; +; -2.163 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.087 ; +; -2.157 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.080 ; +; -2.156 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.080 ; +; -2.153 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.077 ; +; -2.147 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.071 ; +; -2.131 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.055 ; +; -2.127 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.051 ; +; -2.124 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.048 ; +; -2.123 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.047 ; +; -2.123 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.047 ; +; -2.122 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.050 ; +; -2.111 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.035 ; +; -2.099 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.023 ; +; -2.095 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.019 ; +; -2.092 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.015 ; +; -2.092 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.015 ; +; -2.091 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.014 ; +; -2.089 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.012 ; +; -2.087 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.010 ; +; -2.086 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.009 ; +; -2.084 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 3.007 ; +; -2.082 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.071 ; 3.010 ; +; -2.078 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.002 ; +; -2.077 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 3.001 ; +; -2.076 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.076 ; 2.999 ; +; -2.068 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 2.992 ; +; -2.067 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.075 ; 2.991 ; +--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ @@ -788,106 +788,106 @@ No paths to report. +--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ -; -1.082 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.387 ; -; -1.015 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.942 ; -; -1.003 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.308 ; -; -0.996 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.923 ; -; -0.985 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.290 ; -; -0.967 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.894 ; -; -0.966 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.271 ; -; -0.962 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.267 ; -; -0.937 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.242 ; -; -0.917 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.844 ; -; -0.900 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.826 ; -; -0.899 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.826 ; -; -0.893 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.803 ; -; -0.887 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.192 ; -; -0.887 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.192 ; -; -0.881 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.807 ; -; -0.876 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.803 ; -; -0.869 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.174 ; -; -0.869 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.174 ; -; -0.852 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.778 ; -; -0.850 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.155 ; -; -0.847 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.774 ; -; -0.846 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.151 ; -; -0.845 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.150 ; -; -0.821 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.126 ; -; -0.817 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.727 ; -; -0.817 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.122 ; -; -0.802 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.728 ; -; -0.801 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.728 ; -; -0.800 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.710 ; -; -0.784 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.710 ; -; -0.784 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.710 ; -; -0.783 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.710 ; -; -0.778 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.688 ; -; -0.777 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.687 ; -; -0.771 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.076 ; -; -0.771 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.076 ; -; -0.770 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.075 ; -; -0.765 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.691 ; -; -0.761 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.687 ; -; -0.759 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.686 ; -; -0.753 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.058 ; -; -0.753 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.058 ; -; -0.753 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.058 ; -; -0.748 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.658 ; -; -0.736 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.662 ; -; -0.734 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.039 ; -; -0.732 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.658 ; -; -0.730 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.657 ; -; -0.730 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.035 ; -; -0.729 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.034 ; -; -0.728 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.033 ; -; -0.705 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.010 ; -; -0.702 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.612 ; -; -0.701 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.611 ; -; -0.701 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.006 ; -; -0.700 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 2.005 ; -; -0.686 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.612 ; -; -0.686 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.612 ; -; -0.684 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.611 ; -; -0.684 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.594 ; -; -0.684 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.594 ; -; -0.668 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.594 ; -; -0.668 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.594 ; -; -0.668 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.594 ; -; -0.666 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.576 ; -; -0.666 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.593 ; -; -0.662 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.572 ; -; -0.661 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.571 ; -; -0.655 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.960 ; -; -0.655 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.960 ; -; -0.654 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.959 ; -; -0.654 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.959 ; -; -0.649 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.575 ; -; -0.645 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.571 ; -; -0.644 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.570 ; -; -0.642 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.569 ; -; -0.637 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.942 ; -; -0.637 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.942 ; -; -0.636 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.941 ; -; -0.633 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.543 ; -; -0.632 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.542 ; -; -0.620 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.546 ; -; -0.618 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.305 ; 1.922 ; -; -0.616 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.542 ; -; -0.615 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.541 ; -; -0.614 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.919 ; -; -0.613 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.540 ; -; -0.613 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.918 ; -; -0.612 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.917 ; -; -0.592 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.502 ; -; -0.586 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.496 ; -; -0.585 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.089 ; 1.495 ; -; -0.585 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.890 ; -; -0.584 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.889 ; -; -0.583 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.306 ; 1.888 ; -; -0.570 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.496 ; -; -0.570 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.496 ; -; -0.569 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.073 ; 1.495 ; -; -0.568 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.495 ; +; -1.081 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.387 ; +; -1.011 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.922 ; +; -1.002 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.308 ; +; -0.984 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.290 ; +; -0.965 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.271 ; +; -0.961 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.267 ; +; -0.936 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.242 ; +; -0.931 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.842 ; +; -0.914 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.825 ; +; -0.899 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.826 ; +; -0.895 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.806 ; +; -0.892 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.803 ; +; -0.886 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.192 ; +; -0.886 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.192 ; +; -0.880 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.807 ; +; -0.868 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.174 ; +; -0.868 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.174 ; +; -0.866 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.777 ; +; -0.851 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.778 ; +; -0.849 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.155 ; +; -0.845 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.151 ; +; -0.844 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.150 ; +; -0.820 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.126 ; +; -0.816 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.727 ; +; -0.816 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.122 ; +; -0.815 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.726 ; +; -0.801 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.728 ; +; -0.799 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.710 ; +; -0.798 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.709 ; +; -0.783 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.710 ; +; -0.783 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.710 ; +; -0.779 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.690 ; +; -0.777 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.688 ; +; -0.776 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.687 ; +; -0.770 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.076 ; +; -0.770 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.076 ; +; -0.769 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.075 ; +; -0.764 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.691 ; +; -0.760 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.687 ; +; -0.752 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.058 ; +; -0.752 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.058 ; +; -0.752 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.058 ; +; -0.750 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.661 ; +; -0.747 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.658 ; +; -0.735 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.662 ; +; -0.733 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.039 ; +; -0.731 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.658 ; +; -0.729 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.035 ; +; -0.728 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.034 ; +; -0.727 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.033 ; +; -0.704 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.010 ; +; -0.701 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.612 ; +; -0.700 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.611 ; +; -0.700 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.006 ; +; -0.699 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 2.005 ; +; -0.699 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.610 ; +; -0.685 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.612 ; +; -0.685 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.612 ; +; -0.683 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.594 ; +; -0.683 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.594 ; +; -0.682 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.593 ; +; -0.667 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.594 ; +; -0.667 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.594 ; +; -0.667 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.594 ; +; -0.665 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.576 ; +; -0.663 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.574 ; +; -0.661 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.572 ; +; -0.660 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.571 ; +; -0.654 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.960 ; +; -0.654 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.960 ; +; -0.653 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.959 ; +; -0.653 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.959 ; +; -0.648 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.575 ; +; -0.644 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.571 ; +; -0.643 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.570 ; +; -0.636 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.942 ; +; -0.636 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.942 ; +; -0.636 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.942 ; +; -0.635 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.941 ; +; -0.634 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.545 ; +; -0.632 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.543 ; +; -0.631 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.542 ; +; -0.619 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.546 ; +; -0.617 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.923 ; +; -0.615 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.542 ; +; -0.614 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.541 ; +; -0.613 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.919 ; +; -0.612 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.918 ; +; -0.611 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.917 ; +; -0.591 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.502 ; +; -0.588 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.894 ; +; -0.585 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.496 ; +; -0.584 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.495 ; +; -0.584 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.890 ; +; -0.583 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.889 ; +; -0.583 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.088 ; 1.494 ; +; -0.582 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.307 ; 1.888 ; +; -0.569 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.496 ; +; -0.569 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.496 ; +; -0.568 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.072 ; 1.495 ; +--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ @@ -896,106 +896,106 @@ No paths to report. +-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ -; 0.494 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.132 ; -; 0.507 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.145 ; -; 0.583 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 0.843 ; -; 0.583 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 0.843 ; -; 0.584 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 0.844 ; -; 0.585 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 0.845 ; -; 0.586 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 0.846 ; -; 0.588 ; AccN:inst|RegN:reg|dataOut[16] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 0.848 ; -; 0.589 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 0.849 ; -; 0.593 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.231 ; -; 0.598 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 0.842 ; -; 0.598 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.237 ; -; 0.599 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 0.843 ; -; 0.599 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 0.843 ; -; 0.600 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 0.844 ; -; 0.601 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 0.845 ; -; 0.601 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 0.845 ; -; 0.602 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 0.846 ; -; 0.603 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 0.847 ; -; 0.604 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 0.848 ; -; 0.604 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.242 ; -; 0.606 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.244 ; -; 0.617 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.256 ; -; 0.617 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.255 ; -; 0.619 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[0] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 0.863 ; -; 0.697 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.336 ; -; 0.703 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.341 ; -; 0.708 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.347 ; -; 0.709 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.348 ; -; 0.714 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.352 ; -; 0.716 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.355 ; -; 0.716 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.354 ; -; 0.727 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.366 ; -; 0.727 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.366 ; -; 0.727 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.365 ; -; 0.807 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.446 ; -; 0.808 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.447 ; -; 0.813 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.451 ; -; 0.818 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.457 ; -; 0.819 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.458 ; -; 0.819 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.458 ; -; 0.824 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.462 ; -; 0.826 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.465 ; -; 0.826 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.465 ; -; 0.826 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.464 ; -; 0.837 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.476 ; -; 0.837 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.476 ; -; 0.837 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.475 ; -; 0.838 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.477 ; -; 0.868 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.128 ; -; 0.869 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.129 ; -; 0.872 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.132 ; -; 0.874 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.134 ; -; 0.875 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.135 ; -; 0.876 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.136 ; -; 0.882 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.074 ; 1.127 ; -; 0.883 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.143 ; -; 0.884 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.128 ; -; 0.884 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.128 ; -; 0.886 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.146 ; -; 0.887 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.147 ; -; 0.889 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.133 ; -; 0.890 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.134 ; -; 0.891 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.135 ; -; 0.891 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.135 ; -; 0.892 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.136 ; -; 0.892 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.136 ; -; 0.901 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.074 ; 1.146 ; -; 0.902 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.146 ; -; 0.903 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.147 ; -; 0.903 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.147 ; -; 0.917 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.556 ; -; 0.918 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.557 ; -; 0.918 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.557 ; -; 0.928 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.567 ; -; 0.929 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.568 ; -; 0.929 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.568 ; -; 0.934 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.573 ; -; 0.936 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.575 ; -; 0.936 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.575 ; -; 0.937 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.576 ; -; 0.947 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.586 ; -; 0.947 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.586 ; -; 0.948 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.587 ; -; 0.948 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.468 ; 1.587 ; -; 0.967 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.227 ; -; 0.968 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.228 ; -; 0.978 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.238 ; -; 0.979 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.239 ; -; 0.981 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.074 ; 1.226 ; -; 0.983 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.227 ; -; 0.983 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.227 ; -; 0.985 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.245 ; -; 0.986 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.246 ; -; 0.988 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.232 ; -; 0.993 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.074 ; 1.238 ; -; 0.994 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.238 ; -; 0.996 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.256 ; -; 0.997 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.089 ; 1.257 ; -; 0.999 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.073 ; 1.243 ; +; 0.489 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.127 ; +; 0.508 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.146 ; +; 0.584 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.843 ; +; 0.584 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.843 ; +; 0.585 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.844 ; +; 0.585 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.844 ; +; 0.586 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.845 ; +; 0.587 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.846 ; +; 0.588 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.847 ; +; 0.588 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.226 ; +; 0.589 ; AccN:inst|RegN:reg|dataOut[16] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.848 ; +; 0.590 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 0.849 ; +; 0.599 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.842 ; +; 0.599 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.237 ; +; 0.600 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.843 ; +; 0.600 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.843 ; +; 0.600 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.238 ; +; 0.602 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.845 ; +; 0.602 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.845 ; +; 0.603 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.846 ; +; 0.605 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.848 ; +; 0.607 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.245 ; +; 0.618 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.256 ; +; 0.618 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.256 ; +; 0.620 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[0] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 0.863 ; +; 0.698 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.336 ; +; 0.699 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.337 ; +; 0.709 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.347 ; +; 0.710 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.348 ; +; 0.710 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.348 ; +; 0.717 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.355 ; +; 0.717 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.355 ; +; 0.728 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.366 ; +; 0.728 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.366 ; +; 0.729 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.367 ; +; 0.808 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.446 ; +; 0.809 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.447 ; +; 0.809 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.447 ; +; 0.819 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.457 ; +; 0.820 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.458 ; +; 0.820 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.458 ; +; 0.825 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.463 ; +; 0.827 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.465 ; +; 0.827 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.465 ; +; 0.828 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.466 ; +; 0.838 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.476 ; +; 0.838 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.476 ; +; 0.839 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.477 ; +; 0.839 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.477 ; +; 0.869 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.128 ; +; 0.870 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.129 ; +; 0.873 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.132 ; +; 0.873 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.132 ; +; 0.875 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.134 ; +; 0.875 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.134 ; +; 0.876 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.135 ; +; 0.877 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.136 ; +; 0.884 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.143 ; +; 0.885 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.128 ; +; 0.885 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.128 ; +; 0.886 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.145 ; +; 0.887 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.146 ; +; 0.888 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.147 ; +; 0.890 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.133 ; +; 0.892 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.135 ; +; 0.892 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.135 ; +; 0.893 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.136 ; +; 0.893 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.136 ; +; 0.903 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.146 ; +; 0.904 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.147 ; +; 0.904 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.147 ; +; 0.918 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.556 ; +; 0.919 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.557 ; +; 0.919 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.557 ; +; 0.924 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.562 ; +; 0.929 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.567 ; +; 0.930 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.568 ; +; 0.930 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.568 ; +; 0.935 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.573 ; +; 0.937 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.575 ; +; 0.937 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.575 ; +; 0.938 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.576 ; +; 0.938 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.576 ; +; 0.948 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.586 ; +; 0.948 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.586 ; +; 0.949 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.587 ; +; 0.949 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.467 ; 1.587 ; +; 0.968 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.227 ; +; 0.969 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.228 ; +; 0.972 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.231 ; +; 0.979 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.238 ; +; 0.980 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.239 ; +; 0.983 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.242 ; +; 0.984 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.227 ; +; 0.984 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.227 ; +; 0.985 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.244 ; +; 0.986 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.245 ; +; 0.987 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.088 ; 1.246 ; +; 0.989 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.232 ; +; 0.995 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.072 ; 1.238 ; +-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ @@ -1004,18 +1004,17 @@ No paths to report. +-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ -; 0.597 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.840 ; +; 0.598 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.841 ; ; 0.598 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.841 ; ; 0.598 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.841 ; ; 0.599 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.842 ; ; 0.600 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.843 ; ; 0.600 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.843 ; ; 0.600 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.843 ; -; 0.600 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.843 ; ; 0.601 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.844 ; +; 0.601 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.844 ; ; 0.602 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.845 ; ; 0.602 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.845 ; -; 0.603 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.846 ; ; 0.603 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.846 ; ; 0.604 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.847 ; ; 0.604 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.847 ; @@ -1024,86 +1023,87 @@ No paths to report. ; 0.604 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.847 ; ; 0.605 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.848 ; ; 0.605 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.848 ; -; 0.607 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.088 ; 0.866 ; +; 0.605 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.848 ; +; 0.623 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 0.866 ; ; 0.884 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.127 ; ; 0.885 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.128 ; ; 0.886 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.129 ; -; 0.887 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.130 ; +; 0.888 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.131 ; ; 0.889 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.132 ; ; 0.889 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.132 ; -; 0.890 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.133 ; +; 0.890 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.133 ; ; 0.891 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.134 ; ; 0.892 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.135 ; ; 0.892 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.135 ; ; 0.892 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.135 ; ; 0.893 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.136 ; ; 0.893 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.136 ; +; 0.899 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.142 ; +; 0.901 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.144 ; ; 0.902 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.145 ; ; 0.903 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.146 ; ; 0.903 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.146 ; +; 0.904 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.147 ; ; 0.904 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.147 ; ; 0.904 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.147 ; -; 0.982 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.225 ; ; 0.983 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.226 ; ; 0.983 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.226 ; ; 0.984 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.227 ; ; 0.985 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.228 ; -; 0.986 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.229 ; +; 0.986 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 1.226 ; +; 0.987 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.230 ; ; 0.988 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.231 ; -; 0.989 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.232 ; ; 0.994 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.237 ; ; 0.996 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.239 ; -; 0.997 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.240 ; ; 0.998 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.241 ; -; 0.998 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.241 ; +; 0.998 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.241 ; ; 0.999 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.242 ; -; 1.000 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.243 ; +; 1.000 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.243 ; ; 1.001 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.244 ; ; 1.002 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.245 ; +; 1.003 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.246 ; ; 1.003 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.246 ; ; 1.003 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.246 ; ; 1.009 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.252 ; +; 1.011 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.254 ; +; 1.013 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.256 ; ; 1.013 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.256 ; +; 1.014 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.257 ; ; 1.014 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.257 ; -; 1.029 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.270 ; -; 1.046 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.287 ; -; 1.048 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.289 ; -; 1.050 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.291 ; -; 1.052 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.293 ; -; 1.064 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.305 ; +; 1.029 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.273 ; +; 1.048 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.291 ; +; 1.048 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.291 ; +; 1.050 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.293 ; +; 1.063 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 1.305 ; +; 1.082 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.325 ; +; 1.092 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.335 ; ; 1.093 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.336 ; ; 1.093 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.336 ; ; 1.095 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.338 ; -; 1.096 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.339 ; -; 1.097 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.338 ; -; 1.099 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.342 ; -; 1.103 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.346 ; +; 1.097 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.340 ; ; 1.104 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.347 ; ; 1.104 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.347 ; +; 1.106 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 1.348 ; +; 1.107 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.069 ; 1.347 ; ; 1.108 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.351 ; ; 1.108 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.351 ; -; 1.110 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.353 ; +; 1.110 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.353 ; ; 1.111 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.354 ; ; 1.112 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.355 ; -; 1.112 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.355 ; ; 1.112 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.355 ; +; 1.113 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.356 ; ; 1.113 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.356 ; -; 1.115 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.356 ; ; 1.119 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.362 ; +; 1.120 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.363 ; ; 1.122 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.365 ; ; 1.123 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.366 ; ; 1.123 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.366 ; -; 1.139 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.380 ; -; 1.160 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.401 ; -; 1.162 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.403 ; -; 1.174 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.415 ; -; 1.175 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.416 ; -; 1.178 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.419 ; -; 1.201 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.444 ; -; 1.203 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.446 ; -; 1.206 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.449 ; -; 1.207 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.070 ; 1.448 ; -; 1.208 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.451 ; +; 1.124 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 1.366 ; +; 1.124 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.367 ; +; 1.147 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.073 ; 1.391 ; +; 1.158 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.401 ; +; 1.158 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.072 ; 1.401 ; +; 1.160 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.071 ; 1.402 ; +-------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ @@ -1118,8 +1118,8 @@ No synchronizer chains to report. +--------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+--------+---------------+ -; CLOCK_50 ; -1.596 ; -21.945 ; -; FreqDivider:inst2|clkOut ; -0.171 ; -0.699 ; +; CLOCK_50 ; -1.676 ; -16.763 ; +; FreqDivider:inst2|clkOut ; -0.170 ; -0.504 ; +--------------------------+--------+---------------+ @@ -1128,8 +1128,8 @@ No synchronizer chains to report. +--------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+-------+---------------+ -; FreqDivider:inst2|clkOut ; 0.247 ; 0.000 ; -; CLOCK_50 ; 0.298 ; 0.000 ; +; FreqDivider:inst2|clkOut ; 0.244 ; 0.000 ; +; CLOCK_50 ; 0.297 ; 0.000 ; +--------------------------+-------+---------------+ @@ -1150,7 +1150,7 @@ No paths to report. +--------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +--------------------------+--------+---------------+ -; CLOCK_50 ; -3.000 ; -38.002 ; +; CLOCK_50 ; -3.000 ; -38.036 ; ; FreqDivider:inst2|clkOut ; -1.000 ; -17.000 ; +--------------------------+--------+---------------+ @@ -1160,106 +1160,106 @@ No paths to report. +--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ -; -1.596 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.544 ; -; -1.584 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.532 ; -; -1.582 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.530 ; -; -1.566 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.514 ; -; -1.552 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.500 ; -; -1.530 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.478 ; -; -1.516 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.464 ; -; -1.507 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.455 ; -; -1.501 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.449 ; -; -1.457 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.405 ; -; -1.435 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.381 ; -; -1.430 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.378 ; -; -1.423 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.369 ; -; -1.418 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.364 ; -; -1.410 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.358 ; -; -1.400 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.348 ; -; -1.392 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.340 ; -; -1.380 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.328 ; -; -1.363 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.311 ; -; -1.354 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.302 ; -; -1.342 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.288 ; -; -1.339 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.285 ; -; -1.338 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.284 ; -; -1.316 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.262 ; -; -1.311 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.257 ; -; -1.305 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.253 ; -; -1.275 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.221 ; -; -1.247 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.195 ; -; -1.203 ; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.149 ; -; -1.196 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.242 ; 1.941 ; -; -1.140 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 2.086 ; -; -1.127 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 2.075 ; -; -1.093 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.242 ; 1.838 ; -; -1.041 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.242 ; 1.786 ; -; -1.033 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.244 ; 1.776 ; -; -1.020 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.242 ; 1.765 ; -; -1.011 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.242 ; 1.756 ; -; -1.007 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.955 ; -; -0.995 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.244 ; 1.738 ; -; -0.965 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.244 ; 1.708 ; -; -0.936 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.884 ; -; -0.929 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.877 ; -; -0.927 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.875 ; -; -0.927 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.244 ; 1.670 ; -; -0.926 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.874 ; -; -0.905 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.853 ; -; -0.903 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.851 ; -; -0.897 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.244 ; 1.640 ; -; -0.896 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.242 ; 1.641 ; -; -0.886 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.834 ; -; -0.877 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.242 ; 1.622 ; -; -0.869 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.817 ; -; -0.868 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.816 ; -; -0.867 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.815 ; -; -0.865 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.242 ; 1.610 ; -; -0.861 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.807 ; -; -0.859 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.244 ; 1.602 ; -; -0.858 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.806 ; -; -0.857 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.803 ; -; -0.856 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.804 ; -; -0.855 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.801 ; -; -0.845 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.791 ; -; -0.844 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.790 ; -; -0.843 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.789 ; -; -0.840 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.786 ; -; -0.840 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.786 ; -; -0.838 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.784 ; -; -0.834 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.782 ; -; -0.832 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.780 ; -; -0.831 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.779 ; -; -0.829 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.244 ; 1.572 ; -; -0.823 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.771 ; -; -0.821 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.769 ; -; -0.815 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.763 ; -; -0.812 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.760 ; -; -0.804 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.752 ; -; -0.799 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.747 ; -; -0.797 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.745 ; -; -0.794 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.242 ; 1.539 ; -; -0.793 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.741 ; -; -0.791 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.739 ; -; -0.788 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.736 ; -; -0.785 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.733 ; -; -0.776 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.722 ; -; -0.773 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.719 ; -; -0.772 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.718 ; -; -0.771 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.719 ; -; -0.770 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.718 ; -; -0.769 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.715 ; -; -0.768 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.716 ; -; -0.768 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.716 ; -; -0.766 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.714 ; -; -0.763 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.709 ; -; -0.763 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.711 ; -; -0.761 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.709 ; -; -0.760 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.708 ; -; -0.753 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.699 ; -; -0.752 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.700 ; -; -0.752 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.039 ; 1.700 ; -; -0.751 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.041 ; 1.697 ; +; -1.676 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.619 ; +; -1.674 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.617 ; +; -1.622 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.567 ; +; -1.603 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.548 ; +; -1.602 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.545 ; +; -1.601 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.546 ; +; -1.601 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.544 ; +; -1.569 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.514 ; +; -1.559 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.504 ; +; -1.539 ; FreqDivider:inst2|s_counter[18] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.482 ; +; -1.536 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.479 ; +; -1.526 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.469 ; +; -1.503 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.446 ; +; -1.493 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.438 ; +; -1.471 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.414 ; +; -1.465 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.408 ; +; -1.458 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.401 ; +; -1.454 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.397 ; +; -1.441 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.386 ; +; -1.292 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.237 ; +; -1.286 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.229 ; +; -1.229 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.174 ; +; -1.222 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.167 ; +; -1.213 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.158 ; +; -1.179 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.122 ; +; -1.122 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.065 ; +; -1.107 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.052 ; +; -1.103 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 2.046 ; +; -1.086 ; FreqDivider:inst2|s_counter[14] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 2.031 ; +; -1.053 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.998 ; +; -1.031 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.976 ; +; -0.939 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|clkOut ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.884 ; +; -0.893 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.836 ; +; -0.879 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.822 ; +; -0.847 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.790 ; +; -0.843 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.786 ; +; -0.833 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.776 ; +; -0.822 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.765 ; +; -0.822 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.765 ; +; -0.812 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.755 ; +; -0.808 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.753 ; +; -0.808 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.751 ; +; -0.801 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.744 ; +; -0.800 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.743 ; +; -0.799 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.742 ; +; -0.798 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.741 ; +; -0.796 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.739 ; +; -0.795 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.738 ; +; -0.785 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.728 ; +; -0.779 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.722 ; +; -0.776 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.719 ; +; -0.775 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.718 ; +; -0.772 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.715 ; +; -0.768 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.711 ; +; -0.766 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.709 ; +; -0.765 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.708 ; +; -0.763 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.706 ; +; -0.760 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.705 ; +; -0.757 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.700 ; +; -0.754 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.697 ; +; -0.754 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.697 ; +; -0.747 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.692 ; +; -0.746 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.691 ; +; -0.744 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.689 ; +; -0.743 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.686 ; +; -0.741 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.684 ; +; -0.737 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.682 ; +; -0.737 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.680 ; +; -0.728 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.671 ; +; -0.728 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.673 ; +; -0.727 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.670 ; +; -0.727 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.672 ; +; -0.727 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.670 ; +; -0.726 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.669 ; +; -0.726 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.671 ; +; -0.726 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.669 ; +; -0.725 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.670 ; +; -0.725 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.670 ; +; -0.725 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.668 ; +; -0.724 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.667 ; +; -0.723 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.668 ; +; -0.723 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.666 ; +; -0.717 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.660 ; +; -0.714 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[14] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.657 ; +; -0.711 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.654 ; +; -0.708 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.651 ; +; -0.708 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.651 ; +; -0.707 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.650 ; +; -0.704 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.647 ; +; -0.704 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.647 ; +; -0.698 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[16] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.641 ; +; -0.698 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.641 ; +; -0.698 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.641 ; +; -0.697 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.640 ; +; -0.694 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.639 ; +; -0.693 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[18] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.638 ; +; -0.693 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.638 ; +; -0.692 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[23] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.635 ; +; -0.691 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[21] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.042 ; 1.636 ; +; -0.690 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 1.000 ; -0.044 ; 1.633 ; +--------+---------------------------------+---------------------------------+--------------+-------------+--------------+------------+------------+ @@ -1268,106 +1268,106 @@ No paths to report. +--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ -; -0.171 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.311 ; -; -0.124 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.264 ; -; -0.107 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.247 ; -; -0.103 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.243 ; -; -0.099 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.239 ; -; -0.096 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 1.043 ; -; -0.093 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.233 ; -; -0.092 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 1.039 ; -; -0.082 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 1.029 ; -; -0.056 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.196 ; -; -0.055 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.195 ; -; -0.045 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.992 ; -; -0.039 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.179 ; -; -0.035 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.175 ; -; -0.035 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.175 ; +; -0.170 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.311 ; +; -0.123 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.264 ; +; -0.106 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.247 ; +; -0.102 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.243 ; +; -0.102 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 1.039 ; +; -0.098 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.239 ; +; -0.092 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.233 ; +; -0.055 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.196 ; +; -0.054 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.991 ; +; -0.054 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.195 ; +; -0.038 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.179 ; +; -0.038 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.975 ; +; -0.034 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.175 ; +; -0.034 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.175 ; +; -0.034 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.971 ; ; -0.032 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.969 ; -; -0.032 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.172 ; -; -0.031 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.171 ; -; -0.030 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.975 ; -; -0.026 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.971 ; -; -0.026 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.166 ; -; -0.025 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.165 ; -; -0.024 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.971 ; -; -0.020 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.967 ; -; -0.016 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.961 ; -; -0.015 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.962 ; -; 0.012 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.128 ; +; -0.031 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.172 ; +; -0.030 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.171 ; +; -0.029 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.975 ; +; -0.025 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.971 ; +; -0.025 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.166 ; +; -0.024 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.961 ; +; -0.024 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.165 ; +; -0.015 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.961 ; ; 0.013 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.924 ; -; 0.013 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.127 ; -; 0.013 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.127 ; -; 0.021 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.924 ; -; 0.024 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.923 ; -; 0.029 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.111 ; +; 0.013 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.128 ; +; 0.014 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.127 ; +; 0.014 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.923 ; +; 0.014 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.127 ; +; 0.022 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.924 ; +; 0.030 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.111 ; +; 0.030 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.907 ; ; 0.032 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.905 ; -; 0.032 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.108 ; -; 0.033 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.107 ; -; 0.033 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.107 ; +; 0.033 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.108 ; +; 0.034 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.107 ; +; 0.034 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.107 ; +; 0.034 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.903 ; ; 0.036 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.901 ; ; 0.036 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.901 ; -; 0.036 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.104 ; -; 0.037 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.103 ; -; 0.037 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.103 ; -; 0.038 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.907 ; -; 0.042 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.903 ; -; 0.042 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.098 ; -; 0.042 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.903 ; -; 0.042 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.098 ; -; 0.043 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.904 ; +; 0.037 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.104 ; +; 0.038 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.103 ; +; 0.038 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.103 ; +; 0.039 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.907 ; +; 0.043 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.903 ; ; 0.043 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.894 ; -; 0.043 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.097 ; -; 0.046 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.899 ; -; 0.047 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.900 ; -; 0.051 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.894 ; -; 0.052 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.893 ; -; 0.053 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.894 ; -; 0.080 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.060 ; +; 0.043 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.098 ; +; 0.043 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.903 ; +; 0.043 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.098 ; +; 0.044 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.893 ; +; 0.044 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.097 ; +; 0.047 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.899 ; +; 0.052 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.894 ; +; 0.053 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.893 ; ; 0.081 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.856 ; -; 0.081 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.059 ; ; 0.081 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.856 ; -; 0.081 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.059 ; -; 0.081 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.059 ; -; 0.089 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.856 ; -; 0.090 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.855 ; -; 0.092 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.855 ; +; 0.081 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.060 ; +; 0.082 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.059 ; +; 0.082 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.059 ; +; 0.082 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.855 ; +; 0.082 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.059 ; +; 0.090 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.856 ; +; 0.091 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.855 ; +; 0.098 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.043 ; +; 0.098 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.839 ; ; 0.100 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.837 ; -; 0.100 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.152 ; 1.039 ; ; 0.100 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.837 ; ; 0.100 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.837 ; -; 0.100 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.040 ; -; 0.101 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.039 ; -; 0.101 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.039 ; +; 0.101 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.040 ; +; 0.102 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.039 ; +; 0.102 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.039 ; +; 0.102 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.039 ; +; 0.102 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.835 ; ; 0.104 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.833 ; ; 0.104 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.833 ; -; 0.104 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.036 ; -; 0.105 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.035 ; -; 0.105 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.035 ; -; 0.106 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.839 ; -; 0.109 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.836 ; -; 0.110 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.835 ; -; 0.110 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.030 ; -; 0.110 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.835 ; -; 0.110 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.030 ; +; 0.105 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.036 ; +; 0.106 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.035 ; +; 0.106 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.035 ; +; 0.107 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.839 ; +; 0.110 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.836 ; +; 0.111 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.835 ; ; 0.111 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.826 ; -; 0.111 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 1.029 ; ; 0.111 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.826 ; -; 0.112 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.835 ; -; 0.113 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.832 ; -; 0.114 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.831 ; -; 0.116 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.831 ; -; 0.119 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.826 ; -; 0.119 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.826 ; -; 0.120 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.042 ; 0.825 ; -; 0.122 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.040 ; 0.825 ; -; 0.148 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.152 ; 0.991 ; +; 0.111 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.030 ; +; 0.111 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.835 ; +; 0.111 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.030 ; +; 0.112 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.029 ; +; 0.112 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.825 ; +; 0.112 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 1.029 ; +; 0.114 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.832 ; +; 0.115 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.831 ; +; 0.120 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.826 ; +; 0.120 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.826 ; +; 0.121 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.041 ; 0.825 ; ; 0.149 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.788 ; -; 0.149 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 0.991 ; ; 0.149 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.788 ; -; 0.149 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 0.991 ; -; 0.149 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.153 ; 0.991 ; +; 0.149 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 0.992 ; ; 0.150 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.787 ; +; 0.150 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 0.991 ; +; 0.150 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; 0.154 ; 0.991 ; +; 0.150 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 1.000 ; -0.050 ; 0.787 ; +--------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ @@ -1376,106 +1376,106 @@ No paths to report. +-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ -; 0.247 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.574 ; -; 0.260 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.587 ; +; 0.244 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.573 ; +; 0.258 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.587 ; ; 0.291 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.425 ; +; 0.291 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.425 ; ; 0.292 ; AccN:inst|RegN:reg|dataOut[16] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.426 ; ; 0.292 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.426 ; ; 0.292 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.426 ; ; 0.292 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.426 ; +; 0.292 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.426 ; ; 0.293 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.427 ; ; 0.293 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.427 ; -; 0.299 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.425 ; -; 0.299 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.425 ; -; 0.299 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.425 ; -; 0.300 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.425 ; -; 0.300 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.426 ; -; 0.300 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.426 ; -; 0.300 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.426 ; -; 0.301 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.426 ; -; 0.301 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.427 ; -; 0.306 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[0] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.432 ; +; 0.300 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.425 ; +; 0.300 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.425 ; +; 0.300 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.425 ; +; 0.301 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.426 ; +; 0.301 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.426 ; +; 0.301 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.426 ; +; 0.302 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.427 ; +; 0.307 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[0] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.432 ; +; 0.307 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.636 ; +; 0.310 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.639 ; ; 0.310 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.639 ; -; 0.310 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.637 ; -; 0.313 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.640 ; -; 0.323 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.650 ; +; 0.321 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.650 ; ; 0.324 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.653 ; -; 0.326 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.653 ; +; 0.325 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.654 ; ; 0.373 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.702 ; -; 0.376 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.703 ; -; 0.376 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.705 ; +; 0.373 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.702 ; ; 0.376 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.705 ; -; 0.379 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.706 ; +; 0.376 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.705 ; +; 0.377 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.706 ; ; 0.387 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.716 ; -; 0.389 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.716 ; +; 0.388 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.717 ; ; 0.390 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.719 ; ; 0.391 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.720 ; -; 0.392 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.719 ; -; 0.439 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.768 ; +; 0.391 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.720 ; ; 0.439 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.768 ; -; 0.440 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.574 ; +; 0.439 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.768 ; ; 0.440 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.574 ; +; 0.440 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.574 ; +; 0.440 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.574 ; +; 0.440 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.769 ; ; 0.441 ; AccN:inst|RegN:reg|dataOut[15] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.575 ; -; 0.442 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.769 ; ; 0.442 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.771 ; ; 0.442 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.771 ; ; 0.443 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.772 ; -; 0.445 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.772 ; -; 0.446 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.043 ; 0.573 ; -; 0.447 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.573 ; -; 0.448 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.574 ; -; 0.449 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.575 ; +; 0.444 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.773 ; +; 0.448 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.573 ; +; 0.449 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.574 ; ; 0.450 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.584 ; +; 0.450 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.575 ; +; 0.450 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.584 ; ; 0.451 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.585 ; ; 0.452 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.586 ; +; 0.453 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.587 ; ; 0.453 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.782 ; ; 0.453 ; AccN:inst|RegN:reg|dataOut[14] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.587 ; ; 0.454 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.588 ; ; 0.454 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.783 ; +; 0.454 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.783 ; ; 0.455 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.589 ; -; 0.455 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.782 ; ; 0.456 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.785 ; ; 0.457 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.786 ; ; 0.457 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.786 ; -; 0.458 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.584 ; -; 0.458 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.243 ; 0.785 ; -; 0.459 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.585 ; -; 0.459 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.585 ; -; 0.459 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.584 ; -; 0.459 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.585 ; -; 0.460 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.043 ; 0.587 ; -; 0.462 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.588 ; -; 0.462 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.588 ; -; 0.462 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.588 ; +; 0.457 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.786 ; +; 0.459 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.584 ; +; 0.460 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.585 ; +; 0.460 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.585 ; +; 0.460 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[1] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.585 ; +; 0.463 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.588 ; +; 0.463 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.588 ; +; 0.463 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[2] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.588 ; +; 0.503 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.637 ; ; 0.503 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.637 ; ; 0.503 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.637 ; ; 0.505 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.834 ; ; 0.505 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.834 ; +; 0.506 ; AccN:inst|RegN:reg|dataOut[9] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.640 ; ; 0.506 ; AccN:inst|RegN:reg|dataOut[11] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.640 ; ; 0.506 ; AccN:inst|RegN:reg|dataOut[13] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.640 ; ; 0.506 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.835 ; +; 0.507 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.836 ; ; 0.508 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.837 ; ; 0.508 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.837 ; ; 0.509 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.838 ; -; 0.509 ; AccN:inst|RegN:reg|dataOut[7] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.043 ; 0.636 ; ; 0.510 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[10] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.839 ; -; 0.510 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.636 ; -; 0.511 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.637 ; -; 0.512 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.638 ; -; 0.512 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[8] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.043 ; 0.639 ; -; 0.514 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.640 ; -; 0.515 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.042 ; 0.641 ; +; 0.511 ; AccN:inst|RegN:reg|dataOut[5] ; AccN:inst|RegN:reg|dataOut[7] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.636 ; +; 0.512 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[5] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.637 ; +; 0.513 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[3] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.638 ; +; 0.515 ; AccN:inst|RegN:reg|dataOut[3] ; AccN:inst|RegN:reg|dataOut[6] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.640 ; +; 0.516 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.650 ; +; 0.516 ; AccN:inst|RegN:reg|dataOut[1] ; AccN:inst|RegN:reg|dataOut[4] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.041 ; 0.641 ; ; 0.517 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.651 ; ; 0.518 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.652 ; +; 0.519 ; AccN:inst|RegN:reg|dataOut[8] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.653 ; ; 0.519 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[15] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.848 ; ; 0.520 ; AccN:inst|RegN:reg|dataOut[10] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.654 ; ; 0.520 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[13] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.849 ; ; 0.520 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[11] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.849 ; +; 0.520 ; AccN:inst|RegN:reg|dataOut[0] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.849 ; ; 0.521 ; AccN:inst|RegN:reg|dataOut[12] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.050 ; 0.655 ; -; 0.522 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[16] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.851 ; -; 0.523 ; AccN:inst|RegN:reg|dataOut[4] ; AccN:inst|RegN:reg|dataOut[14] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.852 ; -; 0.523 ; AccN:inst|RegN:reg|dataOut[2] ; AccN:inst|RegN:reg|dataOut[12] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.245 ; 0.852 ; -; 0.523 ; AccN:inst|RegN:reg|dataOut[6] ; AccN:inst|RegN:reg|dataOut[9] ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 0.000 ; 0.043 ; 0.650 ; +-------+--------------------------------+--------------------------------+--------------------------+--------------------------+--------------+------------+------------+ @@ -1484,106 +1484,106 @@ No paths to report. +-------+---------------------------------+---------------------------------+--------------------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+---------------------------------+---------------------------------+--------------------------+-------------+--------------+------------+------------+ -; 0.298 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.423 ; -; 0.299 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.424 ; -; 0.299 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.424 ; -; 0.299 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.424 ; -; 0.299 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.424 ; -; 0.300 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.425 ; -; 0.300 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.425 ; -; 0.300 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.425 ; -; 0.300 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.425 ; -; 0.301 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.426 ; -; 0.301 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.426 ; -; 0.301 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.426 ; -; 0.301 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.426 ; -; 0.301 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.426 ; -; 0.302 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.427 ; -; 0.302 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.427 ; -; 0.302 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.427 ; -; 0.302 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.427 ; -; 0.302 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.050 ; 0.436 ; -; 0.303 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.428 ; -; 0.303 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.428 ; -; 0.448 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.573 ; -; 0.448 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.573 ; -; 0.449 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.574 ; -; 0.449 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.574 ; -; 0.449 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.574 ; -; 0.450 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.575 ; -; 0.450 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.575 ; -; 0.459 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.584 ; -; 0.459 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.584 ; -; 0.460 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.585 ; -; 0.460 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.585 ; -; 0.461 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.586 ; -; 0.461 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.586 ; -; 0.462 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.587 ; -; 0.462 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.587 ; -; 0.463 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.588 ; -; 0.464 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.589 ; -; 0.464 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.589 ; -; 0.490 ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; CLOCK_50 ; 0.000 ; 1.635 ; 2.344 ; -; 0.510 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.635 ; -; 0.511 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.636 ; -; 0.511 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.636 ; -; 0.511 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.636 ; -; 0.512 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.637 ; -; 0.512 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.637 ; -; 0.512 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.637 ; -; 0.513 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.638 ; -; 0.514 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.639 ; -; 0.514 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.639 ; -; 0.515 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.640 ; -; 0.515 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.640 ; -; 0.515 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.640 ; -; 0.516 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.641 ; -; 0.517 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.640 ; -; 0.520 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.643 ; -; 0.525 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.650 ; -; 0.525 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.650 ; -; 0.526 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.651 ; -; 0.527 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.650 ; -; 0.527 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.652 ; -; 0.527 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.652 ; -; 0.528 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.653 ; -; 0.529 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.652 ; -; 0.529 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.654 ; -; 0.530 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.653 ; -; 0.530 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.655 ; -; 0.541 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.664 ; -; 0.544 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.667 ; -; 0.577 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.702 ; -; 0.577 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.702 ; -; 0.577 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.702 ; -; 0.578 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.703 ; -; 0.579 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.702 ; -; 0.579 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.704 ; -; 0.579 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.704 ; -; 0.580 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.705 ; -; 0.580 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.705 ; -; 0.581 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.706 ; -; 0.582 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.707 ; -; 0.583 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.706 ; -; 0.587 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[19] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.712 ; -; 0.591 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.716 ; -; 0.591 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.716 ; -; 0.592 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.717 ; -; 0.592 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.717 ; -; 0.592 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.717 ; -; 0.593 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.716 ; -; 0.593 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.718 ; -; 0.594 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.719 ; -; 0.594 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.719 ; -; 0.595 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.720 ; -; 0.595 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.720 ; -; 0.596 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.719 ; -; 0.598 ; FreqDivider:inst2|s_counter[11] ; FreqDivider:inst2|s_counter[11] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.723 ; -; 0.598 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.721 ; -; 0.601 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.041 ; 0.726 ; -; 0.607 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.730 ; -; 0.609 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.732 ; -; 0.610 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.039 ; 0.733 ; +; 0.297 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.423 ; +; 0.298 ; FreqDivider:inst2|s_counter[31] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.424 ; +; 0.298 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.424 ; +; 0.298 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.424 ; +; 0.299 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ; +; 0.299 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ; +; 0.299 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ; +; 0.299 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ; +; 0.299 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.425 ; +; 0.300 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ; +; 0.300 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ; +; 0.300 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ; +; 0.300 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.426 ; +; 0.301 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ; +; 0.301 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ; +; 0.301 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ; +; 0.301 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ; +; 0.301 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.427 ; +; 0.302 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.428 ; +; 0.302 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.428 ; +; 0.310 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[0] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.436 ; +; 0.447 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.573 ; +; 0.448 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ; +; 0.448 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ; +; 0.448 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ; +; 0.448 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.574 ; +; 0.449 ; FreqDivider:inst2|s_counter[9] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.575 ; +; 0.457 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[1] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.583 ; +; 0.458 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.584 ; +; 0.458 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.584 ; +; 0.459 ; FreqDivider:inst2|s_counter[30] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.585 ; +; 0.459 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.585 ; +; 0.460 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.586 ; +; 0.460 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.586 ; +; 0.460 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[2] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.586 ; +; 0.461 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.587 ; +; 0.461 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.587 ; +; 0.461 ; FreqDivider:inst2|s_counter[8] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.587 ; +; 0.462 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.588 ; +; 0.462 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.588 ; +; 0.463 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.589 ; +; 0.463 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.589 ; +; 0.510 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.636 ; +; 0.510 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.636 ; +; 0.511 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ; +; 0.511 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.040 ; 0.635 ; +; 0.511 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ; +; 0.511 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ; +; 0.511 ; FreqDivider:inst2|s_counter[29] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ; +; 0.511 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.637 ; +; 0.513 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.639 ; +; 0.514 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ; +; 0.514 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ; +; 0.514 ; FreqDivider:inst2|s_counter[7] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ; +; 0.514 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.640 ; +; 0.517 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.643 ; +; 0.517 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.643 ; +; 0.523 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[3] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.649 ; +; 0.524 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.650 ; +; 0.525 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.651 ; +; 0.525 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.651 ; +; 0.526 ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; CLOCK_50 ; 0.000 ; 1.647 ; 2.392 ; +; 0.526 ; FreqDivider:inst2|s_counter[16] ; FreqDivider:inst2|s_counter[17] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ; +; 0.526 ; FreqDivider:inst2|s_counter[28] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ; +; 0.526 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ; +; 0.526 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[4] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.652 ; +; 0.527 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[26] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.653 ; +; 0.528 ; FreqDivider:inst2|s_counter[20] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ; +; 0.528 ; FreqDivider:inst2|s_counter[21] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ; +; 0.528 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ; +; 0.528 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.654 ; +; 0.529 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[30] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.655 ; +; 0.533 ; FreqDivider:inst2|s_counter[23] ; FreqDivider:inst2|s_counter[24] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.659 ; +; 0.542 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.668 ; +; 0.545 ; FreqDivider:inst2|s_counter[6] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.671 ; +; 0.568 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[13] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.694 ; +; 0.576 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.702 ; +; 0.576 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.702 ; +; 0.577 ; FreqDivider:inst2|s_counter[1] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.703 ; +; 0.577 ; FreqDivider:inst2|s_counter[27] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.703 ; +; 0.579 ; FreqDivider:inst2|s_counter[5] ; FreqDivider:inst2|s_counter[10] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.705 ; +; 0.579 ; FreqDivider:inst2|s_counter[3] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.705 ; +; 0.580 ; FreqDivider:inst2|s_counter[13] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.706 ; +; 0.580 ; FreqDivider:inst2|s_counter[17] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.706 ; +; 0.580 ; FreqDivider:inst2|s_counter[15] ; FreqDivider:inst2|s_counter[20] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.040 ; 0.704 ; +; 0.580 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.706 ; +; 0.583 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.709 ; +; 0.583 ; FreqDivider:inst2|s_counter[19] ; FreqDivider:inst2|s_counter[22] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.709 ; +; 0.587 ; FreqDivider:inst2|s_counter[25] ; FreqDivider:inst2|s_counter[25] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.713 ; +; 0.589 ; FreqDivider:inst2|s_counter[0] ; FreqDivider:inst2|s_counter[5] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.715 ; +; 0.590 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[27] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.716 ; +; 0.590 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[7] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.716 ; +; 0.591 ; FreqDivider:inst2|s_counter[24] ; FreqDivider:inst2|s_counter[29] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.717 ; +; 0.591 ; FreqDivider:inst2|s_counter[4] ; FreqDivider:inst2|s_counter[9] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.717 ; +; 0.591 ; FreqDivider:inst2|s_counter[10] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.717 ; +; 0.592 ; FreqDivider:inst2|s_counter[26] ; FreqDivider:inst2|s_counter[31] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.718 ; +; 0.592 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[15] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.718 ; +; 0.593 ; FreqDivider:inst2|s_counter[22] ; FreqDivider:inst2|s_counter[28] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.719 ; +; 0.593 ; FreqDivider:inst2|s_counter[2] ; FreqDivider:inst2|s_counter[8] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.719 ; +; 0.594 ; FreqDivider:inst2|s_counter[12] ; FreqDivider:inst2|s_counter[12] ; CLOCK_50 ; CLOCK_50 ; 0.000 ; 0.042 ; 0.720 ; +-------+---------------------------------+---------------------------------+--------------------------+-------------+--------------+------------+------------+ @@ -1598,12 +1598,12 @@ No synchronizer chains to report. +---------------------------+---------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +---------------------------+---------+-------+----------+---------+---------------------+ -; Worst-case Slack ; -4.190 ; 0.247 ; N/A ; N/A ; -3.000 ; -; CLOCK_50 ; -4.190 ; 0.298 ; N/A ; N/A ; -3.000 ; -; FreqDivider:inst2|clkOut ; -1.348 ; 0.247 ; N/A ; N/A ; -1.285 ; -; Design-wide TNS ; -95.668 ; 0.0 ; 0.0 ; 0.0 ; -67.25 ; -; CLOCK_50 ; -78.512 ; 0.000 ; N/A ; N/A ; -45.405 ; -; FreqDivider:inst2|clkOut ; -17.156 ; 0.000 ; N/A ; N/A ; -21.845 ; +; Worst-case Slack ; -4.308 ; 0.244 ; N/A ; N/A ; -3.000 ; +; CLOCK_50 ; -4.308 ; 0.297 ; N/A ; N/A ; -3.000 ; +; FreqDivider:inst2|clkOut ; -1.349 ; 0.244 ; N/A ; N/A ; -1.285 ; +; Design-wide TNS ; -82.271 ; 0.0 ; 0.0 ; 0.0 ; -67.25 ; +; CLOCK_50 ; -65.920 ; 0.000 ; N/A ; N/A ; -45.405 ; +; FreqDivider:inst2|clkOut ; -16.351 ; 0.000 ; N/A ; N/A ; -21.845 ; +---------------------------+---------+-------+----------+---------+---------------------+ @@ -1751,7 +1751,7 @@ No synchronizer chains to report. +--------------------------+--------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +--------------------------+--------------------------+----------+----------+----------+----------+ -; CLOCK_50 ; CLOCK_50 ; 923 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; CLOCK_50 ; 925 ; 0 ; 0 ; 0 ; ; FreqDivider:inst2|clkOut ; CLOCK_50 ; 1 ; 1 ; 0 ; 0 ; ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 153 ; 0 ; 0 ; 0 ; +--------------------------+--------------------------+----------+----------+----------+----------+ @@ -1763,7 +1763,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +--------------------------+--------------------------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +--------------------------+--------------------------+----------+----------+----------+----------+ -; CLOCK_50 ; CLOCK_50 ; 923 ; 0 ; 0 ; 0 ; +; CLOCK_50 ; CLOCK_50 ; 925 ; 0 ; 0 ; 0 ; ; FreqDivider:inst2|clkOut ; CLOCK_50 ; 1 ; 1 ; 0 ; 0 ; ; FreqDivider:inst2|clkOut ; FreqDivider:inst2|clkOut ; 153 ; 0 ; 0 ; 0 ; +--------------------------+--------------------------+----------+----------+----------+----------+ @@ -1916,7 +1916,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Wed Mar 22 12:51:08 2023 + Info: Processing started: Tue Mar 28 15:22:11 2023 Info: Command: quartus_sta AccN_Demo -c AccN_Demo Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -1934,16 +1934,16 @@ Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. -Info (332146): Worst-case setup slack is -4.190 +Info (332146): Worst-case setup slack is -4.308 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -4.190 -78.512 CLOCK_50 - Info (332119): -1.348 -17.156 FreqDivider:inst2|clkOut -Info (332146): Worst-case hold slack is 0.548 + Info (332119): -4.308 -65.920 CLOCK_50 + Info (332119): -1.349 -16.351 FreqDivider:inst2|clkOut +Info (332146): Worst-case hold slack is 0.543 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.548 0.000 FreqDivider:inst2|clkOut - Info (332119): 0.654 0.000 CLOCK_50 + Info (332119): 0.543 0.000 FreqDivider:inst2|clkOut + Info (332119): 0.653 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 @@ -1957,16 +1957,16 @@ Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. -Info (332146): Worst-case setup slack is -3.751 +Info (332146): Worst-case setup slack is -3.850 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.751 -67.496 CLOCK_50 - Info (332119): -1.082 -13.558 FreqDivider:inst2|clkOut -Info (332146): Worst-case hold slack is 0.494 + Info (332119): -3.850 -55.792 CLOCK_50 + Info (332119): -1.081 -12.785 FreqDivider:inst2|clkOut +Info (332146): Worst-case hold slack is 0.489 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.494 0.000 FreqDivider:inst2|clkOut - Info (332119): 0.597 0.000 CLOCK_50 + Info (332119): 0.489 0.000 FreqDivider:inst2|clkOut + Info (332119): 0.598 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 @@ -1978,28 +1978,28 @@ Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Critical Warning (332148): Timing requirements not met Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer. -Info (332146): Worst-case setup slack is -1.596 +Info (332146): Worst-case setup slack is -1.676 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -1.596 -21.945 CLOCK_50 - Info (332119): -0.171 -0.699 FreqDivider:inst2|clkOut -Info (332146): Worst-case hold slack is 0.247 + Info (332119): -1.676 -16.763 CLOCK_50 + Info (332119): -0.170 -0.504 FreqDivider:inst2|clkOut +Info (332146): Worst-case hold slack is 0.244 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): 0.247 0.000 FreqDivider:inst2|clkOut - Info (332119): 0.298 0.000 CLOCK_50 + Info (332119): 0.244 0.000 FreqDivider:inst2|clkOut + Info (332119): 0.297 0.000 CLOCK_50 Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is -3.000 Info (332119): Slack End Point TNS Clock Info (332119): ========= =================== ===================== - Info (332119): -3.000 -38.002 CLOCK_50 + Info (332119): -3.000 -38.036 CLOCK_50 Info (332119): -1.000 -17.000 FreqDivider:inst2|clkOut Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings Info: Peak virtual memory: 537 megabytes - Info: Processing ended: Wed Mar 22 12:51:09 2023 + Info: Processing ended: Tue Mar 28 15:22:12 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.summary b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.summary index e4bb16f..3297e55 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.summary +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/output_files/AccN_Demo.sta.summary @@ -3,19 +3,19 @@ Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'CLOCK_50' -Slack : -4.190 -TNS : -78.512 +Slack : -4.308 +TNS : -65.920 Type : Slow 1200mV 85C Model Setup 'FreqDivider:inst2|clkOut' -Slack : -1.348 -TNS : -17.156 +Slack : -1.349 +TNS : -16.351 Type : Slow 1200mV 85C Model Hold 'FreqDivider:inst2|clkOut' -Slack : 0.548 +Slack : 0.543 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'CLOCK_50' -Slack : 0.654 +Slack : 0.653 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' @@ -27,19 +27,19 @@ Slack : -1.285 TNS : -21.845 Type : Slow 1200mV 0C Model Setup 'CLOCK_50' -Slack : -3.751 -TNS : -67.496 +Slack : -3.850 +TNS : -55.792 Type : Slow 1200mV 0C Model Setup 'FreqDivider:inst2|clkOut' -Slack : -1.082 -TNS : -13.558 +Slack : -1.081 +TNS : -12.785 Type : Slow 1200mV 0C Model Hold 'FreqDivider:inst2|clkOut' -Slack : 0.494 +Slack : 0.489 TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.597 +Slack : 0.598 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' @@ -51,24 +51,24 @@ Slack : -1.285 TNS : -21.845 Type : Fast 1200mV 0C Model Setup 'CLOCK_50' -Slack : -1.596 -TNS : -21.945 +Slack : -1.676 +TNS : -16.763 Type : Fast 1200mV 0C Model Setup 'FreqDivider:inst2|clkOut' -Slack : -0.171 -TNS : -0.699 +Slack : -0.170 +TNS : -0.504 Type : Fast 1200mV 0C Model Hold 'FreqDivider:inst2|clkOut' -Slack : 0.247 +Slack : 0.244 TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'CLOCK_50' -Slack : 0.298 +Slack : 0.297 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' Slack : -3.000 -TNS : -38.002 +TNS : -38.036 Type : Fast 1200mV 0C Model Minimum Pulse Width 'FreqDivider:inst2|clkOut' Slack : -1.000 diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.vho b/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.vho index 0ed80d6..040c504 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.vho +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo.vho @@ -17,7 +17,7 @@ -- PROGRAM "Quartus Prime" -- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" --- DATE "03/22/2023 12:51:10" +-- DATE "03/28/2023 15:22:13" -- -- Device: Altera EP4CE115F29C7 Package FBGA780 @@ -170,7 +170,6 @@ SIGNAL \inst2|Add2~5\ : std_logic; SIGNAL \inst2|Add2~6_combout\ : std_logic; SIGNAL \inst2|Add2~7\ : std_logic; SIGNAL \inst2|Add2~8_combout\ : std_logic; -SIGNAL \inst2|Equal0~5_combout\ : std_logic; SIGNAL \inst2|Add2~9\ : std_logic; SIGNAL \inst2|Add2~10_combout\ : std_logic; SIGNAL \inst2|Add2~11\ : std_logic; @@ -178,6 +177,7 @@ SIGNAL \inst2|Add2~12_combout\ : std_logic; SIGNAL \inst2|s_counter~10_combout\ : std_logic; SIGNAL \inst2|Add2~13\ : std_logic; SIGNAL \inst2|Add2~14_combout\ : std_logic; +SIGNAL \inst2|Equal0~3_combout\ : std_logic; SIGNAL \inst2|Add2~15\ : std_logic; SIGNAL \inst2|Add2~16_combout\ : std_logic; SIGNAL \inst2|Add2~17\ : std_logic; @@ -190,44 +190,36 @@ SIGNAL \inst2|s_counter~9_combout\ : std_logic; SIGNAL \inst2|Add2~23\ : std_logic; SIGNAL \inst2|Add2~24_combout\ : std_logic; SIGNAL \inst2|s_counter~8_combout\ : std_logic; +SIGNAL \inst2|Equal0~2_combout\ : std_logic; SIGNAL \inst2|Add2~25\ : std_logic; SIGNAL \inst2|Add2~26_combout\ : std_logic; SIGNAL \inst2|s_counter~7_combout\ : std_logic; SIGNAL \inst2|Add2~27\ : std_logic; SIGNAL \inst2|Add2~28_combout\ : std_logic; -SIGNAL \inst2|s_counter~4_combout\ : std_logic; +SIGNAL \inst2|s_counter~5_combout\ : std_logic; SIGNAL \inst2|Add2~29\ : std_logic; SIGNAL \inst2|Add2~30_combout\ : std_logic; SIGNAL \inst2|Add2~31\ : std_logic; SIGNAL \inst2|Add2~32_combout\ : std_logic; -SIGNAL \inst2|s_counter~3_combout\ : std_logic; +SIGNAL \inst2|s_counter~4_combout\ : std_logic; SIGNAL \inst2|Add2~33\ : std_logic; SIGNAL \inst2|Add2~34_combout\ : std_logic; SIGNAL \inst2|Add2~35\ : std_logic; SIGNAL \inst2|Add2~36_combout\ : std_logic; SIGNAL \inst2|s_counter~6_combout\ : std_logic; -SIGNAL \inst2|Equal0~2_combout\ : std_logic; -SIGNAL \inst2|Equal0~3_combout\ : std_logic; -SIGNAL \inst2|Add2~37\ : std_logic; -SIGNAL \inst2|Add2~38_combout\ : std_logic; -SIGNAL \inst2|s_counter~2_combout\ : std_logic; -SIGNAL \inst2|Add2~39\ : std_logic; -SIGNAL \inst2|Add2~40_combout\ : std_logic; -SIGNAL \inst2|Add2~41\ : std_logic; -SIGNAL \inst2|Add2~43\ : std_logic; -SIGNAL \inst2|Add2~44_combout\ : std_logic; SIGNAL \inst2|Add2~45\ : std_logic; SIGNAL \inst2|Add2~46_combout\ : std_logic; -SIGNAL \inst2|s_counter~5_combout\ : std_logic; +SIGNAL \inst2|s_counter~1_combout\ : std_logic; SIGNAL \inst2|Add2~47\ : std_logic; SIGNAL \inst2|Add2~48_combout\ : std_logic; -SIGNAL \inst2|s_counter~0_combout\ : std_logic; SIGNAL \inst2|Add2~49\ : std_logic; SIGNAL \inst2|Add2~50_combout\ : std_logic; +SIGNAL \inst2|s_counter~0_combout\ : std_logic; SIGNAL \inst2|Add2~51\ : std_logic; SIGNAL \inst2|Add2~52_combout\ : std_logic; SIGNAL \inst2|Add2~53\ : std_logic; SIGNAL \inst2|Add2~54_combout\ : std_logic; +SIGNAL \inst2|Equal0~1_combout\ : std_logic; SIGNAL \inst2|Add2~55\ : std_logic; SIGNAL \inst2|Add2~56_combout\ : std_logic; SIGNAL \inst2|Add2~57\ : std_logic; @@ -237,22 +229,27 @@ SIGNAL \inst2|Add2~60_combout\ : std_logic; SIGNAL \inst2|Add2~61\ : std_logic; SIGNAL \inst2|Add2~62_combout\ : std_logic; SIGNAL \inst2|Equal0~0_combout\ : std_logic; -SIGNAL \inst2|Equal0~1_combout\ : std_logic; SIGNAL \inst2|Equal0~4_combout\ : std_logic; -SIGNAL \inst2|Equal0~11_combout\ : std_logic; +SIGNAL \inst2|Equal0~5_combout\ : std_logic; +SIGNAL \inst2|Add2~37\ : std_logic; +SIGNAL \inst2|Add2~39\ : std_logic; +SIGNAL \inst2|Add2~40_combout\ : std_logic; +SIGNAL \inst2|Add2~41\ : std_logic; SIGNAL \inst2|Add2~42_combout\ : std_logic; -SIGNAL \inst2|s_counter~1_combout\ : std_logic; +SIGNAL \inst2|s_counter~2_combout\ : std_logic; +SIGNAL \inst2|Add2~43\ : std_logic; +SIGNAL \inst2|Add2~44_combout\ : std_logic; +SIGNAL \inst2|Equal0~6_combout\ : std_logic; SIGNAL \inst2|Equal0~7_combout\ : std_logic; SIGNAL \inst2|Equal0~8_combout\ : std_logic; SIGNAL \inst2|Equal0~9_combout\ : std_logic; -SIGNAL \inst2|Equal0~10_combout\ : std_logic; -SIGNAL \inst2|clkOut~0_combout\ : std_logic; -SIGNAL \inst2|clkOut~2_combout\ : std_logic; +SIGNAL \inst2|Add2~38_combout\ : std_logic; +SIGNAL \inst2|s_counter~3_combout\ : std_logic; SIGNAL \inst2|clkOut~1_combout\ : std_logic; +SIGNAL \inst2|clkOut~2_combout\ : std_logic; +SIGNAL \inst2|clkOut~0_combout\ : std_logic; SIGNAL \inst2|clkOut~3_combout\ : std_logic; -SIGNAL \inst2|Equal0~6_combout\ : std_logic; SIGNAL \inst2|clkOut~4_combout\ : std_logic; -SIGNAL \inst2|clkOut~feeder_combout\ : std_logic; SIGNAL \inst2|clkOut~q\ : std_logic; SIGNAL \inst2|clkOut~clkctrl_outclk\ : std_logic; SIGNAL \SW[16]~input_o\ : std_logic; @@ -564,7 +561,7 @@ PORT MAP ( devpor => ww_devpor, outclk => \CLOCK_50~inputclkctrl_outclk\); --- Location: LCCOMB_X24_Y36_N0 +-- Location: LCCOMB_X55_Y72_N0 \inst2|Add2~0\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~0_combout\ = \inst2|s_counter\(0) $ (VCC) @@ -581,7 +578,7 @@ PORT MAP ( combout => \inst2|Add2~0_combout\, cout => \inst2|Add2~1\); --- Location: FF_X24_Y36_N1 +-- Location: FF_X55_Y72_N1 \inst2|s_counter[0]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -595,7 +592,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(0)); --- Location: LCCOMB_X24_Y36_N2 +-- Location: LCCOMB_X55_Y72_N2 \inst2|Add2~2\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~2_combout\ = (\inst2|s_counter\(1) & (!\inst2|Add2~1\)) # (!\inst2|s_counter\(1) & ((\inst2|Add2~1\) # (GND))) @@ -613,7 +610,7 @@ PORT MAP ( combout => \inst2|Add2~2_combout\, cout => \inst2|Add2~3\); --- Location: FF_X24_Y36_N3 +-- Location: FF_X55_Y72_N3 \inst2|s_counter[1]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -627,7 +624,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(1)); --- Location: LCCOMB_X24_Y36_N4 +-- Location: LCCOMB_X55_Y72_N4 \inst2|Add2~4\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~4_combout\ = (\inst2|s_counter\(2) & (\inst2|Add2~3\ $ (GND))) # (!\inst2|s_counter\(2) & (!\inst2|Add2~3\ & VCC)) @@ -645,7 +642,7 @@ PORT MAP ( combout => \inst2|Add2~4_combout\, cout => \inst2|Add2~5\); --- Location: FF_X24_Y36_N5 +-- Location: FF_X55_Y72_N5 \inst2|s_counter[2]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -659,7 +656,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(2)); --- Location: LCCOMB_X24_Y36_N6 +-- Location: LCCOMB_X55_Y72_N6 \inst2|Add2~6\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~6_combout\ = (\inst2|s_counter\(3) & (!\inst2|Add2~5\)) # (!\inst2|s_counter\(3) & ((\inst2|Add2~5\) # (GND))) @@ -677,7 +674,7 @@ PORT MAP ( combout => \inst2|Add2~6_combout\, cout => \inst2|Add2~7\); --- Location: FF_X24_Y36_N7 +-- Location: FF_X55_Y72_N7 \inst2|s_counter[3]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -691,7 +688,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(3)); --- Location: LCCOMB_X24_Y36_N8 +-- Location: LCCOMB_X55_Y72_N8 \inst2|Add2~8\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~8_combout\ = (\inst2|s_counter\(4) & (\inst2|Add2~7\ $ (GND))) # (!\inst2|s_counter\(4) & (!\inst2|Add2~7\ & VCC)) @@ -709,7 +706,7 @@ PORT MAP ( combout => \inst2|Add2~8_combout\, cout => \inst2|Add2~9\); --- Location: FF_X24_Y36_N9 +-- Location: FF_X55_Y72_N9 \inst2|s_counter[4]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -723,24 +720,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(4)); --- Location: LCCOMB_X23_Y36_N28 -\inst2|Equal0~5\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|Equal0~5_combout\ = (\inst2|s_counter\(4) & (\inst2|s_counter\(3) & (\inst2|s_counter\(1) & \inst2|s_counter\(2)))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1000000000000000", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|s_counter\(4), - datab => \inst2|s_counter\(3), - datac => \inst2|s_counter\(1), - datad => \inst2|s_counter\(2), - combout => \inst2|Equal0~5_combout\); - --- Location: LCCOMB_X24_Y36_N10 +-- Location: LCCOMB_X55_Y72_N10 \inst2|Add2~10\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~10_combout\ = (\inst2|s_counter\(5) & (!\inst2|Add2~9\)) # (!\inst2|s_counter\(5) & ((\inst2|Add2~9\) # (GND))) @@ -758,7 +738,7 @@ PORT MAP ( combout => \inst2|Add2~10_combout\, cout => \inst2|Add2~11\); --- Location: FF_X24_Y36_N11 +-- Location: FF_X55_Y72_N11 \inst2|s_counter[5]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -772,7 +752,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(5)); --- Location: LCCOMB_X24_Y36_N12 +-- Location: LCCOMB_X55_Y72_N12 \inst2|Add2~12\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~12_combout\ = (\inst2|s_counter\(6) & (\inst2|Add2~11\ $ (GND))) # (!\inst2|s_counter\(6) & (!\inst2|Add2~11\ & VCC)) @@ -790,22 +770,23 @@ PORT MAP ( combout => \inst2|Add2~12_combout\, cout => \inst2|Add2~13\); --- Location: LCCOMB_X23_Y36_N6 +-- Location: LCCOMB_X56_Y72_N26 \inst2|s_counter~10\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|s_counter~10_combout\ = (\inst2|Add2~12_combout\ & !\inst2|Equal0~11_combout\) +-- \inst2|s_counter~10_combout\ = (\inst2|Add2~12_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000110000001100", + lut_mask => "0011111100000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datab => \inst2|Add2~12_combout\, - datac => \inst2|Equal0~11_combout\, + datab => \inst2|Equal0~5_combout\, + datac => \inst2|Equal0~9_combout\, + datad => \inst2|Add2~12_combout\, combout => \inst2|s_counter~10_combout\); --- Location: FF_X23_Y36_N7 +-- Location: FF_X56_Y72_N27 \inst2|s_counter[6]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -819,7 +800,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(6)); --- Location: LCCOMB_X24_Y36_N14 +-- Location: LCCOMB_X55_Y72_N14 \inst2|Add2~14\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~14_combout\ = (\inst2|s_counter\(7) & (!\inst2|Add2~13\)) # (!\inst2|s_counter\(7) & ((\inst2|Add2~13\) # (GND))) @@ -837,7 +818,7 @@ PORT MAP ( combout => \inst2|Add2~14_combout\, cout => \inst2|Add2~15\); --- Location: FF_X24_Y36_N15 +-- Location: FF_X55_Y72_N15 \inst2|s_counter[7]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -851,7 +832,24 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(7)); --- Location: LCCOMB_X24_Y36_N16 +-- Location: LCCOMB_X56_Y72_N12 +\inst2|Equal0~3\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst2|Equal0~3_combout\ = (\inst2|s_counter\(4) & (\inst2|s_counter\(3) & (!\inst2|s_counter\(6) & !\inst2|s_counter\(7)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|s_counter\(4), + datab => \inst2|s_counter\(3), + datac => \inst2|s_counter\(6), + datad => \inst2|s_counter\(7), + combout => \inst2|Equal0~3_combout\); + +-- Location: LCCOMB_X55_Y72_N16 \inst2|Add2~16\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~16_combout\ = (\inst2|s_counter\(8) & (\inst2|Add2~15\ $ (GND))) # (!\inst2|s_counter\(8) & (!\inst2|Add2~15\ & VCC)) @@ -869,7 +867,7 @@ PORT MAP ( combout => \inst2|Add2~16_combout\, cout => \inst2|Add2~17\); --- Location: FF_X24_Y36_N17 +-- Location: FF_X55_Y72_N17 \inst2|s_counter[8]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -883,7 +881,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(8)); --- Location: LCCOMB_X24_Y36_N18 +-- Location: LCCOMB_X55_Y72_N18 \inst2|Add2~18\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~18_combout\ = (\inst2|s_counter\(9) & (!\inst2|Add2~17\)) # (!\inst2|s_counter\(9) & ((\inst2|Add2~17\) # (GND))) @@ -901,7 +899,7 @@ PORT MAP ( combout => \inst2|Add2~18_combout\, cout => \inst2|Add2~19\); --- Location: FF_X24_Y36_N19 +-- Location: FF_X55_Y72_N19 \inst2|s_counter[9]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -915,7 +913,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(9)); --- Location: LCCOMB_X24_Y36_N20 +-- Location: LCCOMB_X55_Y72_N20 \inst2|Add2~20\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~20_combout\ = (\inst2|s_counter\(10) & (\inst2|Add2~19\ $ (GND))) # (!\inst2|s_counter\(10) & (!\inst2|Add2~19\ & VCC)) @@ -933,7 +931,7 @@ PORT MAP ( combout => \inst2|Add2~20_combout\, cout => \inst2|Add2~21\); --- Location: FF_X24_Y36_N21 +-- Location: FF_X55_Y72_N21 \inst2|s_counter[10]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -947,7 +945,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(10)); --- Location: LCCOMB_X24_Y36_N22 +-- Location: LCCOMB_X55_Y72_N22 \inst2|Add2~22\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~22_combout\ = (\inst2|s_counter\(11) & (!\inst2|Add2~21\)) # (!\inst2|s_counter\(11) & ((\inst2|Add2~21\) # (GND))) @@ -955,32 +953,33 @@ PORT MAP ( -- pragma translate_off GENERIC MAP ( - lut_mask => "0101101001011111", + lut_mask => "0011110000111111", sum_lutc_input => "cin") -- pragma translate_on PORT MAP ( - dataa => \inst2|s_counter\(11), + datab => \inst2|s_counter\(11), datad => VCC, cin => \inst2|Add2~21\, combout => \inst2|Add2~22_combout\, cout => \inst2|Add2~23\); --- Location: LCCOMB_X23_Y36_N14 +-- Location: LCCOMB_X56_Y72_N22 \inst2|s_counter~9\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|s_counter~9_combout\ = (!\inst2|Equal0~11_combout\ & \inst2|Add2~22_combout\) +-- \inst2|s_counter~9_combout\ = (\inst2|Add2~22_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000111100000000", + lut_mask => "0011111100000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datac => \inst2|Equal0~11_combout\, + datab => \inst2|Equal0~5_combout\, + datac => \inst2|Equal0~9_combout\, datad => \inst2|Add2~22_combout\, combout => \inst2|s_counter~9_combout\); --- Location: FF_X23_Y36_N15 +-- Location: FF_X56_Y72_N23 \inst2|s_counter[11]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -994,7 +993,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(11)); --- Location: LCCOMB_X24_Y36_N24 +-- Location: LCCOMB_X55_Y72_N24 \inst2|Add2~24\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~24_combout\ = (\inst2|s_counter\(12) & (\inst2|Add2~23\ $ (GND))) # (!\inst2|s_counter\(12) & (!\inst2|Add2~23\ & VCC)) @@ -1012,22 +1011,23 @@ PORT MAP ( combout => \inst2|Add2~24_combout\, cout => \inst2|Add2~25\); --- Location: LCCOMB_X23_Y36_N10 +-- Location: LCCOMB_X56_Y72_N20 \inst2|s_counter~8\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|s_counter~8_combout\ = (!\inst2|Equal0~11_combout\ & \inst2|Add2~24_combout\) +-- \inst2|s_counter~8_combout\ = (\inst2|Add2~24_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000111100000000", + lut_mask => "0011111100000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datac => \inst2|Equal0~11_combout\, + datab => \inst2|Equal0~5_combout\, + datac => \inst2|Equal0~9_combout\, datad => \inst2|Add2~24_combout\, combout => \inst2|s_counter~8_combout\); --- Location: FF_X23_Y36_N11 +-- Location: FF_X56_Y72_N21 \inst2|s_counter[12]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1041,7 +1041,24 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(12)); --- Location: LCCOMB_X24_Y36_N26 +-- Location: LCCOMB_X56_Y72_N8 +\inst2|Equal0~2\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst2|Equal0~2_combout\ = (\inst2|s_counter\(11) & (\inst2|s_counter\(12) & (!\inst2|s_counter\(8) & !\inst2|s_counter\(9)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|s_counter\(11), + datab => \inst2|s_counter\(12), + datac => \inst2|s_counter\(8), + datad => \inst2|s_counter\(9), + combout => \inst2|Equal0~2_combout\); + +-- Location: LCCOMB_X55_Y72_N26 \inst2|Add2~26\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~26_combout\ = (\inst2|s_counter\(13) & (!\inst2|Add2~25\)) # (!\inst2|s_counter\(13) & ((\inst2|Add2~25\) # (GND))) @@ -1059,22 +1076,23 @@ PORT MAP ( combout => \inst2|Add2~26_combout\, cout => \inst2|Add2~27\); --- Location: LCCOMB_X23_Y36_N22 +-- Location: LCCOMB_X56_Y72_N16 \inst2|s_counter~7\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|s_counter~7_combout\ = (!\inst2|Equal0~11_combout\ & \inst2|Add2~26_combout\) +-- \inst2|s_counter~7_combout\ = (\inst2|Add2~26_combout\ & ((!\inst2|Equal0~5_combout\) # (!\inst2|Equal0~9_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000111100000000", + lut_mask => "0011000011110000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datac => \inst2|Equal0~11_combout\, - datad => \inst2|Add2~26_combout\, + datab => \inst2|Equal0~9_combout\, + datac => \inst2|Add2~26_combout\, + datad => \inst2|Equal0~5_combout\, combout => \inst2|s_counter~7_combout\); --- Location: FF_X23_Y36_N23 +-- Location: FF_X56_Y72_N17 \inst2|s_counter[13]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1088,7 +1106,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(13)); --- Location: LCCOMB_X24_Y36_N28 +-- Location: LCCOMB_X55_Y72_N28 \inst2|Add2~28\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~28_combout\ = (\inst2|s_counter\(14) & (\inst2|Add2~27\ $ (GND))) # (!\inst2|s_counter\(14) & (!\inst2|Add2~27\ & VCC)) @@ -1106,22 +1124,23 @@ PORT MAP ( combout => \inst2|Add2~28_combout\, cout => \inst2|Add2~29\); --- Location: LCCOMB_X23_Y35_N24 -\inst2|s_counter~4\ : cycloneive_lcell_comb +-- Location: LCCOMB_X56_Y71_N14 +\inst2|s_counter~5\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|s_counter~4_combout\ = (!\inst2|Equal0~11_combout\ & \inst2|Add2~28_combout\) +-- \inst2|s_counter~5_combout\ = (\inst2|Add2~28_combout\ & ((!\inst2|Equal0~5_combout\) # (!\inst2|Equal0~9_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000111100000000", + lut_mask => "0011000011110000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datac => \inst2|Equal0~11_combout\, - datad => \inst2|Add2~28_combout\, - combout => \inst2|s_counter~4_combout\); + datab => \inst2|Equal0~9_combout\, + datac => \inst2|Add2~28_combout\, + datad => \inst2|Equal0~5_combout\, + combout => \inst2|s_counter~5_combout\); --- Location: FF_X23_Y35_N25 +-- Location: FF_X56_Y71_N15 \inst2|s_counter[14]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1130,12 +1149,12 @@ GENERIC MAP ( -- pragma translate_on PORT MAP ( clk => \CLOCK_50~inputclkctrl_outclk\, - d => \inst2|s_counter~4_combout\, + d => \inst2|s_counter~5_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|s_counter\(14)); --- Location: LCCOMB_X24_Y36_N30 +-- Location: LCCOMB_X55_Y72_N30 \inst2|Add2~30\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~30_combout\ = (\inst2|s_counter\(15) & (!\inst2|Add2~29\)) # (!\inst2|s_counter\(15) & ((\inst2|Add2~29\) # (GND))) @@ -1153,7 +1172,7 @@ PORT MAP ( combout => \inst2|Add2~30_combout\, cout => \inst2|Add2~31\); --- Location: FF_X24_Y36_N31 +-- Location: FF_X55_Y72_N31 \inst2|s_counter[15]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1167,7 +1186,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(15)); --- Location: LCCOMB_X24_Y35_N0 +-- Location: LCCOMB_X55_Y71_N0 \inst2|Add2~32\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~32_combout\ = (\inst2|s_counter\(16) & (\inst2|Add2~31\ $ (GND))) # (!\inst2|s_counter\(16) & (!\inst2|Add2~31\ & VCC)) @@ -1185,22 +1204,23 @@ PORT MAP ( combout => \inst2|Add2~32_combout\, cout => \inst2|Add2~33\); --- Location: LCCOMB_X23_Y35_N16 -\inst2|s_counter~3\ : cycloneive_lcell_comb +-- Location: LCCOMB_X56_Y71_N2 +\inst2|s_counter~4\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|s_counter~3_combout\ = (!\inst2|Equal0~11_combout\ & \inst2|Add2~32_combout\) +-- \inst2|s_counter~4_combout\ = (\inst2|Add2~32_combout\ & ((!\inst2|Equal0~5_combout\) # (!\inst2|Equal0~9_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0101000001010000", + lut_mask => "0011000011110000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|Equal0~11_combout\, + datab => \inst2|Equal0~9_combout\, datac => \inst2|Add2~32_combout\, - combout => \inst2|s_counter~3_combout\); + datad => \inst2|Equal0~5_combout\, + combout => \inst2|s_counter~4_combout\); --- Location: FF_X23_Y35_N17 +-- Location: FF_X56_Y71_N3 \inst2|s_counter[16]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1209,12 +1229,12 @@ GENERIC MAP ( -- pragma translate_on PORT MAP ( clk => \CLOCK_50~inputclkctrl_outclk\, - d => \inst2|s_counter~3_combout\, + d => \inst2|s_counter~4_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|s_counter\(16)); --- Location: LCCOMB_X24_Y35_N2 +-- Location: LCCOMB_X55_Y71_N2 \inst2|Add2~34\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~34_combout\ = (\inst2|s_counter\(17) & (!\inst2|Add2~33\)) # (!\inst2|s_counter\(17) & ((\inst2|Add2~33\) # (GND))) @@ -1232,7 +1252,7 @@ PORT MAP ( combout => \inst2|Add2~34_combout\, cout => \inst2|Add2~35\); --- Location: FF_X24_Y35_N3 +-- Location: FF_X55_Y71_N3 \inst2|s_counter[17]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1246,7 +1266,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(17)); --- Location: LCCOMB_X24_Y35_N4 +-- Location: LCCOMB_X55_Y71_N4 \inst2|Add2~36\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~36_combout\ = (\inst2|s_counter\(18) & (\inst2|Add2~35\ $ (GND))) # (!\inst2|s_counter\(18) & (!\inst2|Add2~35\ & VCC)) @@ -1254,32 +1274,33 @@ PORT MAP ( -- pragma translate_off GENERIC MAP ( - lut_mask => "1010010100001010", + lut_mask => "1100001100001100", sum_lutc_input => "cin") -- pragma translate_on PORT MAP ( - dataa => \inst2|s_counter\(18), + datab => \inst2|s_counter\(18), datad => VCC, cin => \inst2|Add2~35\, combout => \inst2|Add2~36_combout\, cout => \inst2|Add2~37\); --- Location: LCCOMB_X23_Y36_N18 +-- Location: LCCOMB_X56_Y72_N30 \inst2|s_counter~6\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|s_counter~6_combout\ = (!\inst2|Equal0~11_combout\ & \inst2|Add2~36_combout\) +-- \inst2|s_counter~6_combout\ = (\inst2|Add2~36_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000111100000000", + lut_mask => "0011111100000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datac => \inst2|Equal0~11_combout\, + datab => \inst2|Equal0~5_combout\, + datac => \inst2|Equal0~9_combout\, datad => \inst2|Add2~36_combout\, combout => \inst2|s_counter~6_combout\); --- Location: FF_X23_Y36_N19 +-- Location: FF_X56_Y72_N31 \inst2|s_counter[18]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1293,138 +1314,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(18)); --- Location: LCCOMB_X23_Y36_N26 -\inst2|Equal0~2\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|Equal0~2_combout\ = (\inst2|s_counter\(12) & (\inst2|s_counter\(11) & (\inst2|s_counter\(13) & \inst2|s_counter\(18)))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1000000000000000", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|s_counter\(12), - datab => \inst2|s_counter\(11), - datac => \inst2|s_counter\(13), - datad => \inst2|s_counter\(18), - combout => \inst2|Equal0~2_combout\); - --- Location: LCCOMB_X23_Y36_N8 -\inst2|Equal0~3\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|Equal0~3_combout\ = (!\inst2|s_counter\(6) & (!\inst2|s_counter\(8) & (!\inst2|s_counter\(7) & !\inst2|s_counter\(9)))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0000000000000001", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|s_counter\(6), - datab => \inst2|s_counter\(8), - datac => \inst2|s_counter\(7), - datad => \inst2|s_counter\(9), - combout => \inst2|Equal0~3_combout\); - --- Location: LCCOMB_X24_Y35_N6 -\inst2|Add2~38\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|Add2~38_combout\ = (\inst2|s_counter\(19) & (!\inst2|Add2~37\)) # (!\inst2|s_counter\(19) & ((\inst2|Add2~37\) # (GND))) --- \inst2|Add2~39\ = CARRY((!\inst2|Add2~37\) # (!\inst2|s_counter\(19))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|s_counter\(19), - datad => VCC, - cin => \inst2|Add2~37\, - combout => \inst2|Add2~38_combout\, - cout => \inst2|Add2~39\); - --- Location: LCCOMB_X23_Y35_N6 -\inst2|s_counter~2\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|s_counter~2_combout\ = (!\inst2|Equal0~11_combout\ & \inst2|Add2~38_combout\) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0000111100000000", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - datac => \inst2|Equal0~11_combout\, - datad => \inst2|Add2~38_combout\, - combout => \inst2|s_counter~2_combout\); - --- Location: FF_X23_Y35_N7 -\inst2|s_counter[19]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \CLOCK_50~inputclkctrl_outclk\, - d => \inst2|s_counter~2_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|s_counter\(19)); - --- Location: LCCOMB_X24_Y35_N8 -\inst2|Add2~40\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|Add2~40_combout\ = (\inst2|s_counter\(20) & (\inst2|Add2~39\ $ (GND))) # (!\inst2|s_counter\(20) & (!\inst2|Add2~39\ & VCC)) --- \inst2|Add2~41\ = CARRY((\inst2|s_counter\(20) & !\inst2|Add2~39\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100001100001100", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|s_counter\(20), - datad => VCC, - cin => \inst2|Add2~39\, - combout => \inst2|Add2~40_combout\, - cout => \inst2|Add2~41\); - --- Location: FF_X24_Y35_N9 -\inst2|s_counter[20]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \CLOCK_50~inputclkctrl_outclk\, - d => \inst2|Add2~40_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|s_counter\(20)); - --- Location: LCCOMB_X24_Y35_N10 -\inst2|Add2~42\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|Add2~42_combout\ = (\inst2|s_counter\(21) & (!\inst2|Add2~41\)) # (!\inst2|s_counter\(21) & ((\inst2|Add2~41\) # (GND))) --- \inst2|Add2~43\ = CARRY((!\inst2|Add2~41\) # (!\inst2|s_counter\(21))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|s_counter\(21), - datad => VCC, - cin => \inst2|Add2~41\, - combout => \inst2|Add2~42_combout\, - cout => \inst2|Add2~43\); - --- Location: LCCOMB_X24_Y35_N12 +-- Location: LCCOMB_X55_Y71_N12 \inst2|Add2~44\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~44_combout\ = (\inst2|s_counter\(22) & (\inst2|Add2~43\ $ (GND))) # (!\inst2|s_counter\(22) & (!\inst2|Add2~43\ & VCC)) @@ -1442,21 +1332,7 @@ PORT MAP ( combout => \inst2|Add2~44_combout\, cout => \inst2|Add2~45\); --- Location: FF_X24_Y35_N13 -\inst2|s_counter[22]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \CLOCK_50~inputclkctrl_outclk\, - d => \inst2|Add2~44_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, - q => \inst2|s_counter\(22)); - --- Location: LCCOMB_X24_Y35_N14 +-- Location: LCCOMB_X55_Y71_N14 \inst2|Add2~46\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~46_combout\ = (\inst2|s_counter\(23) & (!\inst2|Add2~45\)) # (!\inst2|s_counter\(23) & ((\inst2|Add2~45\) # (GND))) @@ -1464,32 +1340,33 @@ PORT MAP ( -- pragma translate_off GENERIC MAP ( - lut_mask => "0101101001011111", + lut_mask => "0011110000111111", sum_lutc_input => "cin") -- pragma translate_on PORT MAP ( - dataa => \inst2|s_counter\(23), + datab => \inst2|s_counter\(23), datad => VCC, cin => \inst2|Add2~45\, combout => \inst2|Add2~46_combout\, cout => \inst2|Add2~47\); --- Location: LCCOMB_X23_Y36_N4 -\inst2|s_counter~5\ : cycloneive_lcell_comb +-- Location: LCCOMB_X56_Y71_N18 +\inst2|s_counter~1\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|s_counter~5_combout\ = (!\inst2|Equal0~11_combout\ & \inst2|Add2~46_combout\) +-- \inst2|s_counter~1_combout\ = (\inst2|Add2~46_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000111100000000", + lut_mask => "0011111100000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datac => \inst2|Equal0~11_combout\, + datab => \inst2|Equal0~5_combout\, + datac => \inst2|Equal0~9_combout\, datad => \inst2|Add2~46_combout\, - combout => \inst2|s_counter~5_combout\); + combout => \inst2|s_counter~1_combout\); --- Location: FF_X23_Y36_N5 +-- Location: FF_X56_Y71_N19 \inst2|s_counter[23]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1498,12 +1375,12 @@ GENERIC MAP ( -- pragma translate_on PORT MAP ( clk => \CLOCK_50~inputclkctrl_outclk\, - d => \inst2|s_counter~5_combout\, + d => \inst2|s_counter~1_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|s_counter\(23)); --- Location: LCCOMB_X24_Y35_N16 +-- Location: LCCOMB_X55_Y71_N16 \inst2|Add2~48\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~48_combout\ = (\inst2|s_counter\(24) & (\inst2|Add2~47\ $ (GND))) # (!\inst2|s_counter\(24) & (!\inst2|Add2~47\ & VCC)) @@ -1521,23 +1398,56 @@ PORT MAP ( combout => \inst2|Add2~48_combout\, cout => \inst2|Add2~49\); --- Location: LCCOMB_X23_Y35_N28 -\inst2|s_counter~0\ : cycloneive_lcell_comb +-- Location: FF_X55_Y71_N17 +\inst2|s_counter[24]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLOCK_50~inputclkctrl_outclk\, + d => \inst2|Add2~48_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|s_counter\(24)); + +-- Location: LCCOMB_X55_Y71_N18 +\inst2|Add2~50\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|s_counter~0_combout\ = (!\inst2|Equal0~11_combout\ & \inst2|Add2~48_combout\) +-- \inst2|Add2~50_combout\ = (\inst2|s_counter\(25) & (!\inst2|Add2~49\)) # (!\inst2|s_counter\(25) & ((\inst2|Add2~49\) # (GND))) +-- \inst2|Add2~51\ = CARRY((!\inst2|Add2~49\) # (!\inst2|s_counter\(25))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000111100000000", + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|s_counter\(25), + datad => VCC, + cin => \inst2|Add2~49\, + combout => \inst2|Add2~50_combout\, + cout => \inst2|Add2~51\); + +-- Location: LCCOMB_X56_Y71_N20 +\inst2|s_counter~0\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst2|s_counter~0_combout\ = (\inst2|Add2~50_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011111100000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datac => \inst2|Equal0~11_combout\, - datad => \inst2|Add2~48_combout\, + datab => \inst2|Equal0~5_combout\, + datac => \inst2|Equal0~9_combout\, + datad => \inst2|Add2~50_combout\, combout => \inst2|s_counter~0_combout\); --- Location: FF_X23_Y35_N29 -\inst2|s_counter[24]\ : dffeas +-- Location: FF_X56_Y71_N21 +\inst2|s_counter[25]\ : dffeas -- pragma translate_off GENERIC MAP ( is_wysiwyg => "true", @@ -1548,41 +1458,9 @@ PORT MAP ( d => \inst2|s_counter~0_combout\, devclrn => ww_devclrn, devpor => ww_devpor, - q => \inst2|s_counter\(24)); - --- Location: LCCOMB_X24_Y35_N18 -\inst2|Add2~50\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|Add2~50_combout\ = (\inst2|s_counter\(25) & (!\inst2|Add2~49\)) # (!\inst2|s_counter\(25) & ((\inst2|Add2~49\) # (GND))) --- \inst2|Add2~51\ = CARRY((!\inst2|Add2~49\) # (!\inst2|s_counter\(25))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0011110000111111", - sum_lutc_input => "cin") --- pragma translate_on -PORT MAP ( - datab => \inst2|s_counter\(25), - datad => VCC, - cin => \inst2|Add2~49\, - combout => \inst2|Add2~50_combout\, - cout => \inst2|Add2~51\); - --- Location: FF_X24_Y35_N19 -\inst2|s_counter[25]\ : dffeas --- pragma translate_off -GENERIC MAP ( - is_wysiwyg => "true", - power_up => "low") --- pragma translate_on -PORT MAP ( - clk => \CLOCK_50~inputclkctrl_outclk\, - d => \inst2|Add2~50_combout\, - devclrn => ww_devclrn, - devpor => ww_devpor, q => \inst2|s_counter\(25)); --- Location: LCCOMB_X24_Y35_N20 +-- Location: LCCOMB_X55_Y71_N20 \inst2|Add2~52\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~52_combout\ = (\inst2|s_counter\(26) & (\inst2|Add2~51\ $ (GND))) # (!\inst2|s_counter\(26) & (!\inst2|Add2~51\ & VCC)) @@ -1600,7 +1478,7 @@ PORT MAP ( combout => \inst2|Add2~52_combout\, cout => \inst2|Add2~53\); --- Location: FF_X24_Y35_N21 +-- Location: FF_X55_Y71_N21 \inst2|s_counter[26]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1614,7 +1492,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(26)); --- Location: LCCOMB_X24_Y35_N22 +-- Location: LCCOMB_X55_Y71_N22 \inst2|Add2~54\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~54_combout\ = (\inst2|s_counter\(27) & (!\inst2|Add2~53\)) # (!\inst2|s_counter\(27) & ((\inst2|Add2~53\) # (GND))) @@ -1632,7 +1510,7 @@ PORT MAP ( combout => \inst2|Add2~54_combout\, cout => \inst2|Add2~55\); --- Location: FF_X24_Y35_N23 +-- Location: FF_X55_Y71_N23 \inst2|s_counter[27]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1646,7 +1524,24 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(27)); --- Location: LCCOMB_X24_Y35_N24 +-- Location: LCCOMB_X56_Y72_N14 +\inst2|Equal0~1\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst2|Equal0~1_combout\ = (\inst2|s_counter\(18) & (\inst2|s_counter\(13) & (!\inst2|s_counter\(27) & !\inst2|s_counter\(26)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|s_counter\(18), + datab => \inst2|s_counter\(13), + datac => \inst2|s_counter\(27), + datad => \inst2|s_counter\(26), + combout => \inst2|Equal0~1_combout\); + +-- Location: LCCOMB_X55_Y71_N24 \inst2|Add2~56\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~56_combout\ = (\inst2|s_counter\(28) & (\inst2|Add2~55\ $ (GND))) # (!\inst2|s_counter\(28) & (!\inst2|Add2~55\ & VCC)) @@ -1664,7 +1559,7 @@ PORT MAP ( combout => \inst2|Add2~56_combout\, cout => \inst2|Add2~57\); --- Location: FF_X24_Y35_N25 +-- Location: FF_X55_Y71_N25 \inst2|s_counter[28]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1678,7 +1573,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(28)); --- Location: LCCOMB_X24_Y35_N26 +-- Location: LCCOMB_X55_Y71_N26 \inst2|Add2~58\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~58_combout\ = (\inst2|s_counter\(29) & (!\inst2|Add2~57\)) # (!\inst2|s_counter\(29) & ((\inst2|Add2~57\) # (GND))) @@ -1696,7 +1591,7 @@ PORT MAP ( combout => \inst2|Add2~58_combout\, cout => \inst2|Add2~59\); --- Location: FF_X24_Y35_N27 +-- Location: FF_X55_Y71_N27 \inst2|s_counter[29]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1710,7 +1605,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(29)); --- Location: LCCOMB_X24_Y35_N28 +-- Location: LCCOMB_X55_Y71_N28 \inst2|Add2~60\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~60_combout\ = (\inst2|s_counter\(30) & (\inst2|Add2~59\ $ (GND))) # (!\inst2|s_counter\(30) & (!\inst2|Add2~59\ & VCC)) @@ -1728,7 +1623,7 @@ PORT MAP ( combout => \inst2|Add2~60_combout\, cout => \inst2|Add2~61\); --- Location: FF_X24_Y35_N29 +-- Location: FF_X55_Y71_N29 \inst2|s_counter[30]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1742,7 +1637,7 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(30)); --- Location: LCCOMB_X24_Y35_N30 +-- Location: LCCOMB_X55_Y71_N30 \inst2|Add2~62\ : cycloneive_lcell_comb -- Equation(s): -- \inst2|Add2~62_combout\ = \inst2|s_counter\(31) $ (\inst2|Add2~61\) @@ -1757,7 +1652,7 @@ PORT MAP ( cin => \inst2|Add2~61\, combout => \inst2|Add2~62_combout\); --- Location: FF_X24_Y35_N31 +-- Location: FF_X55_Y71_N31 \inst2|s_counter[31]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1771,10 +1666,10 @@ PORT MAP ( devpor => ww_devpor, q => \inst2|s_counter\(31)); --- Location: LCCOMB_X23_Y35_N10 +-- Location: LCCOMB_X56_Y72_N24 \inst2|Equal0~0\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|Equal0~0_combout\ = (!\inst2|s_counter\(31) & (!\inst2|s_counter\(30) & (!\inst2|s_counter\(29) & !\inst2|s_counter\(28)))) +-- \inst2|Equal0~0_combout\ = (!\inst2|s_counter\(29) & (!\inst2|s_counter\(30) & (!\inst2|s_counter\(28) & !\inst2|s_counter\(31)))) -- pragma translate_off GENERIC MAP ( @@ -1782,33 +1677,16 @@ GENERIC MAP ( sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|s_counter\(31), + dataa => \inst2|s_counter\(29), datab => \inst2|s_counter\(30), - datac => \inst2|s_counter\(29), - datad => \inst2|s_counter\(28), + datac => \inst2|s_counter\(28), + datad => \inst2|s_counter\(31), combout => \inst2|Equal0~0_combout\); --- Location: LCCOMB_X23_Y36_N24 -\inst2|Equal0~1\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|Equal0~1_combout\ = (!\inst2|s_counter\(27) & (!\inst2|s_counter\(26) & (\inst2|s_counter\(23) & !\inst2|s_counter\(25)))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0000000000010000", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - dataa => \inst2|s_counter\(27), - datab => \inst2|s_counter\(26), - datac => \inst2|s_counter\(23), - datad => \inst2|s_counter\(25), - combout => \inst2|Equal0~1_combout\); - --- Location: LCCOMB_X23_Y36_N20 +-- Location: LCCOMB_X56_Y72_N18 \inst2|Equal0~4\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|Equal0~4_combout\ = (\inst2|Equal0~2_combout\ & (\inst2|Equal0~3_combout\ & (\inst2|Equal0~0_combout\ & \inst2|Equal0~1_combout\))) +-- \inst2|Equal0~4_combout\ = (\inst2|Equal0~3_combout\ & (\inst2|Equal0~2_combout\ & (\inst2|Equal0~1_combout\ & \inst2|Equal0~0_combout\))) -- pragma translate_off GENERIC MAP ( @@ -1816,16 +1694,16 @@ GENERIC MAP ( sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|Equal0~2_combout\, - datab => \inst2|Equal0~3_combout\, - datac => \inst2|Equal0~0_combout\, - datad => \inst2|Equal0~1_combout\, + dataa => \inst2|Equal0~3_combout\, + datab => \inst2|Equal0~2_combout\, + datac => \inst2|Equal0~1_combout\, + datad => \inst2|Equal0~0_combout\, combout => \inst2|Equal0~4_combout\); --- Location: LCCOMB_X23_Y36_N30 -\inst2|Equal0~11\ : cycloneive_lcell_comb +-- Location: LCCOMB_X56_Y72_N28 +\inst2|Equal0~5\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|Equal0~11_combout\ = (\inst2|s_counter\(0) & (\inst2|Equal0~5_combout\ & (\inst2|Equal0~10_combout\ & \inst2|Equal0~4_combout\))) +-- \inst2|Equal0~5_combout\ = (\inst2|s_counter\(0) & (\inst2|s_counter\(1) & (\inst2|s_counter\(2) & \inst2|Equal0~4_combout\))) -- pragma translate_off GENERIC MAP ( @@ -1834,27 +1712,96 @@ GENERIC MAP ( -- pragma translate_on PORT MAP ( dataa => \inst2|s_counter\(0), - datab => \inst2|Equal0~5_combout\, - datac => \inst2|Equal0~10_combout\, + datab => \inst2|s_counter\(1), + datac => \inst2|s_counter\(2), datad => \inst2|Equal0~4_combout\, - combout => \inst2|Equal0~11_combout\); + combout => \inst2|Equal0~5_combout\); --- Location: LCCOMB_X23_Y35_N22 -\inst2|s_counter~1\ : cycloneive_lcell_comb +-- Location: LCCOMB_X55_Y71_N6 +\inst2|Add2~38\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|s_counter~1_combout\ = (!\inst2|Equal0~11_combout\ & \inst2|Add2~42_combout\) +-- \inst2|Add2~38_combout\ = (\inst2|s_counter\(19) & (!\inst2|Add2~37\)) # (!\inst2|s_counter\(19) & ((\inst2|Add2~37\) # (GND))) +-- \inst2|Add2~39\ = CARRY((!\inst2|Add2~37\) # (!\inst2|s_counter\(19))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0101000001010000", + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|s_counter\(19), + datad => VCC, + cin => \inst2|Add2~37\, + combout => \inst2|Add2~38_combout\, + cout => \inst2|Add2~39\); + +-- Location: LCCOMB_X55_Y71_N8 +\inst2|Add2~40\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst2|Add2~40_combout\ = (\inst2|s_counter\(20) & (\inst2|Add2~39\ $ (GND))) # (!\inst2|s_counter\(20) & (!\inst2|Add2~39\ & VCC)) +-- \inst2|Add2~41\ = CARRY((\inst2|s_counter\(20) & !\inst2|Add2~39\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100001100001100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \inst2|s_counter\(20), + datad => VCC, + cin => \inst2|Add2~39\, + combout => \inst2|Add2~40_combout\, + cout => \inst2|Add2~41\); + +-- Location: FF_X55_Y71_N9 +\inst2|s_counter[20]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLOCK_50~inputclkctrl_outclk\, + d => \inst2|Add2~40_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|s_counter\(20)); + +-- Location: LCCOMB_X55_Y71_N10 +\inst2|Add2~42\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst2|Add2~42_combout\ = (\inst2|s_counter\(21) & (!\inst2|Add2~41\)) # (!\inst2|s_counter\(21) & ((\inst2|Add2~41\) # (GND))) +-- \inst2|Add2~43\ = CARRY((!\inst2|Add2~41\) # (!\inst2|s_counter\(21))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0101101001011111", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|s_counter\(21), + datad => VCC, + cin => \inst2|Add2~41\, + combout => \inst2|Add2~42_combout\, + cout => \inst2|Add2~43\); + +-- Location: LCCOMB_X56_Y71_N30 +\inst2|s_counter~2\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst2|s_counter~2_combout\ = (\inst2|Add2~42_combout\ & ((!\inst2|Equal0~9_combout\) # (!\inst2|Equal0~5_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011111100000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|Equal0~11_combout\, - datac => \inst2|Add2~42_combout\, - combout => \inst2|s_counter~1_combout\); + datab => \inst2|Equal0~5_combout\, + datac => \inst2|Equal0~9_combout\, + datad => \inst2|Add2~42_combout\, + combout => \inst2|s_counter~2_combout\); --- Location: FF_X23_Y35_N23 +-- Location: FF_X56_Y71_N31 \inst2|s_counter[21]\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -1863,32 +1810,46 @@ GENERIC MAP ( -- pragma translate_on PORT MAP ( clk => \CLOCK_50~inputclkctrl_outclk\, - d => \inst2|s_counter~1_combout\, + d => \inst2|s_counter~2_combout\, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|s_counter\(21)); --- Location: LCCOMB_X23_Y35_N4 -\inst2|Equal0~7\ : cycloneive_lcell_comb +-- Location: FF_X55_Y71_N13 +\inst2|s_counter[22]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLOCK_50~inputclkctrl_outclk\, + d => \inst2|Add2~44_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|s_counter\(22)); + +-- Location: LCCOMB_X56_Y71_N12 +\inst2|Equal0~6\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|Equal0~7_combout\ = (\inst2|s_counter\(21) & (!\inst2|s_counter\(22) & (!\inst2|s_counter\(20) & \inst2|s_counter\(24)))) +-- \inst2|Equal0~6_combout\ = (!\inst2|s_counter\(22) & (\inst2|s_counter\(25) & (!\inst2|s_counter\(24) & \inst2|s_counter\(23)))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000001000000000", + lut_mask => "0000010000000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|s_counter\(21), - datab => \inst2|s_counter\(22), - datac => \inst2|s_counter\(20), - datad => \inst2|s_counter\(24), - combout => \inst2|Equal0~7_combout\); + dataa => \inst2|s_counter\(22), + datab => \inst2|s_counter\(25), + datac => \inst2|s_counter\(24), + datad => \inst2|s_counter\(23), + combout => \inst2|Equal0~6_combout\); --- Location: LCCOMB_X23_Y35_N26 -\inst2|Equal0~8\ : cycloneive_lcell_comb +-- Location: LCCOMB_X56_Y71_N16 +\inst2|Equal0~7\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|Equal0~8_combout\ = (\inst2|s_counter\(19) & (\inst2|s_counter\(16) & (!\inst2|s_counter\(15) & !\inst2|s_counter\(17)))) +-- \inst2|Equal0~7_combout\ = (\inst2|s_counter\(19) & (\inst2|s_counter\(21) & (!\inst2|s_counter\(20) & !\inst2|s_counter\(17)))) -- pragma translate_off GENERIC MAP ( @@ -1897,47 +1858,15 @@ GENERIC MAP ( -- pragma translate_on PORT MAP ( dataa => \inst2|s_counter\(19), - datab => \inst2|s_counter\(16), - datac => \inst2|s_counter\(15), + datab => \inst2|s_counter\(21), + datac => \inst2|s_counter\(20), datad => \inst2|s_counter\(17), - combout => \inst2|Equal0~8_combout\); + combout => \inst2|Equal0~7_combout\); --- Location: LCCOMB_X23_Y35_N12 -\inst2|Equal0~9\ : cycloneive_lcell_comb +-- Location: LCCOMB_X56_Y71_N24 +\inst2|Equal0~8\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|Equal0~9_combout\ = (\inst2|s_counter\(14) & (\inst2|s_counter\(5) & !\inst2|s_counter\(10))) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "0000000011000000", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - datab => \inst2|s_counter\(14), - datac => \inst2|s_counter\(5), - datad => \inst2|s_counter\(10), - combout => \inst2|Equal0~9_combout\); - --- Location: LCCOMB_X23_Y35_N2 -\inst2|Equal0~10\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|Equal0~10_combout\ = (\inst2|Equal0~7_combout\ & (\inst2|Equal0~8_combout\ & \inst2|Equal0~9_combout\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100000000000000", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - datab => \inst2|Equal0~7_combout\, - datac => \inst2|Equal0~8_combout\, - datad => \inst2|Equal0~9_combout\, - combout => \inst2|Equal0~10_combout\); - --- Location: LCCOMB_X23_Y35_N20 -\inst2|clkOut~0\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|clkOut~0_combout\ = (!\inst2|s_counter\(21) & (\inst2|s_counter\(22) & (\inst2|s_counter\(20) & !\inst2|s_counter\(24)))) +-- \inst2|Equal0~8_combout\ = (!\inst2|s_counter\(15) & (\inst2|s_counter\(16) & (\inst2|s_counter\(14) & !\inst2|s_counter\(10)))) -- pragma translate_off GENERIC MAP ( @@ -1945,32 +1874,63 @@ GENERIC MAP ( sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|s_counter\(21), - datab => \inst2|s_counter\(22), - datac => \inst2|s_counter\(20), - datad => \inst2|s_counter\(24), - combout => \inst2|clkOut~0_combout\); + dataa => \inst2|s_counter\(15), + datab => \inst2|s_counter\(16), + datac => \inst2|s_counter\(14), + datad => \inst2|s_counter\(10), + combout => \inst2|Equal0~8_combout\); --- Location: LCCOMB_X23_Y35_N14 -\inst2|clkOut~2\ : cycloneive_lcell_comb +-- Location: LCCOMB_X56_Y71_N8 +\inst2|Equal0~9\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|clkOut~2_combout\ = (!\inst2|s_counter\(14) & (!\inst2|s_counter\(5) & \inst2|s_counter\(10))) +-- \inst2|Equal0~9_combout\ = (\inst2|Equal0~6_combout\ & (\inst2|Equal0~7_combout\ & (\inst2|s_counter\(5) & \inst2|Equal0~8_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0000001100000000", + lut_mask => "1000000000000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datab => \inst2|s_counter\(14), + dataa => \inst2|Equal0~6_combout\, + datab => \inst2|Equal0~7_combout\, datac => \inst2|s_counter\(5), - datad => \inst2|s_counter\(10), - combout => \inst2|clkOut~2_combout\); + datad => \inst2|Equal0~8_combout\, + combout => \inst2|Equal0~9_combout\); --- Location: LCCOMB_X23_Y35_N18 +-- Location: LCCOMB_X56_Y71_N6 +\inst2|s_counter~3\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst2|s_counter~3_combout\ = (\inst2|Add2~38_combout\ & ((!\inst2|Equal0~5_combout\) # (!\inst2|Equal0~9_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000011110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst2|Equal0~9_combout\, + datac => \inst2|Add2~38_combout\, + datad => \inst2|Equal0~5_combout\, + combout => \inst2|s_counter~3_combout\); + +-- Location: FF_X56_Y71_N7 +\inst2|s_counter[19]\ : dffeas +-- pragma translate_off +GENERIC MAP ( + is_wysiwyg => "true", + power_up => "low") +-- pragma translate_on +PORT MAP ( + clk => \CLOCK_50~inputclkctrl_outclk\, + d => \inst2|s_counter~3_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + q => \inst2|s_counter\(19)); + +-- Location: LCCOMB_X56_Y71_N4 \inst2|clkOut~1\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|clkOut~1_combout\ = (!\inst2|s_counter\(19) & (!\inst2|s_counter\(16) & (\inst2|s_counter\(15) & \inst2|s_counter\(17)))) +-- \inst2|clkOut~1_combout\ = (!\inst2|s_counter\(19) & (!\inst2|s_counter\(21) & (\inst2|s_counter\(20) & \inst2|s_counter\(17)))) -- pragma translate_off GENERIC MAP ( @@ -1979,75 +1939,80 @@ GENERIC MAP ( -- pragma translate_on PORT MAP ( dataa => \inst2|s_counter\(19), - datab => \inst2|s_counter\(16), - datac => \inst2|s_counter\(15), + datab => \inst2|s_counter\(21), + datac => \inst2|s_counter\(20), datad => \inst2|s_counter\(17), combout => \inst2|clkOut~1_combout\); --- Location: LCCOMB_X23_Y35_N0 +-- Location: LCCOMB_X56_Y71_N28 +\inst2|clkOut~2\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst2|clkOut~2_combout\ = (\inst2|s_counter\(15) & (\inst2|s_counter\(10) & (!\inst2|s_counter\(14) & !\inst2|s_counter\(16)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|s_counter\(15), + datab => \inst2|s_counter\(10), + datac => \inst2|s_counter\(14), + datad => \inst2|s_counter\(16), + combout => \inst2|clkOut~2_combout\); + +-- Location: LCCOMB_X56_Y71_N10 +\inst2|clkOut~0\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst2|clkOut~0_combout\ = (\inst2|s_counter\(22) & (!\inst2|s_counter\(25) & (\inst2|s_counter\(24) & !\inst2|s_counter\(23)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst2|s_counter\(22), + datab => \inst2|s_counter\(25), + datac => \inst2|s_counter\(24), + datad => \inst2|s_counter\(23), + combout => \inst2|clkOut~0_combout\); + +-- Location: LCCOMB_X56_Y71_N26 \inst2|clkOut~3\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|clkOut~3_combout\ = (\inst2|clkOut~0_combout\ & (\inst2|clkOut~2_combout\ & \inst2|clkOut~1_combout\)) +-- \inst2|clkOut~3_combout\ = (\inst2|clkOut~1_combout\ & (\inst2|clkOut~2_combout\ & (!\inst2|s_counter\(5) & \inst2|clkOut~0_combout\))) -- pragma translate_off GENERIC MAP ( - lut_mask => "1100000000000000", + lut_mask => "0000100000000000", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datab => \inst2|clkOut~0_combout\, - datac => \inst2|clkOut~2_combout\, - datad => \inst2|clkOut~1_combout\, + dataa => \inst2|clkOut~1_combout\, + datab => \inst2|clkOut~2_combout\, + datac => \inst2|s_counter\(5), + datad => \inst2|clkOut~0_combout\, combout => \inst2|clkOut~3_combout\); --- Location: LCCOMB_X23_Y36_N12 -\inst2|Equal0~6\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|Equal0~6_combout\ = (\inst2|Equal0~5_combout\ & (\inst2|s_counter\(0) & \inst2|Equal0~4_combout\)) - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100000000000000", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - datab => \inst2|Equal0~5_combout\, - datac => \inst2|s_counter\(0), - datad => \inst2|Equal0~4_combout\, - combout => \inst2|Equal0~6_combout\); - --- Location: LCCOMB_X23_Y36_N16 +-- Location: LCCOMB_X56_Y71_N0 \inst2|clkOut~4\ : cycloneive_lcell_comb -- Equation(s): --- \inst2|clkOut~4_combout\ = (\inst2|Equal0~6_combout\ & (!\inst2|Equal0~10_combout\ & ((\inst2|clkOut~3_combout\) # (\inst2|clkOut~q\)))) # (!\inst2|Equal0~6_combout\ & (((\inst2|clkOut~q\)))) +-- \inst2|clkOut~4_combout\ = (\inst2|Equal0~5_combout\ & (!\inst2|Equal0~9_combout\ & ((\inst2|clkOut~3_combout\) # (\inst2|clkOut~q\)))) # (!\inst2|Equal0~5_combout\ & (((\inst2|clkOut~q\)))) -- pragma translate_off GENERIC MAP ( - lut_mask => "0101010011110000", + lut_mask => "0000111011001100", sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - dataa => \inst2|Equal0~10_combout\, - datab => \inst2|clkOut~3_combout\, - datac => \inst2|clkOut~q\, - datad => \inst2|Equal0~6_combout\, + dataa => \inst2|clkOut~3_combout\, + datab => \inst2|clkOut~q\, + datac => \inst2|Equal0~9_combout\, + datad => \inst2|Equal0~5_combout\, combout => \inst2|clkOut~4_combout\); --- Location: LCCOMB_X23_Y36_N2 -\inst2|clkOut~feeder\ : cycloneive_lcell_comb --- Equation(s): --- \inst2|clkOut~feeder_combout\ = \inst2|clkOut~4_combout\ - --- pragma translate_off -GENERIC MAP ( - lut_mask => "1100110011001100", - sum_lutc_input => "datac") --- pragma translate_on -PORT MAP ( - datab => \inst2|clkOut~4_combout\, - combout => \inst2|clkOut~feeder_combout\); - --- Location: FF_X23_Y36_N3 +-- Location: FF_X56_Y71_N23 \inst2|clkOut\ : dffeas -- pragma translate_off GENERIC MAP ( @@ -2056,12 +2021,13 @@ GENERIC MAP ( -- pragma translate_on PORT MAP ( clk => \CLOCK_50~inputclkctrl_outclk\, - d => \inst2|clkOut~feeder_combout\, + asdata => \inst2|clkOut~4_combout\, + sload => VCC, devclrn => ww_devclrn, devpor => ww_devpor, q => \inst2|clkOut~q\); --- Location: CLKCTRL_G0 +-- Location: CLKCTRL_G12 \inst2|clkOut~clkctrl\ : cycloneive_clkctrl -- pragma translate_off GENERIC MAP ( diff --git a/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo_modelsim.xrf b/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo_modelsim.xrf index ca1d8b1..e4c0284 100644 --- a/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo_modelsim.xrf +++ b/1ano/2semestre/lsd/pratica05/AccN_Demo/simulation/modelsim/AccN_Demo_modelsim.xrf @@ -40,7 +40,6 @@ instance = comp, \inst2|Add2~6\, inst2|Add2~6, AccN_Demo, 1 instance = comp, \inst2|s_counter[3]\, inst2|s_counter[3], AccN_Demo, 1 instance = comp, \inst2|Add2~8\, inst2|Add2~8, AccN_Demo, 1 instance = comp, \inst2|s_counter[4]\, inst2|s_counter[4], AccN_Demo, 1 -instance = comp, \inst2|Equal0~5\, inst2|Equal0~5, AccN_Demo, 1 instance = comp, \inst2|Add2~10\, inst2|Add2~10, AccN_Demo, 1 instance = comp, \inst2|s_counter[5]\, inst2|s_counter[5], AccN_Demo, 1 instance = comp, \inst2|Add2~12\, inst2|Add2~12, AccN_Demo, 1 @@ -48,6 +47,7 @@ instance = comp, \inst2|s_counter~10\, inst2|s_counter~10, AccN_Demo, 1 instance = comp, \inst2|s_counter[6]\, inst2|s_counter[6], AccN_Demo, 1 instance = comp, \inst2|Add2~14\, inst2|Add2~14, AccN_Demo, 1 instance = comp, \inst2|s_counter[7]\, inst2|s_counter[7], AccN_Demo, 1 +instance = comp, \inst2|Equal0~3\, inst2|Equal0~3, AccN_Demo, 1 instance = comp, \inst2|Add2~16\, inst2|Add2~16, AccN_Demo, 1 instance = comp, \inst2|s_counter[8]\, inst2|s_counter[8], AccN_Demo, 1 instance = comp, \inst2|Add2~18\, inst2|Add2~18, AccN_Demo, 1 @@ -60,44 +60,37 @@ instance = comp, \inst2|s_counter[11]\, inst2|s_counter[11], AccN_Demo, 1 instance = comp, \inst2|Add2~24\, inst2|Add2~24, AccN_Demo, 1 instance = comp, \inst2|s_counter~8\, inst2|s_counter~8, AccN_Demo, 1 instance = comp, \inst2|s_counter[12]\, inst2|s_counter[12], AccN_Demo, 1 +instance = comp, \inst2|Equal0~2\, inst2|Equal0~2, AccN_Demo, 1 instance = comp, \inst2|Add2~26\, inst2|Add2~26, AccN_Demo, 1 instance = comp, \inst2|s_counter~7\, inst2|s_counter~7, AccN_Demo, 1 instance = comp, \inst2|s_counter[13]\, inst2|s_counter[13], AccN_Demo, 1 instance = comp, \inst2|Add2~28\, inst2|Add2~28, AccN_Demo, 1 -instance = comp, \inst2|s_counter~4\, inst2|s_counter~4, AccN_Demo, 1 +instance = comp, \inst2|s_counter~5\, inst2|s_counter~5, AccN_Demo, 1 instance = comp, \inst2|s_counter[14]\, inst2|s_counter[14], AccN_Demo, 1 instance = comp, \inst2|Add2~30\, inst2|Add2~30, AccN_Demo, 1 instance = comp, \inst2|s_counter[15]\, inst2|s_counter[15], AccN_Demo, 1 instance = comp, \inst2|Add2~32\, inst2|Add2~32, AccN_Demo, 1 -instance = comp, \inst2|s_counter~3\, inst2|s_counter~3, AccN_Demo, 1 +instance = comp, \inst2|s_counter~4\, inst2|s_counter~4, AccN_Demo, 1 instance = comp, \inst2|s_counter[16]\, inst2|s_counter[16], AccN_Demo, 1 instance = comp, \inst2|Add2~34\, inst2|Add2~34, AccN_Demo, 1 instance = comp, \inst2|s_counter[17]\, inst2|s_counter[17], AccN_Demo, 1 instance = comp, \inst2|Add2~36\, inst2|Add2~36, AccN_Demo, 1 instance = comp, \inst2|s_counter~6\, inst2|s_counter~6, AccN_Demo, 1 instance = comp, \inst2|s_counter[18]\, inst2|s_counter[18], AccN_Demo, 1 -instance = comp, \inst2|Equal0~2\, inst2|Equal0~2, AccN_Demo, 1 -instance = comp, \inst2|Equal0~3\, inst2|Equal0~3, AccN_Demo, 1 -instance = comp, \inst2|Add2~38\, inst2|Add2~38, AccN_Demo, 1 -instance = comp, \inst2|s_counter~2\, inst2|s_counter~2, AccN_Demo, 1 -instance = comp, \inst2|s_counter[19]\, inst2|s_counter[19], AccN_Demo, 1 -instance = comp, \inst2|Add2~40\, inst2|Add2~40, AccN_Demo, 1 -instance = comp, \inst2|s_counter[20]\, inst2|s_counter[20], AccN_Demo, 1 -instance = comp, \inst2|Add2~42\, inst2|Add2~42, AccN_Demo, 1 instance = comp, \inst2|Add2~44\, inst2|Add2~44, AccN_Demo, 1 -instance = comp, \inst2|s_counter[22]\, inst2|s_counter[22], AccN_Demo, 1 instance = comp, \inst2|Add2~46\, inst2|Add2~46, AccN_Demo, 1 -instance = comp, \inst2|s_counter~5\, inst2|s_counter~5, AccN_Demo, 1 +instance = comp, \inst2|s_counter~1\, inst2|s_counter~1, AccN_Demo, 1 instance = comp, \inst2|s_counter[23]\, inst2|s_counter[23], AccN_Demo, 1 instance = comp, \inst2|Add2~48\, inst2|Add2~48, AccN_Demo, 1 -instance = comp, \inst2|s_counter~0\, inst2|s_counter~0, AccN_Demo, 1 instance = comp, \inst2|s_counter[24]\, inst2|s_counter[24], AccN_Demo, 1 instance = comp, \inst2|Add2~50\, inst2|Add2~50, AccN_Demo, 1 +instance = comp, \inst2|s_counter~0\, inst2|s_counter~0, AccN_Demo, 1 instance = comp, \inst2|s_counter[25]\, inst2|s_counter[25], AccN_Demo, 1 instance = comp, \inst2|Add2~52\, inst2|Add2~52, AccN_Demo, 1 instance = comp, \inst2|s_counter[26]\, inst2|s_counter[26], AccN_Demo, 1 instance = comp, \inst2|Add2~54\, inst2|Add2~54, AccN_Demo, 1 instance = comp, \inst2|s_counter[27]\, inst2|s_counter[27], AccN_Demo, 1 +instance = comp, \inst2|Equal0~1\, inst2|Equal0~1, AccN_Demo, 1 instance = comp, \inst2|Add2~56\, inst2|Add2~56, AccN_Demo, 1 instance = comp, \inst2|s_counter[28]\, inst2|s_counter[28], AccN_Demo, 1 instance = comp, \inst2|Add2~58\, inst2|Add2~58, AccN_Demo, 1 @@ -107,22 +100,26 @@ instance = comp, \inst2|s_counter[30]\, inst2|s_counter[30], AccN_Demo, 1 instance = comp, \inst2|Add2~62\, inst2|Add2~62, AccN_Demo, 1 instance = comp, \inst2|s_counter[31]\, inst2|s_counter[31], AccN_Demo, 1 instance = comp, \inst2|Equal0~0\, inst2|Equal0~0, AccN_Demo, 1 -instance = comp, \inst2|Equal0~1\, inst2|Equal0~1, AccN_Demo, 1 instance = comp, \inst2|Equal0~4\, inst2|Equal0~4, AccN_Demo, 1 -instance = comp, \inst2|Equal0~11\, inst2|Equal0~11, AccN_Demo, 1 -instance = comp, \inst2|s_counter~1\, inst2|s_counter~1, AccN_Demo, 1 +instance = comp, \inst2|Equal0~5\, inst2|Equal0~5, AccN_Demo, 1 +instance = comp, \inst2|Add2~38\, inst2|Add2~38, AccN_Demo, 1 +instance = comp, \inst2|Add2~40\, inst2|Add2~40, AccN_Demo, 1 +instance = comp, \inst2|s_counter[20]\, inst2|s_counter[20], AccN_Demo, 1 +instance = comp, \inst2|Add2~42\, inst2|Add2~42, AccN_Demo, 1 +instance = comp, \inst2|s_counter~2\, inst2|s_counter~2, AccN_Demo, 1 instance = comp, \inst2|s_counter[21]\, inst2|s_counter[21], AccN_Demo, 1 +instance = comp, \inst2|s_counter[22]\, inst2|s_counter[22], AccN_Demo, 1 +instance = comp, \inst2|Equal0~6\, inst2|Equal0~6, AccN_Demo, 1 instance = comp, \inst2|Equal0~7\, inst2|Equal0~7, AccN_Demo, 1 instance = comp, \inst2|Equal0~8\, inst2|Equal0~8, AccN_Demo, 1 instance = comp, \inst2|Equal0~9\, inst2|Equal0~9, AccN_Demo, 1 -instance = comp, \inst2|Equal0~10\, inst2|Equal0~10, AccN_Demo, 1 -instance = comp, \inst2|clkOut~0\, inst2|clkOut~0, AccN_Demo, 1 -instance = comp, \inst2|clkOut~2\, inst2|clkOut~2, AccN_Demo, 1 +instance = comp, \inst2|s_counter~3\, inst2|s_counter~3, AccN_Demo, 1 +instance = comp, \inst2|s_counter[19]\, inst2|s_counter[19], AccN_Demo, 1 instance = comp, \inst2|clkOut~1\, inst2|clkOut~1, AccN_Demo, 1 +instance = comp, \inst2|clkOut~2\, inst2|clkOut~2, AccN_Demo, 1 +instance = comp, \inst2|clkOut~0\, inst2|clkOut~0, AccN_Demo, 1 instance = comp, \inst2|clkOut~3\, inst2|clkOut~3, AccN_Demo, 1 -instance = comp, \inst2|Equal0~6\, inst2|Equal0~6, AccN_Demo, 1 instance = comp, \inst2|clkOut~4\, inst2|clkOut~4, AccN_Demo, 1 -instance = comp, \inst2|clkOut~feeder\, inst2|clkOut~feeder, AccN_Demo, 1 instance = comp, \inst2|clkOut\, inst2|clkOut, AccN_Demo, 1 instance = comp, \inst2|clkOut~clkctrl\, inst2|clkOut~clkctrl, AccN_Demo, 1 instance = comp, \SW[16]~input\, SW[16]~input, AccN_Demo, 1