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[LSD] DisplayDemo using block diagram finished

This commit is contained in:
TiagoRG 2023-03-08 20:52:48 +00:00
parent 522822d101
commit ae62913362
Signed by untrusted user who does not match committer: TiagoRG
GPG Key ID: DFCD48E3F420DB42
52 changed files with 180 additions and 173 deletions
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678297834900 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678308727535 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678297835108 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678308727690 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "DisplayDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/ simulation " "Generated file DisplayDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678297835145 ""} { "Info" "IWSC_DONE_HDL_GENERATION" "DisplayDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/ simulation " "Generated file DisplayDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678308727715 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "611 " "Peak virtual memory: 611 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678297835160 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 17:50:35 2023 " "Processing ended: Wed Mar 8 17:50:35 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678297835160 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678297835160 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678297835160 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678297835160 ""} { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "611 " "Peak virtual memory: 611 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678308727725 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 20:52:07 2023 " "Processing ended: Wed Mar 8 20:52:07 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678308727725 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678308727725 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678308727725 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678308727725 ""}

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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678297797885 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308711555 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678297798243 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678308711681 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DisplayDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file DisplayDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DisplayDemo " "Found entity 1: DisplayDemo" { } { { "DisplayDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678297808481 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678297808481 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DisplayDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file DisplayDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DisplayDemo " "Found entity 1: DisplayDemo" { } { { "DisplayDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678308716344 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308716344 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "DisplayDemo " "Elaborating entity \"DisplayDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678297808559 ""} { "Info" "ISGN_START_ELABORATION_TOP" "DisplayDemo " "Elaborating entity \"DisplayDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678308716370 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Bin7SegDecoder Bin7SegDecoder:inst " "Elaborating entity \"Bin7SegDecoder\" for hierarchy \"Bin7SegDecoder:inst\"" { } { { "DisplayDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf" { { 280 544 752 360 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678297808563 ""} { "Info" "ISGN_START_ELABORATION_HIERARCHY" "Bin7SegDecoder Bin7SegDecoder:inst " "Elaborating entity \"Bin7SegDecoder\" for hierarchy \"Bin7SegDecoder:inst\"" { } { { "DisplayDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/DisplayDemo.bdf" { { 280 544 752 360 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678308716371 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678297809508 ""} { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678308716714 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678297810359 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678297810359 ""} { "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678308717020 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678308717020 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678297810404 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678297810404 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678297810404 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678297810404 ""} { "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678308717035 ""} { "Info" "ICUT_CUT_TM_OPINS" "18 " "Implemented 18 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678308717035 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678308717035 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678308717035 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678297810413 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 17:50:10 2023 " "Processing ended: Wed Mar 8 17:50:10 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678297810413 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678297810413 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:34 " "Total CPU time (on all processors): 00:00:34" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678297810413 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678297810413 ""} { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "428 " "Peak virtual memory: 428 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678308717038 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 20:51:57 2023 " "Processing ended: Wed Mar 8 20:51:57 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678308717038 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678308717038 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678308717038 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678308717038 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678297832935 ""} { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678308726168 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678297832935 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 17:50:32 2023 " "Processing started: Wed Mar 8 17:50:32 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678297832935 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678297832935 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678308726168 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 8 20:52:06 2023 " "Processing started: Wed Mar 8 20:52:06 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678308726168 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678308726168 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DisplayDemo -c DisplayDemo " "Command: quartus_sta DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678297832935 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta DisplayDemo -c DisplayDemo " "Command: quartus_sta DisplayDemo -c DisplayDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678308726168 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678297832964 ""} { "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678308726189 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678297833043 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678308726248 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678297833043 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678308726248 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678297833102 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678308726294 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678297833102 ""} { "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678308726294 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "DisplayDemo.sdc " "Synopsys Design Constraints File file not found: 'DisplayDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678297833544 ""} { "Critical Warning" "WSTA_SDC_NOT_FOUND" "DisplayDemo.sdc " "Synopsys Design Constraints File file not found: 'DisplayDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678308726593 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678297833544 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678308726594 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678297833544 ""} { "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678308726594 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678297833544 ""} { "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678308726594 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678297833545 ""} { "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678308726594 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678297833545 ""} { "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678308726594 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678297833545 ""} { "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678308726595 ""}
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678297833549 ""} { "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678308726598 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678297833549 ""} { "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678308726598 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833550 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726598 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833552 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726600 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833552 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726600 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833553 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726600 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833553 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726601 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833554 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726601 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678297833556 ""} { "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678308726602 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678297833575 ""} { "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678308726615 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678297833808 ""} { "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678308726771 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678297833827 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678308726784 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678297833828 ""} { "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678308726784 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678297833828 ""} { "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678308726784 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678297833828 ""} { "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678308726784 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833828 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726784 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833829 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726785 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833829 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726785 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833830 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726786 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833830 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726786 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833830 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726786 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678297833832 ""} { "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678308726787 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678297833889 ""} { "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678308726824 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678297833889 ""} { "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678308726825 ""}
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678297833889 ""} { "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678308726825 ""}
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678297833889 ""} { "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678308726825 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833890 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726825 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833891 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726826 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833891 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726826 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833891 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726827 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678297833892 ""} { "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678308726827 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678297834211 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678308727040 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678297834211 ""} { "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678308727040 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "536 " "Peak virtual memory: 536 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678297834226 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 17:50:34 2023 " "Processing ended: Wed Mar 8 17:50:34 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678297834226 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678297834226 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678297834226 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678297834226 ""} { "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "538 " "Peak virtual memory: 538 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678308727050 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 8 20:52:07 2023 " "Processing ended: Wed Mar 8 20:52:07 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678308727050 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678308727050 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678308727050 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678308727050 ""}

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1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.sta.rdb
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1ano/2semestre/lsd/pratica02/DisplayDemo/db/DisplayDemo.tmw_info Normal file
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@ -0,0 +1,7 @@
start_full_compilation:s:00:00:17
start_analysis_synthesis:s:00:00:06-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:06-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:02-start_full_compilation
start_eda_netlist_writer:s:00:00:01-start_full_compilation

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12
1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.asm.rpt
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@ -1,5 +1,5 @@
Assembler report for DisplayDemo Assembler report for DisplayDemo
Wed Mar 8 17:50:32 2023 Wed Mar 8 20:52:05 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+ +---------------------------------------------------------------+
; Assembler Summary ; ; Assembler Summary ;
+-----------------------+---------------------------------------+ +-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Mar 8 17:50:32 2023 ; ; Assembler Status ; Successful - Wed Mar 8 20:52:05 2023 ;
; Revision Name ; DisplayDemo ; ; Revision Name ; DisplayDemo ;
; Top-level Entity Name ; DisplayDemo ; ; Top-level Entity Name ; DisplayDemo ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus Prime Assembler Info: Running Quartus Prime Assembler
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Wed Mar 8 17:50:29 2023 Info: Processing started: Wed Mar 8 20:52:03 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 365 megabytes Info: Peak virtual memory: 365 megabytes
Info: Processing ended: Wed Mar 8 17:50:32 2023 Info: Processing ended: Wed Mar 8 20:52:05 2023
Info: Elapsed time: 00:00:03 Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:03 Info: Total CPU time (on all processors): 00:00:02

2
1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.done
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@ -1 +1 @@
Wed Mar 8 17:50:35 2023 Wed Mar 8 20:52:08 2023

10
1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.eda.rpt
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@ -1,5 +1,5 @@
EDA Netlist Writer report for DisplayDemo EDA Netlist Writer report for DisplayDemo
Wed Mar 8 17:50:35 2023 Wed Mar 8 20:52:07 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------+ +-------------------------------------------------------------------+
; EDA Netlist Writer Summary ; ; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+ +---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Mar 8 17:50:35 2023 ; ; EDA Netlist Writer Status ; Successful - Wed Mar 8 20:52:07 2023 ;
; Revision Name ; DisplayDemo ; ; Revision Name ; DisplayDemo ;
; Top-level Entity Name ; DisplayDemo ; ; Top-level Entity Name ; DisplayDemo ;
; Family ; Cyclone IV E ; ; Family ; Cyclone IV E ;
@ -81,14 +81,14 @@ https://fpgasoftware.intel.com/eula.
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Wed Mar 8 17:50:34 2023 Info: Processing started: Wed Mar 8 20:52:07 2023
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off DisplayDemo -c DisplayDemo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file DisplayDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/" for EDA simulation tool Info (204019): Generated file DisplayDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 611 megabytes Info: Peak virtual memory: 611 megabytes
Info: Processing ended: Wed Mar 8 17:50:35 2023 Info: Processing ended: Wed Mar 8 20:52:07 2023
Info: Elapsed time: 00:00:01 Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00 Info: Total CPU time (on all processors): 00:00:00

22
1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.rpt
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@ -1,5 +1,5 @@
Fitter report for DisplayDemo Fitter report for DisplayDemo
Wed Mar 8 17:50:27 2023 Wed Mar 8 20:52:03 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -64,7 +64,7 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------+
; Fitter Summary ; ; Fitter Summary ;
+------------------------------------+---------------------------------------------+ +------------------------------------+---------------------------------------------+
; Fitter Status ; Successful - Wed Mar 8 17:50:27 2023 ; ; Fitter Status ; Successful - Wed Mar 8 20:52:03 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; DisplayDemo ; ; Revision Name ; DisplayDemo ;
; Top-level Entity Name ; DisplayDemo ; ; Top-level Entity Name ; DisplayDemo ;
@ -156,7 +156,7 @@ https://fpgasoftware.intel.com/eula.
; ; ; ; ; ;
; Usage by Processor ; % Time Used ; ; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ; ; Processor 1 ; 100.0% ;
; Processors 2-4 ; 0.0% ; ; Processors 2-4 ; 0.1% ;
+----------------------------+-------------+ +----------------------------+-------------+
@ -2569,7 +2569,7 @@ Warning (15705): Ignored locations or region assignments to the following nodes
Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02 Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
@ -2582,20 +2582,20 @@ Info (170195): Router estimated average interconnect usage is 0% of the availabl
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.03 seconds. Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
Info (334003): Started post-fitting delay annotation Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully Info (334004): Delay annotation completed successfully
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 503 warnings Info: Quartus Prime Fitter was successful. 0 errors, 503 warnings
Info: Peak virtual memory: 1149 megabytes Info: Peak virtual memory: 1148 megabytes
Info: Processing ended: Wed Mar 8 17:50:27 2023 Info: Processing ended: Wed Mar 8 20:52:03 2023
Info: Elapsed time: 00:00:16 Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:25 Info: Total CPU time (on all processors): 00:00:09
+----------------------------+ +----------------------------+

2
1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.fit.summary
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@ -1,4 +1,4 @@
Fitter Status : Successful - Wed Mar 8 17:50:27 2023 Fitter Status : Successful - Wed Mar 8 20:52:03 2023
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : DisplayDemo Revision Name : DisplayDemo
Top-level Entity Name : DisplayDemo Top-level Entity Name : DisplayDemo

20
1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.flow.rpt
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@ -1,5 +1,5 @@
Flow report for DisplayDemo Flow report for DisplayDemo
Wed Mar 8 17:50:35 2023 Wed Mar 8 20:52:07 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------+
; Flow Summary ; ; Flow Summary ;
+------------------------------------+---------------------------------------------+ +------------------------------------+---------------------------------------------+
; Flow Status ; Successful - Wed Mar 8 17:50:35 2023 ; ; Flow Status ; Successful - Wed Mar 8 20:52:07 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; DisplayDemo ; ; Revision Name ; DisplayDemo ;
; Top-level Entity Name ; DisplayDemo ; ; Top-level Entity Name ; DisplayDemo ;
@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+ +-------------------+---------------------+
; Option ; Setting ; ; Option ; Setting ;
+-------------------+---------------------+ +-------------------+---------------------+
; Start date & time ; 03/08/2023 17:49:58 ; ; Start date & time ; 03/08/2023 20:51:51 ;
; Main task ; Compilation ; ; Main task ; Compilation ;
; Revision Name ; DisplayDemo ; ; Revision Name ; DisplayDemo ;
+-------------------+---------------------+ +-------------------+---------------------+
@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 2690080394329.167829779807428 ; -- ; -- ; -- ; ; COMPILER_SIGNATURE_ID ; 2690080394329.167830871123418 ; -- ; -- ; -- ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
@ -101,12 +101,12 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:13 ; 1.0 ; 433 MB ; 00:00:33 ; ; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 428 MB ; 00:00:12 ;
; Fitter ; 00:00:16 ; 1.0 ; 1149 MB ; 00:00:24 ; ; Fitter ; 00:00:06 ; 1.0 ; 1148 MB ; 00:00:09 ;
; Assembler ; 00:00:03 ; 1.0 ; 365 MB ; 00:00:03 ; ; Assembler ; 00:00:02 ; 1.0 ; 365 MB ; 00:00:02 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 536 MB ; 00:00:01 ; ; Timing Analyzer ; 00:00:01 ; 1.0 ; 538 MB ; 00:00:01 ;
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 611 MB ; 00:00:00 ; ; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 611 MB ; 00:00:00 ;
; Total ; 00:00:35 ; -- ; -- ; 00:01:01 ; ; Total ; 00:00:14 ; -- ; -- ; 00:00:24 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+ +----------------------+--------------+-------------------------+---------------------+------------------------------------+

16
1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.map.rpt
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@ -1,5 +1,5 @@
Analysis & Synthesis report for DisplayDemo Analysis & Synthesis report for DisplayDemo
Wed Mar 8 17:50:10 2023 Wed Mar 8 20:51:57 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -44,7 +44,7 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ; ; Analysis & Synthesis Summary ;
+------------------------------------+---------------------------------------------+ +------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Mar 8 17:50:10 2023 ; ; Analysis & Synthesis Status ; Successful - Wed Mar 8 20:51:57 2023 ;
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name ; DisplayDemo ; ; Revision Name ; DisplayDemo ;
; Top-level Entity Name ; DisplayDemo ; ; Top-level Entity Name ; DisplayDemo ;
@ -262,7 +262,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------+--------------+ +----------------+--------------+
; Partition Name ; Elapsed Time ; ; Partition Name ; Elapsed Time ;
+----------------+--------------+ +----------------+--------------+
; Top ; 00:00:01 ; ; Top ; 00:00:00 ;
+----------------+--------------+ +----------------+--------------+
@ -272,7 +272,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis Info: Running Quartus Prime Analysis & Synthesis
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Wed Mar 8 17:49:57 2023 Info: Processing started: Wed Mar 8 20:51:51 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DisplayDemo -c DisplayDemo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
@ -291,9 +291,9 @@ Info (21057): Implemented 37 device resources after synthesis - the final resour
Info (21059): Implemented 18 output pins Info (21059): Implemented 18 output pins
Info (21061): Implemented 14 logic cells Info (21061): Implemented 14 logic cells
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Peak virtual memory: 433 megabytes Info: Peak virtual memory: 428 megabytes
Info: Processing ended: Wed Mar 8 17:50:10 2023 Info: Processing ended: Wed Mar 8 20:51:57 2023
Info: Elapsed time: 00:00:13 Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:34 Info: Total CPU time (on all processors): 00:00:13

2
1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.map.summary
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@ -1,4 +1,4 @@
Analysis & Synthesis Status : Successful - Wed Mar 8 17:50:10 2023 Analysis & Synthesis Status : Successful - Wed Mar 8 20:51:57 2023
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Revision Name : DisplayDemo Revision Name : DisplayDemo
Top-level Entity Name : DisplayDemo Top-level Entity Name : DisplayDemo

BIN
1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sof
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Binary file not shown.

12
1ano/2semestre/lsd/pratica02/DisplayDemo/output_files/DisplayDemo.sta.rpt
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@ -1,5 +1,5 @@
Timing Analyzer report for DisplayDemo Timing Analyzer report for DisplayDemo
Wed Mar 8 17:50:34 2023 Wed Mar 8 20:52:07 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
@ -96,7 +96,7 @@ https://fpgasoftware.intel.com/eula.
; ; ; ; ; ;
; Usage by Processor ; % Time Used ; ; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ; ; Processor 1 ; 100.0% ;
; Processors 2-4 ; 0.3% ; ; Processors 2-4 ; 0.2% ;
+----------------------------+-------------+ +----------------------------+-------------+
@ -486,7 +486,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
Info: ******************************************************************* Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer Info: Running Quartus Prime Timing Analyzer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Wed Mar 8 17:50:32 2023 Info: Processing started: Wed Mar 8 20:52:06 2023
Info: Command: quartus_sta DisplayDemo -c DisplayDemo Info: Command: quartus_sta DisplayDemo -c DisplayDemo
Info: qsta_default_script.tcl version: #1 Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
@ -534,9 +534,9 @@ Info (332140): No Minimum Pulse Width paths to report
Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 536 megabytes Info: Peak virtual memory: 538 megabytes
Info: Processing ended: Wed Mar 8 17:50:34 2023 Info: Processing ended: Wed Mar 8 20:52:07 2023
Info: Elapsed time: 00:00:02 Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01 Info: Total CPU time (on all processors): 00:00:01

2
1ano/2semestre/lsd/pratica02/DisplayDemo/simulation/modelsim/DisplayDemo.vho
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@ -17,7 +17,7 @@
-- PROGRAM "Quartus Prime" -- PROGRAM "Quartus Prime"
-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" -- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
-- DATE "03/08/2023 17:50:35" -- DATE "03/08/2023 20:52:07"
-- --
-- Device: Altera EP4CE115F29C7 Package FBGA780 -- Device: Altera EP4CE115F29C7 Package FBGA780