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[LSD] pratica06 part1 added (with enable and direction selector included)

This commit is contained in:
TiagoRG 2023-03-29 13:06:32 +01:00
parent 6a7822da70
commit 9801a71384
Signed by untrusted user who does not match committer: TiagoRG
GPG Key ID: DFCD48E3F420DB42
7 changed files with 789 additions and 0 deletions
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31
1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/FreqDivider.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider is
generic(divFactor : positive := 10);
port(
clkIn : in std_logic;
clkOut : out std_logic);
end FreqDivider;
architecture Behavioral of FreqDivider is
subtype TCounter is natural range 0 to divFactor - 1;
signal s_divCounter : TCounter := 0;
begin
assert(divFactor >= 2);
process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_divCounter >= (divFactor - 1)) then
clkOut <= '0';
s_divCounter <= 0;
else
if (s_divCounter = (divFactor / 2 - 1)) then
clkOut <= '1';
end if;
s_divCounter <= s_divCounter + 1;
end if;
end if;
end process;
end Behavioral;

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1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/ShiftRegister4.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ShiftRegister4 is
port
(
clk : in std_logic;
sin : in std_logic;
toleft : in std_logic;
dataOut : out std_logic_vector(3 downto 0)
);
end ShiftRegister4;
architecture Behav of ShiftRegister4 is
signal aux : std_logic_vector(3 downto 0) := "0000";
begin
process(clk)
begin
if (rising_edge(clk)) then
if (toleft = '1') then
aux <= aux(2 downto 0) & sin; -- deslocamento à esquerda
else
aux <= sin & aux(3 downto 1); -- deslocamento à direita
end if;
end if;
end process;
dataOut <= aux;
end Behav;

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1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/ShiftRegister4.vwf Normal file
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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off ShiftRegister_Demo -c ShiftRegister_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/ShiftRegister4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/simulation/qsim/ShiftRegister4.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off ShiftRegister_Demo -c ShiftRegister_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/ShiftRegister4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/simulation/qsim/ShiftRegister4.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/simulation/qsim/" ShiftRegister_Demo -c ShiftRegister_Demo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/simulation/qsim/" ShiftRegister_Demo -c ShiftRegister_Demo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work ShiftRegister_Demo.vho
vcom -work work ShiftRegister4.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.ShiftRegister4_vhd_vec_tst
vcd file -direction ShiftRegister_Demo.msim.vcd
vcd add -internal ShiftRegister4_vhd_vec_tst/*
vcd add -internal ShiftRegister4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work ShiftRegister_Demo.vho
vcom -work work ShiftRegister4.vwf.vht
vsim -novopt -c -t 1ps -sdfmax ShiftRegister4_vhd_vec_tst/i1=ShiftRegister_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.ShiftRegister4_vhd_vec_tst
vcd file -direction ShiftRegister_Demo.msim.vcd
vcd add -internal ShiftRegister4_vhd_vec_tst/*
vcd add -internal ShiftRegister4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("dataOut")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("dataOut[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("sin")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("toleft")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 50;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
}
}
}
TRANSITION_LIST("dataOut[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("sin")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 90.0;
LEVEL 1 FOR 90.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 90.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 10.0;
}
}
TRANSITION_LIST("toleft")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 500.0;
LEVEL 1 FOR 500.0;
}
}
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "sin";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "toleft";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "dataOut";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
CHILDREN = 4, 5, 6, 7;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 3;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

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1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/ShiftRegisterN.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ShiftRegisterN is
generic ( size : positive := 4 );
port
(
clk : in std_logic;
sin : in std_logic;
toleft : in std_logic;
enable : in std_logic;
dataOut : out std_logic_vector((size-1) downto 0)
);
end ShiftRegisterN;
architecture Behav of ShiftRegisterN is
signal aux : std_logic_vector((size-1) downto 0) := (others => '0');
begin
process(clk)
begin
if (rising_edge(clk)) then
if (enable = '1') then
if (toleft = '1') then
aux <= aux((size-2) downto 0) & sin; -- deslocamento à esquerda
else
aux <= sin & aux((size-1) downto 1); -- deslocamento à direita
end if;
end if;
end if;
end process;
dataOut <= aux;
end Behav;

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1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/ShiftRegisterN.vwf Normal file
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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off ShiftRegister_Demo -c ShiftRegister_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/ShiftRegisterN.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/simulation/qsim/ShiftRegisterN.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off ShiftRegister_Demo -c ShiftRegister_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/ShiftRegisterN.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/simulation/qsim/ShiftRegisterN.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/simulation/qsim/" ShiftRegister_Demo -c ShiftRegister_Demo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/simulation/qsim/" ShiftRegister_Demo -c ShiftRegister_Demo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work ShiftRegister_Demo.vho
vcom -work work ShiftRegisterN.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.ShiftRegisterN_vhd_vec_tst
vcd file -direction ShiftRegister_Demo.msim.vcd
vcd add -internal ShiftRegisterN_vhd_vec_tst/*
vcd add -internal ShiftRegisterN_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work ShiftRegister_Demo.vho
vcom -work work ShiftRegisterN.vwf.vht
vsim -novopt -c -t 1ps -sdfmax ShiftRegisterN_vhd_vec_tst/i1=ShiftRegister_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.ShiftRegisterN_vhd_vec_tst
vcd file -direction ShiftRegister_Demo.msim.vcd
vcd add -internal ShiftRegisterN_vhd_vec_tst/*
vcd add -internal ShiftRegisterN_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("dataOut")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("dataOut[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("dataOut[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "dataOut";
}
SIGNAL("sin")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("toleft")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 50;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
}
}
}
TRANSITION_LIST("dataOut[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("dataOut[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("sin")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 90.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 90.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 90.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 90.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 280.0;
}
}
TRANSITION_LIST("toleft")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1;
LEVEL 0 FOR 500.0;
LEVEL 1 FOR 500.0;
}
}
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "sin";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "toleft";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "dataOut";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
CHILDREN = 4, 5, 6, 7;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 3;
}
DISPLAY_LINE
{
CHANNEL = "dataOut[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 3;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

37
1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/ShiftRegister_Demo.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity ShiftRegister_Demo is
generic ( size : positive := 18);
port
(
SW : in std_logic_vector(2 downto 0);
CLOCK_50 : in std_logic;
LEDR : out std_logic_vector((size-1) downto 0)
);
end ShiftRegister_Demo;
architecture Shell of ShiftRegister_Demo is
signal clk : std_logic;
begin
freqDevider : entity work.FreqDivider(Behavioral)
generic map (divFactor => 25_000_000)
port map
(
clkIn => CLOCK_50,
clkOut => clk
);
system : entity work.ShiftRegisterN(Behav)
generic map (size => size)
port map
(
clk => clk,
sin => SW(0),
toleft => SW(1),
enable => SW(2),
dataOut => LEDR
);
end Shell;

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1ano/2semestre/lsd/pratica06/ShiftRegister_Demo/output_files/ShiftRegister_Demo.sof Normal file
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