[LSD] Mini Project of 2021-2022 added (working fine I think 💀)
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TiagoRG
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60ea30e569
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DFCD48E3F420DB42
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity Bin7SegDecoder is
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port
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(
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binInput : in std_logic_vector(3 downto 0);
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enable : in std_logic;
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decOut_n : out std_logic_vector(6 downto 0)
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);
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end Bin7SegDecoder;
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architecture Behavioral of Bin7SegDecoder is
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begin
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decOut_n <= "1111111" when (enable = '0' ) else -- disabled
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"1111001" when (binInput = "0001") else --1
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"0100100" when (binInput = "0010") else --2
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"0110000" when (binInput = "0011") else --3
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"0011001" when (binInput = "0100") else --4
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"0010010" when (binInput = "0101") else --5
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"0000010" when (binInput = "0110") else --6
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"1111000" when (binInput = "0111") else --7
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"0000000" when (binInput = "1000") else --8
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"0010000" when (binInput = "1001") else --9
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"0001000" when (binInput = "1010") else --A
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"0000011" when (binInput = "1011") else --b
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"1000110" when (binInput = "1100") else --C
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"0100001" when (binInput = "1101") else --d
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"0000110" when (binInput = "1110") else --E
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"0001110" when (binInput = "1111") else --F
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"1000000"; --0
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end Behavioral;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity Counter is
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port
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(
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clk : in std_logic;
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reset : in std_logic;
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count : out std_logic_vector(3 downto 0)
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);
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end Counter;
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architecture Behavioral of Counter is
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signal up : std_logic := '1';
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signal s_count : unsigned(3 downto 0) := to_unsigned(0, 4);
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begin
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process(clk, reset)
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begin
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if (reset = '1') then
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s_count <= to_unsigned(0, 4);
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up <= '1';
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elsif (rising_edge(clk)) then
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if (up = '1') then
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if (std_logic_vector(s_count) = "1111") then
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s_count <= s_count - 1;
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up <= '0';
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else
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s_count <= s_count + 1;
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end if;
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else
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if (std_logic_vector(s_count) = "0000") then
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s_count <= s_count + 1;
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up <= '1';
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else
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s_count <= s_count - 1;
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end if;
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end if;
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end if;
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end process;
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count <= std_logic_vector(s_count);
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end Behavioral;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity FreqDivider is
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generic(divFactor : positive := 10);
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port
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(
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clkIn : in std_logic;
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multi : in positive := 1;
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clkOut : out std_logic
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);
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end FreqDivider;
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architecture Behavioral of FreqDivider is
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subtype TCounter is natural range 0 to divFactor - 1;
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signal s_divFactor : positive := 10;
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signal s_divCounter : TCounter := 0;
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begin
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s_divFactor <= divFactor / multi;
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assert(divFactor >= 2);
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process(clkIn)
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begin
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if (rising_edge(clkIn)) then
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if (s_divCounter >= (s_divFactor - 1)) then
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clkOut <= '0';
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s_divCounter <= 0;
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else
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if (s_divCounter = (s_divFactor / 2 - 1)) then
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clkOut <= '1';
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end if;
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s_divCounter <= s_divCounter + 1;
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end if;
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end if;
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end process;
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end Behavioral;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity HexToDec4Bit is
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port
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(
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hexIn : in std_logic_vector(3 downto 0);
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cin : in std_logic;
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decOut0 : out std_logic_vector(3 downto 0);
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decOut1 : out std_logic_vector(3 downto 0)
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);
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end HexToDec4Bit;
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architecture Behavioral of HexToDec4Bit is
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begin
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process (hexIn, cin) is
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begin
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if cin = '1' then
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if hexIn = "0000" then
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decOut0 <= "0110";
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elsif hexIn = "0001" then
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decOut0 <= "0111";
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elsif hexIn = "0010" then
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decOut0 <= "1000";
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elsif hexIn = "0011" then
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decOut0 <= "1001";
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elsif hexIn = "0100" then
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decOut0 <= "0000";
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elsif hexIn = "0101" then
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decOut0 <= "0001";
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elsif hexIn = "0110" then
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decOut0 <= "0010";
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elsif hexIn = "0111" then
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decOut0 <= "0011";
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elsif hexIn = "1000" then
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decOut0 <= "0100";
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elsif hexIn = "1001" then
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decOut0 <= "0101";
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elsif hexIn = "1010" then
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decOut0 <= "0110";
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elsif hexIn = "1011" then
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decOut0 <= "0111";
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elsif hexIn = "1100" then
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decOut0 <= "1000";
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elsif hexIn = "1101" then
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decOut0 <= "1001";
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else
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decOut0 <= "0000";
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end if;
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if hexIn < "0100" then
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decOut1 <= "0001";
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elsif hexIn < "1110" then
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decOut1 <= "0010";
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else
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decOut1 <= "0011";
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end if;
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else
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if hexIn < "1010" then
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decOut0 <= hexIn;
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decOut1 <= "0000";
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else
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if hexIn = "1010" then
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decOut0 <= "0000";
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elsif hexIn = "1011" then
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decOut0 <= "0001";
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elsif hexIn = "1100" then
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decOut0 <= "0010";
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elsif hexIn = "1101" then
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decOut0 <= "0011";
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elsif hexIn = "1110" then
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decOut0 <= "0100";
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else
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decOut0 <= "0101";
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end if;
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decOut1 <= "0001";
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end if;
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end if;
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end process;
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end Behavioral;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity LedDisplayer is
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port
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(
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count : in std_logic_vector(3 downto 0);
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ledOut : out std_logic_vector(14 downto 0)
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);
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end LedDisplayer;
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architecture Behavioral of LedDisplayer is
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begin
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with count select
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ledOut <= "000000000000000" when "0000",
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"000000000000001" when "0001",
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"000000000000011" when "0010",
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"000000000000111" when "0011",
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"000000000001111" when "0100",
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"000000000011111" when "0101",
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"000000000111111" when "0110",
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"000000001111111" when "0111",
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"000000011111111" when "1000",
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"000000111111111" when "1001",
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"000001111111111" when "1010",
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"000011111111111" when "1011",
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"000111111111111" when "1100",
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"001111111111111" when "1101",
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"011111111111111" when "1110",
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"111111111111111" when "1111";
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end Behavioral;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity MiniProj_Demo is
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port
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(
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CLOCK_50 : in std_logic;
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KEY : in std_logic_vector(1 downto 0);
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LEDR : out std_logic_vector(14 downto 0);
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HEX0 : out std_logic_vector(6 downto 0);
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HEX1 : out std_logic_vector(6 downto 0)
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);
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end MiniProj_Demo;
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architecture Shell of MiniProj_Demo is
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signal s_clk_def, s_clk_div : std_logic;
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signal s_speed : positive := 4;
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signal s_reset : std_logic;
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signal s_count : std_logic_vector(3 downto 0);
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signal s_display0, s_display1 : std_logic_vector(3 downto 0);
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begin
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s_clk_def <= CLOCK_50;
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s_reset <= not KEY(0);
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speed_select : entity work.SpeedSelect(Behavioral)
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port map
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(
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toggle => not KEY(1),
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reset => s_reset,
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speed => s_speed
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);
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freq_divider : entity work.FreqDivider(Behavioral)
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generic map (divFactor => 50_000_000)
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port map
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(
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clkIn => s_clk_def,
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multi => s_speed,
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clkOut => s_clk_div
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);
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counter : entity work.Counter(Behavioral)
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port map
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(
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clk => s_clk_div,
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reset => s_reset,
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count => s_count
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);
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led_display : entity work.LedDisplayer(Behavioral)
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port map
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(
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count => s_count,
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ledOut => LEDR
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);
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hex_to_dec : entity work.HexToDec4Bit(Behavioral)
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port map
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(
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hexIn => s_count,
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cin => '0',
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decOut0 => s_display0,
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decOut1 => s_display1
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);
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display0 : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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enable => '1',
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binInput => s_display0,
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decOut_n => HEX0
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);
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display1 : entity work.Bin7SegDecoder(Behavioral)
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port map
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(
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enable => '1',
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binInput => s_display1,
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decOut_n => HEX1
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);
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end Shell;
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@ -0,0 +1,31 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity SpeedSelect is
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port
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(
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toggle : in std_logic;
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reset : in std_logic;
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speed : out positive := 4
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);
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end SpeedSelect;
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architecture Behavioral of SpeedSelect is
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signal current_speed : positive := 4;
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begin
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process(toggle, reset)
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begin
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if (reset = '1') then
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current_speed <= 4;
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else
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if (toggle = '1') then
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if (current_speed = 1) then
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current_speed <= 4;
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else
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current_speed <= 1;
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end if;
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end if;
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end if;
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end process;
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speed <= current_speed;
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end Behavioral;
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