From 8a731a9fc914cd11d1e5a8d49f4e9ea1b45a4c62 Mon Sep 17 00:00:00 2001
From: TiagoRG <35657250+TiagoRG@users.noreply.github.com>
Date: Wed, 5 Apr 2023 21:23:18 +0100
Subject: [PATCH] [LSD] SeqShiftUnit_Demo added (pratica06 - part2)
---
.../SeqShiftUnit_Demo/FreqDivider.bsf | 50 +
.../SeqShiftUnit_Demo/FreqDivider.vhd | 33 +
.../SeqShiftUnit_Demo/SeqShiftUnit.bsf | 93 ++
.../SeqShiftUnit_Demo/SeqShiftUnit.vhd | 52 ++
.../SeqShiftUnit_Demo/SeqShiftUnit.vwf | 872 ++++++++++++++++++
.../SeqShiftUnit_Demo/SeqShiftUnit_Demo.bdf | 350 +++++++
.../output_files/SeqShiftUnit_Demo.sof | Bin 0 -> 3541753 bytes
7 files changed, 1450 insertions(+)
create mode 100644 1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.bsf
create mode 100644 1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.vhd
create mode 100644 1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.bsf
create mode 100644 1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vhd
create mode 100644 1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf
create mode 100644 1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit_Demo.bdf
create mode 100644 1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/output_files/SeqShiftUnit_Demo.sof
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.bsf b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.bsf
new file mode 100644
index 0000000..b3344f5
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.bsf
@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 16 16 160 96)
+ (text "FreqDivider" (rect 5 0 52 12)(font "Arial" ))
+ (text "inst" (rect 8 64 20 76)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "clkIn" (rect 0 0 17 12)(font "Arial" ))
+ (text "clkIn" (rect 21 27 38 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 144 32)
+ (output)
+ (text "clkOut" (rect 0 0 24 12)(font "Arial" ))
+ (text "clkOut" (rect 99 27 123 39)(font "Arial" ))
+ (line (pt 144 32)(pt 128 32)(line_width 1))
+ )
+ (parameter
+ "divFactor"
+ "10"
+ ""
+ (type "PARAMETER_SIGNED_DEC") )
+ (drawing
+ (rectangle (rect 16 16 128 64)(line_width 1))
+ )
+ (annotation_block (parameter)(rect 160 -64 260 16))
+)
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.vhd b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.vhd
new file mode 100644
index 0000000..e79de6d
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/FreqDivider.vhd
@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity FreqDivider is
+ generic(divFactor : positive := 10);
+ port
+ (
+ clkIn : in std_logic;
+ clkOut : out std_logic
+ );
+end FreqDivider;
+
+architecture Behavioral of FreqDivider is
+ subtype TCounter is natural range 0 to divFactor - 1;
+ signal s_divCounter : TCounter := 0;
+begin
+ assert(divFactor >= 2);
+ process(clkIn)
+ begin
+ if (rising_edge(clkIn)) then
+ if (s_divCounter >= (divFactor - 1)) then
+ clkOut <= '0';
+ s_divCounter <= 0;
+ else
+ if (s_divCounter = (divFactor / 2 - 1)) then
+ clkOut <= '1';
+ end if;
+ s_divCounter <= s_divCounter + 1;
+ end if;
+ end if;
+ end process;
+end Behavioral;
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.bsf b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.bsf
new file mode 100644
index 0000000..a6512c6
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.bsf
@@ -0,0 +1,93 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 16 16 208 192)
+ (text "SeqShiftUnit" (rect 5 0 53 12)(font "Arial" ))
+ (text "inst" (rect 8 160 20 172)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "clk" (rect 0 0 10 12)(font "Arial" ))
+ (text "clk" (rect 21 27 31 39)(font "Arial" ))
+ (line (pt 0 32)(pt 16 32)(line_width 1))
+ )
+ (port
+ (pt 0 48)
+ (input)
+ (text "dataIn[7..0]" (rect 0 0 43 12)(font "Arial" ))
+ (text "dataIn[7..0]" (rect 21 43 64 55)(font "Arial" ))
+ (line (pt 0 48)(pt 16 48)(line_width 3))
+ )
+ (port
+ (pt 0 64)
+ (input)
+ (text "siLeft" (rect 0 0 22 12)(font "Arial" ))
+ (text "siLeft" (rect 21 59 43 71)(font "Arial" ))
+ (line (pt 0 64)(pt 16 64)(line_width 1))
+ )
+ (port
+ (pt 0 80)
+ (input)
+ (text "siRight" (rect 0 0 27 12)(font "Arial" ))
+ (text "siRight" (rect 21 75 48 87)(font "Arial" ))
+ (line (pt 0 80)(pt 16 80)(line_width 1))
+ )
+ (port
+ (pt 0 96)
+ (input)
+ (text "loadEn" (rect 0 0 27 12)(font "Arial" ))
+ (text "loadEn" (rect 21 91 48 103)(font "Arial" ))
+ (line (pt 0 96)(pt 16 96)(line_width 1))
+ )
+ (port
+ (pt 0 112)
+ (input)
+ (text "rotate" (rect 0 0 22 12)(font "Arial" ))
+ (text "rotate" (rect 21 107 43 119)(font "Arial" ))
+ (line (pt 0 112)(pt 16 112)(line_width 1))
+ )
+ (port
+ (pt 0 128)
+ (input)
+ (text "dirLeft" (rect 0 0 25 12)(font "Arial" ))
+ (text "dirLeft" (rect 21 123 46 135)(font "Arial" ))
+ (line (pt 0 128)(pt 16 128)(line_width 1))
+ )
+ (port
+ (pt 0 144)
+ (input)
+ (text "shArith" (rect 0 0 29 12)(font "Arial" ))
+ (text "shArith" (rect 21 139 50 151)(font "Arial" ))
+ (line (pt 0 144)(pt 16 144)(line_width 1))
+ )
+ (port
+ (pt 192 32)
+ (output)
+ (text "dataOut[7..0]" (rect 0 0 50 12)(font "Arial" ))
+ (text "dataOut[7..0]" (rect 121 27 171 39)(font "Arial" ))
+ (line (pt 192 32)(pt 176 32)(line_width 3))
+ )
+ (drawing
+ (rectangle (rect 16 16 176 160)(line_width 1))
+ )
+)
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vhd b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vhd
new file mode 100644
index 0000000..457132f
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vhd
@@ -0,0 +1,52 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity SeqShiftUnit is
+ port
+ (
+ clk : in std_logic;
+ dataIn : in std_logic_vector(7 downto 0);
+ siLeft : in std_logic;
+ siRight : in std_logic;
+ loadEn : in std_logic;
+ rotate : in std_logic;
+ dirLeft : in std_logic;
+ shArith : in std_logic;
+ dataOut : out std_logic_vector(7 downto 0)
+ );
+end SeqShiftUnit;
+
+architecture Behavioral of SeqShiftUnit is
+ signal s_shiftReg : std_logic_vector(7 downto 0);
+begin
+ process (clk)
+ begin
+ if (falling_edge(clk)) then
+ if (loadEn = '1') then
+ s_shiftReg <= dataIn;
+
+ elsif (rotate = '1') then
+ if (dirLeft = '1') then
+ s_shiftReg <= s_shiftReg(6 downto 0) & s_shiftReg(7);
+ else
+ s_shiftReg <= s_shiftReg(0) & s_shiftReg(7 downto 1);
+ end if;
+
+ elsif (shArith = '1') then
+ if (dirLeft = '1') then
+ s_shiftReg <= s_shiftReg(6 downto 0) & '0';
+ else
+ s_shiftReg <= s_shiftReg(7) & s_shiftReg(7 downto 1);
+ end if;
+
+ else
+ if (dirLeft = '1') then
+ s_shiftReg <= s_shiftReg(6 downto 0) & siLeft;
+ else
+ s_shiftReg <= siRight & s_shiftReg(7 downto 1);
+ end if;
+ end if;
+ end if;
+ end process;
+ dataOut <= s_ShiftReg;
+end Behavioral;
\ No newline at end of file
diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf
new file mode 100644
index 0000000..5a6f4b5
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf
@@ -0,0 +1,872 @@
+/*
+quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off SeqShiftUnit_Demo -c SeqShiftUnit_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/SeqShiftUnit.vwf.vht"
+quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off SeqShiftUnit_Demo -c SeqShiftUnit_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/SeqShiftUnit.vwf.vht"
+quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/" SeqShiftUnit_Demo -c SeqShiftUnit_Demo
+quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/" SeqShiftUnit_Demo -c SeqShiftUnit_Demo
+onerror {exit -code 1}
+vlib work
+vcom -work work SeqShiftUnit_Demo.vho
+vcom -work work SeqShiftUnit.vwf.vht
+vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.SeqShiftUnit_vhd_vec_tst
+vcd file -direction SeqShiftUnit_Demo.msim.vcd
+vcd add -internal SeqShiftUnit_vhd_vec_tst/*
+vcd add -internal SeqShiftUnit_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+ echo "Simulation time: $::now ps"
+ if { [string equal running [runStatus]] } {
+ after 2500 simTimestamp
+ }
+}
+after 2500 simTimestamp
+run -all
+quit -f
+
+
+onerror {exit -code 1}
+vlib work
+vcom -work work SeqShiftUnit_Demo.vho
+vcom -work work SeqShiftUnit.vwf.vht
+vsim -novopt -c -t 1ps -sdfmax SeqShiftUnit_vhd_vec_tst/i1=SeqShiftUnit_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.SeqShiftUnit_vhd_vec_tst
+vcd file -direction SeqShiftUnit_Demo.msim.vcd
+vcd add -internal SeqShiftUnit_vhd_vec_tst/*
+vcd add -internal SeqShiftUnit_vhd_vec_tst/i1/*
+proc simTimestamp {} {
+ echo "Simulation time: $::now ps"
+ if { [string equal running [runStatus]] } {
+ after 2500 simTimestamp
+ }
+}
+after 2500 simTimestamp
+run -all
+quit -f
+
+
+vhdl
+*/
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+
+HEADER
+{
+ VERSION = 1;
+ TIME_UNIT = ns;
+ DATA_OFFSET = 0.0;
+ DATA_DURATION = 1000.0;
+ SIMULATION_TIME = 0.0;
+ GRID_PHASE = 0.0;
+ GRID_PERIOD = 10.0;
+ GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("clk")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("dataIn")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 8;
+ LSB_INDEX = 0;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("dataIn[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dataIn[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "dataIn";
+}
+
+SIGNAL("dirLeft")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("loadEn")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("rotate")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("shArith")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("siLeft")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("siRight")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("dataOut")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 8;
+ LSB_INDEX = 0;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("dataOut[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+SIGNAL("dataOut[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "dataOut";
+}
+
+TRANSITION_LIST("clk")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 100;
+ LEVEL 0 FOR 5.0;
+ LEVEL 1 FOR 5.0;
+ }
+ }
+}
+
+TRANSITION_LIST("dataIn[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dataIn[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 1000.0;
+ }
+}
+
+TRANSITION_LIST("dirLeft")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 25;
+ LEVEL 0 FOR 20.0;
+ LEVEL 1 FOR 20.0;
+ }
+ }
+}
+
+TRANSITION_LIST("loadEn")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 50;
+ LEVEL 0 FOR 10.0;
+ LEVEL 1 FOR 10.0;
+ }
+ }
+}
+
+TRANSITION_LIST("rotate")
+{
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diff --git a/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit_Demo.bdf b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit_Demo.bdf
new file mode 100644
index 0000000..e202bfb
--- /dev/null
+++ b/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit_Demo.bdf
@@ -0,0 +1,350 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2020 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
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