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[LSD] pratica04 part3 added

This commit is contained in:
TiagoRG 2023-03-21 22:40:05 +00:00
parent c85eb336e5
commit 7ff3a22cc6
Signed by untrusted user who does not match committer: TiagoRG
GPG Key ID: DFCD48E3F420DB42
132 changed files with 11971 additions and 0 deletions
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44
1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 224 96)
(text "Bin7SegDecoder" (rect 5 0 71 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "binInput[3..0]" (rect 0 0 49 12)(font "Arial" ))
(text "binInput[3..0]" (rect 21 27 70 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 208 32)
(output)
(text "decOut_n[6..0]" (rect 0 0 59 12)(font "Arial" ))
(text "decOut_n[6..0]" (rect 128 27 187 39)(font "Arial" ))
(line (pt 208 32)(pt 192 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 192 64)(line_width 1))
)
)

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1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port
(
binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0)
);
end Bin7SegDecoder;
architecture Behavioral of Bin7SegDecoder is
begin
decOut_n <= "1111001" when (binInput = "0001") else --1
"0100100" when (binInput = "0010") else --2
"0110000" when (binInput = "0011") else --3
"0011001" when (binInput = "0100") else --4
"0010010" when (binInput = "0101") else --5
"0000010" when (binInput = "0110") else --6
"1111000" when (binInput = "0111") else --7
"0000000" when (binInput = "1000") else --8
"0010000" when (binInput = "1001") else --9
"0001000" when (binInput = "1010") else --A
"0000011" when (binInput = "1011") else --b
"1000110" when (binInput = "1100") else --C
"0100001" when (binInput = "1101") else --d
"0000110" when (binInput = "1110") else --E
"0001110" when (binInput = "1111") else --F
"1000000"; --0
end Behavioral;

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1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd.bak Normal file
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1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 256 232 424 248)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "KEY[1]" (rect 5 0 39 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 192 248 256 264))
)
(pin
(input)
(rect 256 248 424 264)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "SW[0]" (rect 5 0 35 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 192 264 256 280))
)
(pin
(input)
(rect 152 176 320 192)
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "CLOCK_50" (rect 5 0 63 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 88 192 152 208))
)
(pin
(output)
(rect 872 216 1048 232)
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
(text "HEX0[6..0]" (rect 90 0 144 11)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
(annotation_block (location)(rect 1048 232 1112 248))
)
(symbol
(rect 432 224 480 256)
(text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6)))
(text "inst3" (rect 3 21 27 34)(font "Intel Clear" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 16 18)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 16 18)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16))
)
(port
(pt 48 16)
(output)
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
(line (pt 13 25)(pt 13 7))
(line (pt 13 7)(pt 31 16))
(line (pt 13 25)(pt 31 16))
(circle (rect 31 12 39 20))
)
)
(symbol
(rect 672 192 880 272)
(text "Bin7SegDecoder" (rect 5 0 89 11)(font "Arial" ))
(text "hex" (rect 8 64 28 75)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "binInput[3..0]" (rect 0 0 63 11)(font "Arial" ))
(text "binInput[3..0]" (rect 21 27 84 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 208 32)
(output)
(text "decOut_n[6..0]" (rect 0 0 73 11)(font "Arial" ))
(text "decOut_n[6..0]" (rect 126 27 199 38)(font "Arial" ))
(line (pt 208 32)(pt 192 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 192 64))
)
)
(symbol
(rect 488 192 664 304)
(text "CounterUpDown4" (rect 5 0 94 11)(font "Arial" ))
(text "inst" (rect 8 96 26 107)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 27 11)(font "Arial" ))
(text "clock" (rect 21 27 48 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "reset" (rect 0 0 25 11)(font "Arial" ))
(text "reset" (rect 21 43 46 54)(font "Arial" ))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "upDown" (rect 0 0 42 11)(font "Arial" ))
(text "upDown" (rect 21 59 63 70)(font "Arial" ))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 176 32)
(output)
(text "count[3..0]" (rect 0 0 51 11)(font "Arial" ))
(text "count[3..0]" (rect 112 27 163 38)(font "Arial" ))
(line (pt 176 32)(pt 160 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 160 96))
)
)
(symbol
(rect 328 152 472 232)
(text "FreqDivider" (rect 5 0 64 11)(font "Arial" ))
(text "inst1" (rect 8 64 32 77)(font "Intel Clear" ))
(port
(pt 0 32)
(input)
(text "clkIn" (rect 0 0 24 11)(font "Arial" ))
(text "clkIn" (rect 21 27 45 38)(font "Arial" ))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 144 32)
(output)
(text "clkOut" (rect 0 0 33 11)(font "Arial" ))
(text "clkOut" (rect 96 27 129 38)(font "Arial" ))
(line (pt 144 32)(pt 128 32))
)
(drawing
(rectangle (rect 16 16 128 64))
)
)
(connector
(pt 480 224)
(pt 488 224)
)
(connector
(pt 488 240)
(pt 480 240)
)
(connector
(pt 432 240)
(pt 424 240)
)
(connector
(pt 664 224)
(pt 672 224)
(bus)
)
(connector
(pt 872 224)
(pt 880 224)
(bus)
)
(connector
(pt 424 256)
(pt 488 256)
)
(connector
(pt 480 184)
(pt 472 184)
)
(connector
(pt 480 224)
(pt 480 184)
)
(connector
(pt 328 184)
(pt 320 184)
)

31
1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qpf Normal file
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@ -0,0 +1,31 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 16:44:06 March 16, 2023
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "20.1"
DATE = "16:44:06 March 16, 2023"
# Revisions
PROJECT_REVISION = "CounterDemo"

588
1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qsf Normal file
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@ -0,0 +1,588 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 16:44:06 March 16, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# CounterDemo_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY CounterDemo
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:44:06 MARCH 16, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_location_assignment PIN_Y2 -to CLOCK_50
set_location_assignment PIN_AG14 -to CLOCK2_50
set_location_assignment PIN_AG15 -to CLOCK3_50
set_location_assignment PIN_AH14 -to SMA_CLKIN
set_location_assignment PIN_AE23 -to SMA_CLKOUT
set_location_assignment PIN_M23 -to KEY[0]
set_location_assignment PIN_M21 -to KEY[1]
set_location_assignment PIN_N21 -to KEY[2]
set_location_assignment PIN_R24 -to KEY[3]
set_location_assignment PIN_AB28 -to SW[0]
set_location_assignment PIN_AC28 -to SW[1]
set_location_assignment PIN_AC27 -to SW[2]
set_location_assignment PIN_AD27 -to SW[3]
set_location_assignment PIN_AB27 -to SW[4]
set_location_assignment PIN_AC26 -to SW[5]
set_location_assignment PIN_AD26 -to SW[6]
set_location_assignment PIN_AB26 -to SW[7]
set_location_assignment PIN_AC25 -to SW[8]
set_location_assignment PIN_AB25 -to SW[9]
set_location_assignment PIN_AC24 -to SW[10]
set_location_assignment PIN_AB24 -to SW[11]
set_location_assignment PIN_AB23 -to SW[12]
set_location_assignment PIN_AA24 -to SW[13]
set_location_assignment PIN_AA23 -to SW[14]
set_location_assignment PIN_AA22 -to SW[15]
set_location_assignment PIN_Y24 -to SW[16]
set_location_assignment PIN_Y23 -to SW[17]
set_location_assignment PIN_G19 -to LEDR[0]
set_location_assignment PIN_F19 -to LEDR[1]
set_location_assignment PIN_E19 -to LEDR[2]
set_location_assignment PIN_F21 -to LEDR[3]
set_location_assignment PIN_F18 -to LEDR[4]
set_location_assignment PIN_E18 -to LEDR[5]
set_location_assignment PIN_J19 -to LEDR[6]
set_location_assignment PIN_H19 -to LEDR[7]
set_location_assignment PIN_J17 -to LEDR[8]
set_location_assignment PIN_G17 -to LEDR[9]
set_location_assignment PIN_J15 -to LEDR[10]
set_location_assignment PIN_H16 -to LEDR[11]
set_location_assignment PIN_J16 -to LEDR[12]
set_location_assignment PIN_H17 -to LEDR[13]
set_location_assignment PIN_F15 -to LEDR[14]
set_location_assignment PIN_G15 -to LEDR[15]
set_location_assignment PIN_G16 -to LEDR[16]
set_location_assignment PIN_H15 -to LEDR[17]
set_location_assignment PIN_E21 -to LEDG[0]
set_location_assignment PIN_E22 -to LEDG[1]
set_location_assignment PIN_E25 -to LEDG[2]
set_location_assignment PIN_E24 -to LEDG[3]
set_location_assignment PIN_H21 -to LEDG[4]
set_location_assignment PIN_G20 -to LEDG[5]
set_location_assignment PIN_G22 -to LEDG[6]
set_location_assignment PIN_G21 -to LEDG[7]
set_location_assignment PIN_F17 -to LEDG[8]
set_location_assignment PIN_G18 -to HEX0[0]
set_location_assignment PIN_F22 -to HEX0[1]
set_location_assignment PIN_E17 -to HEX0[2]
set_location_assignment PIN_L26 -to HEX0[3]
set_location_assignment PIN_L25 -to HEX0[4]
set_location_assignment PIN_J22 -to HEX0[5]
set_location_assignment PIN_H22 -to HEX0[6]
set_location_assignment PIN_M24 -to HEX1[0]
set_location_assignment PIN_Y22 -to HEX1[1]
set_location_assignment PIN_W21 -to HEX1[2]
set_location_assignment PIN_W22 -to HEX1[3]
set_location_assignment PIN_W25 -to HEX1[4]
set_location_assignment PIN_U23 -to HEX1[5]
set_location_assignment PIN_U24 -to HEX1[6]
set_location_assignment PIN_AA25 -to HEX2[0]
set_location_assignment PIN_AA26 -to HEX2[1]
set_location_assignment PIN_Y25 -to HEX2[2]
set_location_assignment PIN_W26 -to HEX2[3]
set_location_assignment PIN_Y26 -to HEX2[4]
set_location_assignment PIN_W27 -to HEX2[5]
set_location_assignment PIN_W28 -to HEX2[6]
set_location_assignment PIN_V21 -to HEX3[0]
set_location_assignment PIN_U21 -to HEX3[1]
set_location_assignment PIN_AB20 -to HEX3[2]
set_location_assignment PIN_AA21 -to HEX3[3]
set_location_assignment PIN_AD24 -to HEX3[4]
set_location_assignment PIN_AF23 -to HEX3[5]
set_location_assignment PIN_Y19 -to HEX3[6]
set_location_assignment PIN_AB19 -to HEX4[0]
set_location_assignment PIN_AA19 -to HEX4[1]
set_location_assignment PIN_AG21 -to HEX4[2]
set_location_assignment PIN_AH21 -to HEX4[3]
set_location_assignment PIN_AE19 -to HEX4[4]
set_location_assignment PIN_AF19 -to HEX4[5]
set_location_assignment PIN_AE18 -to HEX4[6]
set_location_assignment PIN_AD18 -to HEX5[0]
set_location_assignment PIN_AC18 -to HEX5[1]
set_location_assignment PIN_AB18 -to HEX5[2]
set_location_assignment PIN_AH19 -to HEX5[3]
set_location_assignment PIN_AG19 -to HEX5[4]
set_location_assignment PIN_AF18 -to HEX5[5]
set_location_assignment PIN_AH18 -to HEX5[6]
set_location_assignment PIN_AA17 -to HEX6[0]
set_location_assignment PIN_AB16 -to HEX6[1]
set_location_assignment PIN_AA16 -to HEX6[2]
set_location_assignment PIN_AB17 -to HEX6[3]
set_location_assignment PIN_AB15 -to HEX6[4]
set_location_assignment PIN_AA15 -to HEX6[5]
set_location_assignment PIN_AC17 -to HEX6[6]
set_location_assignment PIN_AD17 -to HEX7[0]
set_location_assignment PIN_AE17 -to HEX7[1]
set_location_assignment PIN_AG17 -to HEX7[2]
set_location_assignment PIN_AH17 -to HEX7[3]
set_location_assignment PIN_AF17 -to HEX7[4]
set_location_assignment PIN_AG18 -to HEX7[5]
set_location_assignment PIN_AA14 -to HEX7[6]
set_location_assignment PIN_L3 -to LCD_DATA[0]
set_location_assignment PIN_L1 -to LCD_DATA[1]
set_location_assignment PIN_L2 -to LCD_DATA[2]
set_location_assignment PIN_K7 -to LCD_DATA[3]
set_location_assignment PIN_K1 -to LCD_DATA[4]
set_location_assignment PIN_K2 -to LCD_DATA[5]
set_location_assignment PIN_M3 -to LCD_DATA[6]
set_location_assignment PIN_M5 -to LCD_DATA[7]
set_location_assignment PIN_L6 -to LCD_BLON
set_location_assignment PIN_M1 -to LCD_RW
set_location_assignment PIN_L4 -to LCD_EN
set_location_assignment PIN_M2 -to LCD_RS
set_location_assignment PIN_L5 -to LCD_ON
set_location_assignment PIN_G9 -to UART_TXD
set_location_assignment PIN_G12 -to UART_RXD
set_location_assignment PIN_G14 -to UART_CTS
set_location_assignment PIN_J13 -to UART_RTS
set_location_assignment PIN_G6 -to PS2_CLK
set_location_assignment PIN_H5 -to PS2_DAT
set_location_assignment PIN_G5 -to PS2_CLK2
set_location_assignment PIN_F5 -to PS2_DAT2
set_location_assignment PIN_AE13 -to SD_CLK
set_location_assignment PIN_AD14 -to SD_CMD
set_location_assignment PIN_AF14 -to SD_WP_N
set_location_assignment PIN_AE14 -to SD_DAT[0]
set_location_assignment PIN_AF13 -to SD_DAT[1]
set_location_assignment PIN_AB14 -to SD_DAT[2]
set_location_assignment PIN_AC14 -to SD_DAT[3]
set_location_assignment PIN_G13 -to VGA_HS
set_location_assignment PIN_C13 -to VGA_VS
set_location_assignment PIN_C10 -to VGA_SYNC_N
set_location_assignment PIN_A12 -to VGA_CLK
set_location_assignment PIN_F11 -to VGA_BLANK_N
set_location_assignment PIN_E12 -to VGA_R[0]
set_location_assignment PIN_E11 -to VGA_R[1]
set_location_assignment PIN_D10 -to VGA_R[2]
set_location_assignment PIN_F12 -to VGA_R[3]
set_location_assignment PIN_G10 -to VGA_R[4]
set_location_assignment PIN_J12 -to VGA_R[5]
set_location_assignment PIN_H8 -to VGA_R[6]
set_location_assignment PIN_H10 -to VGA_R[7]
set_location_assignment PIN_G8 -to VGA_G[0]
set_location_assignment PIN_G11 -to VGA_G[1]
set_location_assignment PIN_F8 -to VGA_G[2]
set_location_assignment PIN_H12 -to VGA_G[3]
set_location_assignment PIN_C8 -to VGA_G[4]
set_location_assignment PIN_B8 -to VGA_G[5]
set_location_assignment PIN_F10 -to VGA_G[6]
set_location_assignment PIN_C9 -to VGA_G[7]
set_location_assignment PIN_B10 -to VGA_B[0]
set_location_assignment PIN_A10 -to VGA_B[1]
set_location_assignment PIN_C11 -to VGA_B[2]
set_location_assignment PIN_B11 -to VGA_B[3]
set_location_assignment PIN_A11 -to VGA_B[4]
set_location_assignment PIN_C12 -to VGA_B[5]
set_location_assignment PIN_D11 -to VGA_B[6]
set_location_assignment PIN_D12 -to VGA_B[7]
set_location_assignment PIN_C2 -to AUD_ADCLRCK
set_location_assignment PIN_D2 -to AUD_ADCDAT
set_location_assignment PIN_E3 -to AUD_DACLRCK
set_location_assignment PIN_D1 -to AUD_DACDAT
set_location_assignment PIN_E1 -to AUD_XCK
set_location_assignment PIN_F2 -to AUD_BCLK
set_location_assignment PIN_D14 -to EEP_I2C_SCLK
set_location_assignment PIN_E14 -to EEP_I2C_SDAT
set_location_assignment PIN_B7 -to I2C_SCLK
set_location_assignment PIN_A8 -to I2C_SDAT
set_location_assignment PIN_A14 -to ENETCLK_25
set_location_assignment PIN_C14 -to ENET0_LINK100
set_location_assignment PIN_A17 -to ENET0_GTX_CLK
set_location_assignment PIN_C19 -to ENET0_RST_N
set_location_assignment PIN_C20 -to ENET0_MDC
set_location_assignment PIN_B21 -to ENET0_MDIO
set_location_assignment PIN_A21 -to ENET0_INT_N
set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
set_location_assignment PIN_B17 -to ENET0_TX_CLK
set_location_assignment PIN_A18 -to ENET0_TX_EN
set_location_assignment PIN_B18 -to ENET0_TX_ER
set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
set_location_assignment PIN_A15 -to ENET0_RX_CLK
set_location_assignment PIN_C17 -to ENET0_RX_DV
set_location_assignment PIN_D18 -to ENET0_RX_ER
set_location_assignment PIN_D15 -to ENET0_RX_CRS
set_location_assignment PIN_E15 -to ENET0_RX_COL
set_location_assignment PIN_D13 -to ENET1_LINK100
set_location_assignment PIN_C23 -to ENET1_GTX_CLK
set_location_assignment PIN_D22 -to ENET1_RST_N
set_location_assignment PIN_D23 -to ENET1_MDC
set_location_assignment PIN_D25 -to ENET1_MDIO
set_location_assignment PIN_D24 -to ENET1_INT_N
set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
set_location_assignment PIN_C22 -to ENET1_TX_CLK
set_location_assignment PIN_B25 -to ENET1_TX_EN
set_location_assignment PIN_A25 -to ENET1_TX_ER
set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
set_location_assignment PIN_B15 -to ENET1_RX_CLK
set_location_assignment PIN_A22 -to ENET1_RX_DV
set_location_assignment PIN_C24 -to ENET1_RX_ER
set_location_assignment PIN_D20 -to ENET1_RX_CRS
set_location_assignment PIN_B22 -to ENET1_RX_COL
set_location_assignment PIN_E5 -to TD_HS
set_location_assignment PIN_E4 -to TD_VS
set_location_assignment PIN_B14 -to TD_CLK27
set_location_assignment PIN_G7 -to TD_RESET_N
set_location_assignment PIN_E8 -to TD_DATA[0]
set_location_assignment PIN_A7 -to TD_DATA[1]
set_location_assignment PIN_D8 -to TD_DATA[2]
set_location_assignment PIN_C7 -to TD_DATA[3]
set_location_assignment PIN_D7 -to TD_DATA[4]
set_location_assignment PIN_D6 -to TD_DATA[5]
set_location_assignment PIN_E7 -to TD_DATA[6]
set_location_assignment PIN_F7 -to TD_DATA[7]
set_location_assignment PIN_J6 -to OTG_DATA[0]
set_location_assignment PIN_K4 -to OTG_DATA[1]
set_location_assignment PIN_J5 -to OTG_DATA[2]
set_location_assignment PIN_K3 -to OTG_DATA[3]
set_location_assignment PIN_J4 -to OTG_DATA[4]
set_location_assignment PIN_J3 -to OTG_DATA[5]
set_location_assignment PIN_J7 -to OTG_DATA[6]
set_location_assignment PIN_H6 -to OTG_DATA[7]
set_location_assignment PIN_H3 -to OTG_DATA[8]
set_location_assignment PIN_H4 -to OTG_DATA[9]
set_location_assignment PIN_G1 -to OTG_DATA[10]
set_location_assignment PIN_G2 -to OTG_DATA[11]
set_location_assignment PIN_G3 -to OTG_DATA[12]
set_location_assignment PIN_F1 -to OTG_DATA[13]
set_location_assignment PIN_F3 -to OTG_DATA[14]
set_location_assignment PIN_G4 -to OTG_DATA[15]
set_location_assignment PIN_H7 -to OTG_ADDR[0]
set_location_assignment PIN_C3 -to OTG_ADDR[1]
set_location_assignment PIN_J1 -to OTG_DREQ[0]
set_location_assignment PIN_A3 -to OTG_CS_N
set_location_assignment PIN_A4 -to OTG_WR_N
set_location_assignment PIN_B3 -to OTG_RD_N
set_location_assignment PIN_D5 -to OTG_INT
set_location_assignment PIN_C5 -to OTG_RST_N
set_location_assignment PIN_Y15 -to IRDA_RXD
set_location_assignment PIN_U7 -to DRAM_BA[0]
set_location_assignment PIN_R4 -to DRAM_BA[1]
set_location_assignment PIN_U2 -to DRAM_DQM[0]
set_location_assignment PIN_W4 -to DRAM_DQM[1]
set_location_assignment PIN_K8 -to DRAM_DQM[2]
set_location_assignment PIN_N8 -to DRAM_DQM[3]
set_location_assignment PIN_U6 -to DRAM_RAS_N
set_location_assignment PIN_V7 -to DRAM_CAS_N
set_location_assignment PIN_AA6 -to DRAM_CKE
set_location_assignment PIN_AE5 -to DRAM_CLK
set_location_assignment PIN_V6 -to DRAM_WE_N
set_location_assignment PIN_T4 -to DRAM_CS_N
set_location_assignment PIN_W3 -to DRAM_DQ[0]
set_location_assignment PIN_W2 -to DRAM_DQ[1]
set_location_assignment PIN_V4 -to DRAM_DQ[2]
set_location_assignment PIN_W1 -to DRAM_DQ[3]
set_location_assignment PIN_V3 -to DRAM_DQ[4]
set_location_assignment PIN_V2 -to DRAM_DQ[5]
set_location_assignment PIN_V1 -to DRAM_DQ[6]
set_location_assignment PIN_U3 -to DRAM_DQ[7]
set_location_assignment PIN_Y3 -to DRAM_DQ[8]
set_location_assignment PIN_Y4 -to DRAM_DQ[9]
set_location_assignment PIN_AB1 -to DRAM_DQ[10]
set_location_assignment PIN_AA3 -to DRAM_DQ[11]
set_location_assignment PIN_AB2 -to DRAM_DQ[12]
set_location_assignment PIN_AC1 -to DRAM_DQ[13]
set_location_assignment PIN_AB3 -to DRAM_DQ[14]
set_location_assignment PIN_AC2 -to DRAM_DQ[15]
set_location_assignment PIN_M8 -to DRAM_DQ[16]
set_location_assignment PIN_L8 -to DRAM_DQ[17]
set_location_assignment PIN_P2 -to DRAM_DQ[18]
set_location_assignment PIN_N3 -to DRAM_DQ[19]
set_location_assignment PIN_N4 -to DRAM_DQ[20]
set_location_assignment PIN_M4 -to DRAM_DQ[21]
set_location_assignment PIN_M7 -to DRAM_DQ[22]
set_location_assignment PIN_L7 -to DRAM_DQ[23]
set_location_assignment PIN_U5 -to DRAM_DQ[24]
set_location_assignment PIN_R7 -to DRAM_DQ[25]
set_location_assignment PIN_R1 -to DRAM_DQ[26]
set_location_assignment PIN_R2 -to DRAM_DQ[27]
set_location_assignment PIN_R3 -to DRAM_DQ[28]
set_location_assignment PIN_T3 -to DRAM_DQ[29]
set_location_assignment PIN_U4 -to DRAM_DQ[30]
set_location_assignment PIN_U1 -to DRAM_DQ[31]
set_location_assignment PIN_R6 -to DRAM_ADDR[0]
set_location_assignment PIN_V8 -to DRAM_ADDR[1]
set_location_assignment PIN_U8 -to DRAM_ADDR[2]
set_location_assignment PIN_P1 -to DRAM_ADDR[3]
set_location_assignment PIN_V5 -to DRAM_ADDR[4]
set_location_assignment PIN_W8 -to DRAM_ADDR[5]
set_location_assignment PIN_W7 -to DRAM_ADDR[6]
set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
set_location_assignment PIN_R5 -to DRAM_ADDR[10]
set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
set_location_assignment PIN_T7 -to SRAM_ADDR[9]
set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
set_location_assignment PIN_T8 -to SRAM_ADDR[19]
set_location_assignment PIN_AH3 -to SRAM_DQ[0]
set_location_assignment PIN_AF4 -to SRAM_DQ[1]
set_location_assignment PIN_AG4 -to SRAM_DQ[2]
set_location_assignment PIN_AH4 -to SRAM_DQ[3]
set_location_assignment PIN_AF6 -to SRAM_DQ[4]
set_location_assignment PIN_AG6 -to SRAM_DQ[5]
set_location_assignment PIN_AH6 -to SRAM_DQ[6]
set_location_assignment PIN_AF7 -to SRAM_DQ[7]
set_location_assignment PIN_AD1 -to SRAM_DQ[8]
set_location_assignment PIN_AD2 -to SRAM_DQ[9]
set_location_assignment PIN_AE2 -to SRAM_DQ[10]
set_location_assignment PIN_AE1 -to SRAM_DQ[11]
set_location_assignment PIN_AE3 -to SRAM_DQ[12]
set_location_assignment PIN_AE4 -to SRAM_DQ[13]
set_location_assignment PIN_AF3 -to SRAM_DQ[14]
set_location_assignment PIN_AG3 -to SRAM_DQ[15]
set_location_assignment PIN_AC4 -to SRAM_UB_N
set_location_assignment PIN_AD4 -to SRAM_LB_N
set_location_assignment PIN_AF8 -to SRAM_CE_N
set_location_assignment PIN_AD5 -to SRAM_OE_N
set_location_assignment PIN_AE8 -to SRAM_WE_N
set_location_assignment PIN_AG12 -to FL_ADDR[0]
set_location_assignment PIN_AH7 -to FL_ADDR[1]
set_location_assignment PIN_Y13 -to FL_ADDR[2]
set_location_assignment PIN_Y14 -to FL_ADDR[3]
set_location_assignment PIN_Y12 -to FL_ADDR[4]
set_location_assignment PIN_AA13 -to FL_ADDR[5]
set_location_assignment PIN_AA12 -to FL_ADDR[6]
set_location_assignment PIN_AB13 -to FL_ADDR[7]
set_location_assignment PIN_AB12 -to FL_ADDR[8]
set_location_assignment PIN_AB10 -to FL_ADDR[9]
set_location_assignment PIN_AE9 -to FL_ADDR[10]
set_location_assignment PIN_AF9 -to FL_ADDR[11]
set_location_assignment PIN_AA10 -to FL_ADDR[12]
set_location_assignment PIN_AD8 -to FL_ADDR[13]
set_location_assignment PIN_AC8 -to FL_ADDR[14]
set_location_assignment PIN_Y10 -to FL_ADDR[15]
set_location_assignment PIN_AA8 -to FL_ADDR[16]
set_location_assignment PIN_AH12 -to FL_ADDR[17]
set_location_assignment PIN_AC12 -to FL_ADDR[18]
set_location_assignment PIN_AD12 -to FL_ADDR[19]
set_location_assignment PIN_AE10 -to FL_ADDR[20]
set_location_assignment PIN_AD10 -to FL_ADDR[21]
set_location_assignment PIN_AD11 -to FL_ADDR[22]
set_location_assignment PIN_AH8 -to FL_DQ[0]
set_location_assignment PIN_AF10 -to FL_DQ[1]
set_location_assignment PIN_AG10 -to FL_DQ[2]
set_location_assignment PIN_AH10 -to FL_DQ[3]
set_location_assignment PIN_AF11 -to FL_DQ[4]
set_location_assignment PIN_AG11 -to FL_DQ[5]
set_location_assignment PIN_AH11 -to FL_DQ[6]
set_location_assignment PIN_AF12 -to FL_DQ[7]
set_location_assignment PIN_AG7 -to FL_CE_N
set_location_assignment PIN_AG8 -to FL_OE_N
set_location_assignment PIN_AE11 -to FL_RST_N
set_location_assignment PIN_Y1 -to FL_RY
set_location_assignment PIN_AC10 -to FL_WE_N
set_location_assignment PIN_AE12 -to FL_WP_N
set_location_assignment PIN_AB22 -to GPIO[0]
set_location_assignment PIN_AC15 -to GPIO[1]
set_location_assignment PIN_AB21 -to GPIO[2]
set_location_assignment PIN_Y17 -to GPIO[3]
set_location_assignment PIN_AC21 -to GPIO[4]
set_location_assignment PIN_Y16 -to GPIO[5]
set_location_assignment PIN_AD21 -to GPIO[6]
set_location_assignment PIN_AE16 -to GPIO[7]
set_location_assignment PIN_AD15 -to GPIO[8]
set_location_assignment PIN_AE15 -to GPIO[9]
set_location_assignment PIN_AC19 -to GPIO[10]
set_location_assignment PIN_AF16 -to GPIO[11]
set_location_assignment PIN_AD19 -to GPIO[12]
set_location_assignment PIN_AF15 -to GPIO[13]
set_location_assignment PIN_AF24 -to GPIO[14]
set_location_assignment PIN_AE21 -to GPIO[15]
set_location_assignment PIN_AF25 -to GPIO[16]
set_location_assignment PIN_AC22 -to GPIO[17]
set_location_assignment PIN_AE22 -to GPIO[18]
set_location_assignment PIN_AF21 -to GPIO[19]
set_location_assignment PIN_AF22 -to GPIO[20]
set_location_assignment PIN_AD22 -to GPIO[21]
set_location_assignment PIN_AG25 -to GPIO[22]
set_location_assignment PIN_AD25 -to GPIO[23]
set_location_assignment PIN_AH25 -to GPIO[24]
set_location_assignment PIN_AE25 -to GPIO[25]
set_location_assignment PIN_AG22 -to GPIO[26]
set_location_assignment PIN_AE24 -to GPIO[27]
set_location_assignment PIN_AH22 -to GPIO[28]
set_location_assignment PIN_AF26 -to GPIO[29]
set_location_assignment PIN_AE20 -to GPIO[30]
set_location_assignment PIN_AG23 -to GPIO[31]
set_location_assignment PIN_AF20 -to GPIO[32]
set_location_assignment PIN_AH26 -to GPIO[33]
set_location_assignment PIN_AH23 -to GPIO[34]
set_location_assignment PIN_AG26 -to GPIO[35]
set_location_assignment PIN_AH15 -to HSMC_CLKIN0
set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
set_location_assignment PIN_AE26 -to HSMC_D[0]
set_location_assignment PIN_AE28 -to HSMC_D[1]
set_location_assignment PIN_AE27 -to HSMC_D[2]
set_location_assignment PIN_AF27 -to HSMC_D[3]
set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
set_location_assignment PIN_J10 -to EX_IO[0]
set_location_assignment PIN_J14 -to EX_IO[1]
set_location_assignment PIN_H13 -to EX_IO[2]
set_location_assignment PIN_H14 -to EX_IO[3]
set_location_assignment PIN_F14 -to EX_IO[4]
set_location_assignment PIN_E10 -to EX_IO[5]
set_location_assignment PIN_D9 -to EX_IO[6]
set_global_assignment -name VHDL_FILE CounterUpDown4.vhd
set_global_assignment -name VHDL_FILE CounterDown4.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE CounterDown4.vwf
set_global_assignment -name BDF_FILE CounterDemo.bdf
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE Bin7SegDecoder.vhd
set_global_assignment -name VHDL_FILE FreqDivider.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

588
1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qsf.bak Normal file
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@ -0,0 +1,588 @@
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#
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# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
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# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
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# https://fpgasoftware.intel.com/eula.
#
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#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 16:44:06 March 16, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# CounterDemo_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY FreqDivider
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:44:06 MARCH 16, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_location_assignment PIN_Y2 -to CLOCK_50
set_location_assignment PIN_AG14 -to CLOCK2_50
set_location_assignment PIN_AG15 -to CLOCK3_50
set_location_assignment PIN_AH14 -to SMA_CLKIN
set_location_assignment PIN_AE23 -to SMA_CLKOUT
set_location_assignment PIN_M23 -to KEY[0]
set_location_assignment PIN_M21 -to KEY[1]
set_location_assignment PIN_N21 -to KEY[2]
set_location_assignment PIN_R24 -to KEY[3]
set_location_assignment PIN_AB28 -to SW[0]
set_location_assignment PIN_AC28 -to SW[1]
set_location_assignment PIN_AC27 -to SW[2]
set_location_assignment PIN_AD27 -to SW[3]
set_location_assignment PIN_AB27 -to SW[4]
set_location_assignment PIN_AC26 -to SW[5]
set_location_assignment PIN_AD26 -to SW[6]
set_location_assignment PIN_AB26 -to SW[7]
set_location_assignment PIN_AC25 -to SW[8]
set_location_assignment PIN_AB25 -to SW[9]
set_location_assignment PIN_AC24 -to SW[10]
set_location_assignment PIN_AB24 -to SW[11]
set_location_assignment PIN_AB23 -to SW[12]
set_location_assignment PIN_AA24 -to SW[13]
set_location_assignment PIN_AA23 -to SW[14]
set_location_assignment PIN_AA22 -to SW[15]
set_location_assignment PIN_Y24 -to SW[16]
set_location_assignment PIN_Y23 -to SW[17]
set_location_assignment PIN_G19 -to LEDR[0]
set_location_assignment PIN_F19 -to LEDR[1]
set_location_assignment PIN_E19 -to LEDR[2]
set_location_assignment PIN_F21 -to LEDR[3]
set_location_assignment PIN_F18 -to LEDR[4]
set_location_assignment PIN_E18 -to LEDR[5]
set_location_assignment PIN_J19 -to LEDR[6]
set_location_assignment PIN_H19 -to LEDR[7]
set_location_assignment PIN_J17 -to LEDR[8]
set_location_assignment PIN_G17 -to LEDR[9]
set_location_assignment PIN_J15 -to LEDR[10]
set_location_assignment PIN_H16 -to LEDR[11]
set_location_assignment PIN_J16 -to LEDR[12]
set_location_assignment PIN_H17 -to LEDR[13]
set_location_assignment PIN_F15 -to LEDR[14]
set_location_assignment PIN_G15 -to LEDR[15]
set_location_assignment PIN_G16 -to LEDR[16]
set_location_assignment PIN_H15 -to LEDR[17]
set_location_assignment PIN_E21 -to LEDG[0]
set_location_assignment PIN_E22 -to LEDG[1]
set_location_assignment PIN_E25 -to LEDG[2]
set_location_assignment PIN_E24 -to LEDG[3]
set_location_assignment PIN_H21 -to LEDG[4]
set_location_assignment PIN_G20 -to LEDG[5]
set_location_assignment PIN_G22 -to LEDG[6]
set_location_assignment PIN_G21 -to LEDG[7]
set_location_assignment PIN_F17 -to LEDG[8]
set_location_assignment PIN_G18 -to HEX0[0]
set_location_assignment PIN_F22 -to HEX0[1]
set_location_assignment PIN_E17 -to HEX0[2]
set_location_assignment PIN_L26 -to HEX0[3]
set_location_assignment PIN_L25 -to HEX0[4]
set_location_assignment PIN_J22 -to HEX0[5]
set_location_assignment PIN_H22 -to HEX0[6]
set_location_assignment PIN_M24 -to HEX1[0]
set_location_assignment PIN_Y22 -to HEX1[1]
set_location_assignment PIN_W21 -to HEX1[2]
set_location_assignment PIN_W22 -to HEX1[3]
set_location_assignment PIN_W25 -to HEX1[4]
set_location_assignment PIN_U23 -to HEX1[5]
set_location_assignment PIN_U24 -to HEX1[6]
set_location_assignment PIN_AA25 -to HEX2[0]
set_location_assignment PIN_AA26 -to HEX2[1]
set_location_assignment PIN_Y25 -to HEX2[2]
set_location_assignment PIN_W26 -to HEX2[3]
set_location_assignment PIN_Y26 -to HEX2[4]
set_location_assignment PIN_W27 -to HEX2[5]
set_location_assignment PIN_W28 -to HEX2[6]
set_location_assignment PIN_V21 -to HEX3[0]
set_location_assignment PIN_U21 -to HEX3[1]
set_location_assignment PIN_AB20 -to HEX3[2]
set_location_assignment PIN_AA21 -to HEX3[3]
set_location_assignment PIN_AD24 -to HEX3[4]
set_location_assignment PIN_AF23 -to HEX3[5]
set_location_assignment PIN_Y19 -to HEX3[6]
set_location_assignment PIN_AB19 -to HEX4[0]
set_location_assignment PIN_AA19 -to HEX4[1]
set_location_assignment PIN_AG21 -to HEX4[2]
set_location_assignment PIN_AH21 -to HEX4[3]
set_location_assignment PIN_AE19 -to HEX4[4]
set_location_assignment PIN_AF19 -to HEX4[5]
set_location_assignment PIN_AE18 -to HEX4[6]
set_location_assignment PIN_AD18 -to HEX5[0]
set_location_assignment PIN_AC18 -to HEX5[1]
set_location_assignment PIN_AB18 -to HEX5[2]
set_location_assignment PIN_AH19 -to HEX5[3]
set_location_assignment PIN_AG19 -to HEX5[4]
set_location_assignment PIN_AF18 -to HEX5[5]
set_location_assignment PIN_AH18 -to HEX5[6]
set_location_assignment PIN_AA17 -to HEX6[0]
set_location_assignment PIN_AB16 -to HEX6[1]
set_location_assignment PIN_AA16 -to HEX6[2]
set_location_assignment PIN_AB17 -to HEX6[3]
set_location_assignment PIN_AB15 -to HEX6[4]
set_location_assignment PIN_AA15 -to HEX6[5]
set_location_assignment PIN_AC17 -to HEX6[6]
set_location_assignment PIN_AD17 -to HEX7[0]
set_location_assignment PIN_AE17 -to HEX7[1]
set_location_assignment PIN_AG17 -to HEX7[2]
set_location_assignment PIN_AH17 -to HEX7[3]
set_location_assignment PIN_AF17 -to HEX7[4]
set_location_assignment PIN_AG18 -to HEX7[5]
set_location_assignment PIN_AA14 -to HEX7[6]
set_location_assignment PIN_L3 -to LCD_DATA[0]
set_location_assignment PIN_L1 -to LCD_DATA[1]
set_location_assignment PIN_L2 -to LCD_DATA[2]
set_location_assignment PIN_K7 -to LCD_DATA[3]
set_location_assignment PIN_K1 -to LCD_DATA[4]
set_location_assignment PIN_K2 -to LCD_DATA[5]
set_location_assignment PIN_M3 -to LCD_DATA[6]
set_location_assignment PIN_M5 -to LCD_DATA[7]
set_location_assignment PIN_L6 -to LCD_BLON
set_location_assignment PIN_M1 -to LCD_RW
set_location_assignment PIN_L4 -to LCD_EN
set_location_assignment PIN_M2 -to LCD_RS
set_location_assignment PIN_L5 -to LCD_ON
set_location_assignment PIN_G9 -to UART_TXD
set_location_assignment PIN_G12 -to UART_RXD
set_location_assignment PIN_G14 -to UART_CTS
set_location_assignment PIN_J13 -to UART_RTS
set_location_assignment PIN_G6 -to PS2_CLK
set_location_assignment PIN_H5 -to PS2_DAT
set_location_assignment PIN_G5 -to PS2_CLK2
set_location_assignment PIN_F5 -to PS2_DAT2
set_location_assignment PIN_AE13 -to SD_CLK
set_location_assignment PIN_AD14 -to SD_CMD
set_location_assignment PIN_AF14 -to SD_WP_N
set_location_assignment PIN_AE14 -to SD_DAT[0]
set_location_assignment PIN_AF13 -to SD_DAT[1]
set_location_assignment PIN_AB14 -to SD_DAT[2]
set_location_assignment PIN_AC14 -to SD_DAT[3]
set_location_assignment PIN_G13 -to VGA_HS
set_location_assignment PIN_C13 -to VGA_VS
set_location_assignment PIN_C10 -to VGA_SYNC_N
set_location_assignment PIN_A12 -to VGA_CLK
set_location_assignment PIN_F11 -to VGA_BLANK_N
set_location_assignment PIN_E12 -to VGA_R[0]
set_location_assignment PIN_E11 -to VGA_R[1]
set_location_assignment PIN_D10 -to VGA_R[2]
set_location_assignment PIN_F12 -to VGA_R[3]
set_location_assignment PIN_G10 -to VGA_R[4]
set_location_assignment PIN_J12 -to VGA_R[5]
set_location_assignment PIN_H8 -to VGA_R[6]
set_location_assignment PIN_H10 -to VGA_R[7]
set_location_assignment PIN_G8 -to VGA_G[0]
set_location_assignment PIN_G11 -to VGA_G[1]
set_location_assignment PIN_F8 -to VGA_G[2]
set_location_assignment PIN_H12 -to VGA_G[3]
set_location_assignment PIN_C8 -to VGA_G[4]
set_location_assignment PIN_B8 -to VGA_G[5]
set_location_assignment PIN_F10 -to VGA_G[6]
set_location_assignment PIN_C9 -to VGA_G[7]
set_location_assignment PIN_B10 -to VGA_B[0]
set_location_assignment PIN_A10 -to VGA_B[1]
set_location_assignment PIN_C11 -to VGA_B[2]
set_location_assignment PIN_B11 -to VGA_B[3]
set_location_assignment PIN_A11 -to VGA_B[4]
set_location_assignment PIN_C12 -to VGA_B[5]
set_location_assignment PIN_D11 -to VGA_B[6]
set_location_assignment PIN_D12 -to VGA_B[7]
set_location_assignment PIN_C2 -to AUD_ADCLRCK
set_location_assignment PIN_D2 -to AUD_ADCDAT
set_location_assignment PIN_E3 -to AUD_DACLRCK
set_location_assignment PIN_D1 -to AUD_DACDAT
set_location_assignment PIN_E1 -to AUD_XCK
set_location_assignment PIN_F2 -to AUD_BCLK
set_location_assignment PIN_D14 -to EEP_I2C_SCLK
set_location_assignment PIN_E14 -to EEP_I2C_SDAT
set_location_assignment PIN_B7 -to I2C_SCLK
set_location_assignment PIN_A8 -to I2C_SDAT
set_location_assignment PIN_A14 -to ENETCLK_25
set_location_assignment PIN_C14 -to ENET0_LINK100
set_location_assignment PIN_A17 -to ENET0_GTX_CLK
set_location_assignment PIN_C19 -to ENET0_RST_N
set_location_assignment PIN_C20 -to ENET0_MDC
set_location_assignment PIN_B21 -to ENET0_MDIO
set_location_assignment PIN_A21 -to ENET0_INT_N
set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
set_location_assignment PIN_B17 -to ENET0_TX_CLK
set_location_assignment PIN_A18 -to ENET0_TX_EN
set_location_assignment PIN_B18 -to ENET0_TX_ER
set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
set_location_assignment PIN_A15 -to ENET0_RX_CLK
set_location_assignment PIN_C17 -to ENET0_RX_DV
set_location_assignment PIN_D18 -to ENET0_RX_ER
set_location_assignment PIN_D15 -to ENET0_RX_CRS
set_location_assignment PIN_E15 -to ENET0_RX_COL
set_location_assignment PIN_D13 -to ENET1_LINK100
set_location_assignment PIN_C23 -to ENET1_GTX_CLK
set_location_assignment PIN_D22 -to ENET1_RST_N
set_location_assignment PIN_D23 -to ENET1_MDC
set_location_assignment PIN_D25 -to ENET1_MDIO
set_location_assignment PIN_D24 -to ENET1_INT_N
set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
set_location_assignment PIN_C22 -to ENET1_TX_CLK
set_location_assignment PIN_B25 -to ENET1_TX_EN
set_location_assignment PIN_A25 -to ENET1_TX_ER
set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
set_location_assignment PIN_B15 -to ENET1_RX_CLK
set_location_assignment PIN_A22 -to ENET1_RX_DV
set_location_assignment PIN_C24 -to ENET1_RX_ER
set_location_assignment PIN_D20 -to ENET1_RX_CRS
set_location_assignment PIN_B22 -to ENET1_RX_COL
set_location_assignment PIN_E5 -to TD_HS
set_location_assignment PIN_E4 -to TD_VS
set_location_assignment PIN_B14 -to TD_CLK27
set_location_assignment PIN_G7 -to TD_RESET_N
set_location_assignment PIN_E8 -to TD_DATA[0]
set_location_assignment PIN_A7 -to TD_DATA[1]
set_location_assignment PIN_D8 -to TD_DATA[2]
set_location_assignment PIN_C7 -to TD_DATA[3]
set_location_assignment PIN_D7 -to TD_DATA[4]
set_location_assignment PIN_D6 -to TD_DATA[5]
set_location_assignment PIN_E7 -to TD_DATA[6]
set_location_assignment PIN_F7 -to TD_DATA[7]
set_location_assignment PIN_J6 -to OTG_DATA[0]
set_location_assignment PIN_K4 -to OTG_DATA[1]
set_location_assignment PIN_J5 -to OTG_DATA[2]
set_location_assignment PIN_K3 -to OTG_DATA[3]
set_location_assignment PIN_J4 -to OTG_DATA[4]
set_location_assignment PIN_J3 -to OTG_DATA[5]
set_location_assignment PIN_J7 -to OTG_DATA[6]
set_location_assignment PIN_H6 -to OTG_DATA[7]
set_location_assignment PIN_H3 -to OTG_DATA[8]
set_location_assignment PIN_H4 -to OTG_DATA[9]
set_location_assignment PIN_G1 -to OTG_DATA[10]
set_location_assignment PIN_G2 -to OTG_DATA[11]
set_location_assignment PIN_G3 -to OTG_DATA[12]
set_location_assignment PIN_F1 -to OTG_DATA[13]
set_location_assignment PIN_F3 -to OTG_DATA[14]
set_location_assignment PIN_G4 -to OTG_DATA[15]
set_location_assignment PIN_H7 -to OTG_ADDR[0]
set_location_assignment PIN_C3 -to OTG_ADDR[1]
set_location_assignment PIN_J1 -to OTG_DREQ[0]
set_location_assignment PIN_A3 -to OTG_CS_N
set_location_assignment PIN_A4 -to OTG_WR_N
set_location_assignment PIN_B3 -to OTG_RD_N
set_location_assignment PIN_D5 -to OTG_INT
set_location_assignment PIN_C5 -to OTG_RST_N
set_location_assignment PIN_Y15 -to IRDA_RXD
set_location_assignment PIN_U7 -to DRAM_BA[0]
set_location_assignment PIN_R4 -to DRAM_BA[1]
set_location_assignment PIN_U2 -to DRAM_DQM[0]
set_location_assignment PIN_W4 -to DRAM_DQM[1]
set_location_assignment PIN_K8 -to DRAM_DQM[2]
set_location_assignment PIN_N8 -to DRAM_DQM[3]
set_location_assignment PIN_U6 -to DRAM_RAS_N
set_location_assignment PIN_V7 -to DRAM_CAS_N
set_location_assignment PIN_AA6 -to DRAM_CKE
set_location_assignment PIN_AE5 -to DRAM_CLK
set_location_assignment PIN_V6 -to DRAM_WE_N
set_location_assignment PIN_T4 -to DRAM_CS_N
set_location_assignment PIN_W3 -to DRAM_DQ[0]
set_location_assignment PIN_W2 -to DRAM_DQ[1]
set_location_assignment PIN_V4 -to DRAM_DQ[2]
set_location_assignment PIN_W1 -to DRAM_DQ[3]
set_location_assignment PIN_V3 -to DRAM_DQ[4]
set_location_assignment PIN_V2 -to DRAM_DQ[5]
set_location_assignment PIN_V1 -to DRAM_DQ[6]
set_location_assignment PIN_U3 -to DRAM_DQ[7]
set_location_assignment PIN_Y3 -to DRAM_DQ[8]
set_location_assignment PIN_Y4 -to DRAM_DQ[9]
set_location_assignment PIN_AB1 -to DRAM_DQ[10]
set_location_assignment PIN_AA3 -to DRAM_DQ[11]
set_location_assignment PIN_AB2 -to DRAM_DQ[12]
set_location_assignment PIN_AC1 -to DRAM_DQ[13]
set_location_assignment PIN_AB3 -to DRAM_DQ[14]
set_location_assignment PIN_AC2 -to DRAM_DQ[15]
set_location_assignment PIN_M8 -to DRAM_DQ[16]
set_location_assignment PIN_L8 -to DRAM_DQ[17]
set_location_assignment PIN_P2 -to DRAM_DQ[18]
set_location_assignment PIN_N3 -to DRAM_DQ[19]
set_location_assignment PIN_N4 -to DRAM_DQ[20]
set_location_assignment PIN_M4 -to DRAM_DQ[21]
set_location_assignment PIN_M7 -to DRAM_DQ[22]
set_location_assignment PIN_L7 -to DRAM_DQ[23]
set_location_assignment PIN_U5 -to DRAM_DQ[24]
set_location_assignment PIN_R7 -to DRAM_DQ[25]
set_location_assignment PIN_R1 -to DRAM_DQ[26]
set_location_assignment PIN_R2 -to DRAM_DQ[27]
set_location_assignment PIN_R3 -to DRAM_DQ[28]
set_location_assignment PIN_T3 -to DRAM_DQ[29]
set_location_assignment PIN_U4 -to DRAM_DQ[30]
set_location_assignment PIN_U1 -to DRAM_DQ[31]
set_location_assignment PIN_R6 -to DRAM_ADDR[0]
set_location_assignment PIN_V8 -to DRAM_ADDR[1]
set_location_assignment PIN_U8 -to DRAM_ADDR[2]
set_location_assignment PIN_P1 -to DRAM_ADDR[3]
set_location_assignment PIN_V5 -to DRAM_ADDR[4]
set_location_assignment PIN_W8 -to DRAM_ADDR[5]
set_location_assignment PIN_W7 -to DRAM_ADDR[6]
set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
set_location_assignment PIN_R5 -to DRAM_ADDR[10]
set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
set_location_assignment PIN_T7 -to SRAM_ADDR[9]
set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
set_location_assignment PIN_T8 -to SRAM_ADDR[19]
set_location_assignment PIN_AH3 -to SRAM_DQ[0]
set_location_assignment PIN_AF4 -to SRAM_DQ[1]
set_location_assignment PIN_AG4 -to SRAM_DQ[2]
set_location_assignment PIN_AH4 -to SRAM_DQ[3]
set_location_assignment PIN_AF6 -to SRAM_DQ[4]
set_location_assignment PIN_AG6 -to SRAM_DQ[5]
set_location_assignment PIN_AH6 -to SRAM_DQ[6]
set_location_assignment PIN_AF7 -to SRAM_DQ[7]
set_location_assignment PIN_AD1 -to SRAM_DQ[8]
set_location_assignment PIN_AD2 -to SRAM_DQ[9]
set_location_assignment PIN_AE2 -to SRAM_DQ[10]
set_location_assignment PIN_AE1 -to SRAM_DQ[11]
set_location_assignment PIN_AE3 -to SRAM_DQ[12]
set_location_assignment PIN_AE4 -to SRAM_DQ[13]
set_location_assignment PIN_AF3 -to SRAM_DQ[14]
set_location_assignment PIN_AG3 -to SRAM_DQ[15]
set_location_assignment PIN_AC4 -to SRAM_UB_N
set_location_assignment PIN_AD4 -to SRAM_LB_N
set_location_assignment PIN_AF8 -to SRAM_CE_N
set_location_assignment PIN_AD5 -to SRAM_OE_N
set_location_assignment PIN_AE8 -to SRAM_WE_N
set_location_assignment PIN_AG12 -to FL_ADDR[0]
set_location_assignment PIN_AH7 -to FL_ADDR[1]
set_location_assignment PIN_Y13 -to FL_ADDR[2]
set_location_assignment PIN_Y14 -to FL_ADDR[3]
set_location_assignment PIN_Y12 -to FL_ADDR[4]
set_location_assignment PIN_AA13 -to FL_ADDR[5]
set_location_assignment PIN_AA12 -to FL_ADDR[6]
set_location_assignment PIN_AB13 -to FL_ADDR[7]
set_location_assignment PIN_AB12 -to FL_ADDR[8]
set_location_assignment PIN_AB10 -to FL_ADDR[9]
set_location_assignment PIN_AE9 -to FL_ADDR[10]
set_location_assignment PIN_AF9 -to FL_ADDR[11]
set_location_assignment PIN_AA10 -to FL_ADDR[12]
set_location_assignment PIN_AD8 -to FL_ADDR[13]
set_location_assignment PIN_AC8 -to FL_ADDR[14]
set_location_assignment PIN_Y10 -to FL_ADDR[15]
set_location_assignment PIN_AA8 -to FL_ADDR[16]
set_location_assignment PIN_AH12 -to FL_ADDR[17]
set_location_assignment PIN_AC12 -to FL_ADDR[18]
set_location_assignment PIN_AD12 -to FL_ADDR[19]
set_location_assignment PIN_AE10 -to FL_ADDR[20]
set_location_assignment PIN_AD10 -to FL_ADDR[21]
set_location_assignment PIN_AD11 -to FL_ADDR[22]
set_location_assignment PIN_AH8 -to FL_DQ[0]
set_location_assignment PIN_AF10 -to FL_DQ[1]
set_location_assignment PIN_AG10 -to FL_DQ[2]
set_location_assignment PIN_AH10 -to FL_DQ[3]
set_location_assignment PIN_AF11 -to FL_DQ[4]
set_location_assignment PIN_AG11 -to FL_DQ[5]
set_location_assignment PIN_AH11 -to FL_DQ[6]
set_location_assignment PIN_AF12 -to FL_DQ[7]
set_location_assignment PIN_AG7 -to FL_CE_N
set_location_assignment PIN_AG8 -to FL_OE_N
set_location_assignment PIN_AE11 -to FL_RST_N
set_location_assignment PIN_Y1 -to FL_RY
set_location_assignment PIN_AC10 -to FL_WE_N
set_location_assignment PIN_AE12 -to FL_WP_N
set_location_assignment PIN_AB22 -to GPIO[0]
set_location_assignment PIN_AC15 -to GPIO[1]
set_location_assignment PIN_AB21 -to GPIO[2]
set_location_assignment PIN_Y17 -to GPIO[3]
set_location_assignment PIN_AC21 -to GPIO[4]
set_location_assignment PIN_Y16 -to GPIO[5]
set_location_assignment PIN_AD21 -to GPIO[6]
set_location_assignment PIN_AE16 -to GPIO[7]
set_location_assignment PIN_AD15 -to GPIO[8]
set_location_assignment PIN_AE15 -to GPIO[9]
set_location_assignment PIN_AC19 -to GPIO[10]
set_location_assignment PIN_AF16 -to GPIO[11]
set_location_assignment PIN_AD19 -to GPIO[12]
set_location_assignment PIN_AF15 -to GPIO[13]
set_location_assignment PIN_AF24 -to GPIO[14]
set_location_assignment PIN_AE21 -to GPIO[15]
set_location_assignment PIN_AF25 -to GPIO[16]
set_location_assignment PIN_AC22 -to GPIO[17]
set_location_assignment PIN_AE22 -to GPIO[18]
set_location_assignment PIN_AF21 -to GPIO[19]
set_location_assignment PIN_AF22 -to GPIO[20]
set_location_assignment PIN_AD22 -to GPIO[21]
set_location_assignment PIN_AG25 -to GPIO[22]
set_location_assignment PIN_AD25 -to GPIO[23]
set_location_assignment PIN_AH25 -to GPIO[24]
set_location_assignment PIN_AE25 -to GPIO[25]
set_location_assignment PIN_AG22 -to GPIO[26]
set_location_assignment PIN_AE24 -to GPIO[27]
set_location_assignment PIN_AH22 -to GPIO[28]
set_location_assignment PIN_AF26 -to GPIO[29]
set_location_assignment PIN_AE20 -to GPIO[30]
set_location_assignment PIN_AG23 -to GPIO[31]
set_location_assignment PIN_AF20 -to GPIO[32]
set_location_assignment PIN_AH26 -to GPIO[33]
set_location_assignment PIN_AH23 -to GPIO[34]
set_location_assignment PIN_AG26 -to GPIO[35]
set_location_assignment PIN_AH15 -to HSMC_CLKIN0
set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
set_location_assignment PIN_AE26 -to HSMC_D[0]
set_location_assignment PIN_AE28 -to HSMC_D[1]
set_location_assignment PIN_AE27 -to HSMC_D[2]
set_location_assignment PIN_AF27 -to HSMC_D[3]
set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
set_location_assignment PIN_J10 -to EX_IO[0]
set_location_assignment PIN_J14 -to EX_IO[1]
set_location_assignment PIN_H13 -to EX_IO[2]
set_location_assignment PIN_H14 -to EX_IO[3]
set_location_assignment PIN_F14 -to EX_IO[4]
set_location_assignment PIN_E10 -to EX_IO[5]
set_location_assignment PIN_D9 -to EX_IO[6]
set_global_assignment -name VHDL_FILE CounterUpDown4.vhd
set_global_assignment -name VHDL_FILE CounterDown4.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE CounterDown4.vwf
set_global_assignment -name BDF_FILE CounterDemo.bdf
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VHDL_FILE Bin7SegDecoder.vhd
set_global_assignment -name VHDL_FILE FreqDivider.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.qws Normal file
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Binary file not shown.

44
1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.bsf Normal file
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@ -0,0 +1,44 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 176 96)
(text "CounterDown4" (rect 5 0 65 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 20 12)(font "Arial" ))
(text "clock" (rect 21 27 41 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 160 32)
(output)
(text "count[3..0]" (rect 0 0 41 12)(font "Arial" ))
(text "count[3..0]" (rect 98 27 139 39)(font "Arial" ))
(line (pt 160 32)(pt 144 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 144 64)(line_width 1))
)
)

23
1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd Normal file
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@ -0,0 +1,23 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterDown4 is
port
(
clock : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end CounterDown4;
architecture Behavioral of CounterDown4 is
signal s_count : unsigned(3 downto 0);
begin
process(clock)
begin
if (rising_edge(clock)) then
s_count <= s_count - 1;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;

23
1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd.bak Normal file
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@ -0,0 +1,23 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterDown4 is
port
(
clk: in std_logic;
count : out std_logic_vector(3 downto 0)
);
end CounterDown4;
architecture Behavioral of CounterDown4 is
signal s_count : unsigned(3 downto 0);
begin
process(clk)
begin
if (rising_edge(clk)) then
s_count <= s_count - 1;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;

253
1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vwf Normal file
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@ -0,0 +1,253 @@
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CounterDemo -c CounterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDown4.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CounterDemo -c CounterDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/CounterDown4.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/" CounterDemo -c CounterDemo</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/qsim/" CounterDemo -c CounterDemo</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work CounterDemo.vho
vcom -work work CounterDown4.vwf.vht
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CounterDown4_vhd_vec_tst
vcd file -direction CounterDemo.msim.vcd
vcd add -internal CounterDown4_vhd_vec_tst/*
vcd add -internal CounterDown4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work CounterDemo.vho
vcom -work work CounterDown4.vwf.vht
vsim -novopt -c -t 1ps -sdfmax CounterDown4_vhd_vec_tst/i1=CounterDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CounterDown4_vhd_vec_tst
vcd file -direction CounterDemo.msim.vcd
vcd add -internal CounterDown4_vhd_vec_tst/*
vcd add -internal CounterDown4_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("count")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 4;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("count[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
SIGNAL("count[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
SIGNAL("count[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
SIGNAL("count[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "count";
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 25;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 20.0;
}
}
}
TRANSITION_LIST("count[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("count[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("count[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("count[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "count";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
CHILDREN = 2, 3, 4, 5;
}
DISPLAY_LINE
{
CHANNEL = "count[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 1;
PARENT = 1;
}
DISPLAY_LINE
{
CHANNEL = "count[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 1;
PARENT = 1;
}
DISPLAY_LINE
{
CHANNEL = "count[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 1;
}
DISPLAY_LINE
{
CHANNEL = "count[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 1;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

58
1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.bsf Normal file
View File

@ -0,0 +1,58 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 192 128)
(text "CounterUpDown4" (rect 5 0 76 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 20 12)(font "Arial" ))
(text "clock" (rect 21 27 41 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "reset" (rect 0 0 20 12)(font "Arial" ))
(text "reset" (rect 21 43 41 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "upDown" (rect 0 0 31 12)(font "Arial" ))
(text "upDown" (rect 21 59 52 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 176 32)
(output)
(text "count[3..0]" (rect 0 0 41 12)(font "Arial" ))
(text "count[3..0]" (rect 114 27 155 39)(font "Arial" ))
(line (pt 176 32)(pt 160 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 160 96)(line_width 1))
)
)

31
1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd Normal file
View File

@ -0,0 +1,31 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterUpDown4 is
port
(
clock : in std_logic;
reset : in std_logic;
upDown : in std_logic;
count : out std_logic_vector(3 downto 0)
);
end CounterUpDown4;
architecture Behavioral of CounterUpDown4 is
signal s_count : unsigned(3 downto 0);
begin
process(clock, reset, upDown)
begin
if (reset = '1') then
s_count <= to_unsigned(0, 4);
elsif (rising_edge(clock)) then
if (upDown = '1') then
s_count <= s_count - 1;
else
s_count <= s_count + 1;
end if;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;

23
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity CounterDown4 is
port
(
clk: in std_logic;
count : out std_logic_vector(3 downto 0)
);
end CounterDown4;
architecture Behavioral of CounterDown4 is
signal s_count : unsigned(3 downto 0);
begin
process(clk)
begin
if (rising_edge(clk)) then
s_count <= s_count - 1;
end if;
end process;
count <= std_logic_vector(s_count);
end Behavioral;

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 160 96)
(text "FreqDivider" (rect 5 0 52 12)(font "Arial" ))
(text "inst" (rect 8 64 20 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clkIn" (rect 0 0 17 12)(font "Arial" ))
(text "clkIn" (rect 21 27 38 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 144 32)
(output)
(text "clkOut" (rect 0 0 24 12)(font "Arial" ))
(text "clkOut" (rect 99 27 123 39)(font "Arial" ))
(line (pt 144 32)(pt 128 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 128 64)(line_width 1))
)
)

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider is
port (clkIn : in std_logic;
clkOut : out std_logic
);
end FreqDivider;
architecture Behavioral of FreqDivider is
signal s_counter : unsigned(31 downto 0);
signal s_halfWay : unsigned(31 downto 0);
signal k : std_logic_vector(31 downto 0);
begin
k <= x"017D7840";
s_halfWay <= unsigned(k);
process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_counter = s_halfWay - 1) then
clkOut <= '0';
s_counter <= (others => '0');
else
if (s_counter = s_halfWay/2 - 1) then
clkOut <= '1';
end if;
s_counter <= s_counter + 1;
end if;
end if;
end process;
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity FreqDivider is
port (clkIn : in std_logic;
k : in std_logic_vector(31 downto 0);
clkOut : out std_logic
);
end FreqDivider;
architecture Behavioral of FreqDivider is
signal s_counter : unsigned(31 downto 0);
signal s_halfWay : unsigned(31 downto 0);
begin
s_halfWay <= unsigned(k);
process(clkIn)
begin
if (rising_edge(clkIn)) then
if (s_counter = s_halfWay - 1) then
clkOut <= '0';
s_counter <= (others => '0');
else
if (s_counter = s_halfWay/2 - 1) then
clkOut <= '1';
end if;
s_counter <= s_counter + 1;
end if;
end if;
end process;
end Behavioral;

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318129121 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318129121 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:15:29 2023 " "Processing started: Mon Mar 20 13:15:29 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318129121 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679318129121 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679318129121 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679318129243 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679318130666 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679318130726 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "364 " "Peak virtual memory: 364 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318130905 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:15:30 2023 " "Processing ended: Mon Mar 20 13:15:30 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318130905 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318130905 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318130905 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679318130905 ""}

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="CounterDemo">
</PROJECT>
</LOG_ROOT>

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v1
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
IO_RULES_MATRIX,Total Pass,0;10;10;0;0;10;10;0;0;0;0;0;0;7;0;0;0;3;7;0;3;0;0;7;0;10;10;10;0;0,
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,Total Inapplicable,10;0;0;10;10;0;0;10;10;10;10;10;10;3;10;10;10;7;3;10;7;10;10;3;10;0;0;0;10;10,
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
IO_RULES_MATRIX,HEX0[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,HEX0[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,KEY[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,CLOCK_50,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
IO_RULES_SUMMARY,Total I/O Rules,30,
IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,

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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Mon Mar 20 12:53:27 2023

6
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318133210 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318133210 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:15:33 2023 " "Processing started: Mon Mar 20 13:15:33 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318133210 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318133210 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo " "Command: quartus_eda --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318133210 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1679318133360 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "CounterDemo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/ simulation " "Generated file CounterDemo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1679318133388 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318133399 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:15:33 2023 " "Processing ended: Mon Mar 20 13:15:33 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318133399 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318133399 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318133399 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1679318133399 ""}

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|CounterDemo
HEX0[0] <= Bin7SegDecoder:hex.decOut_n[0]
HEX0[1] <= Bin7SegDecoder:hex.decOut_n[1]
HEX0[2] <= Bin7SegDecoder:hex.decOut_n[2]
HEX0[3] <= Bin7SegDecoder:hex.decOut_n[3]
HEX0[4] <= Bin7SegDecoder:hex.decOut_n[4]
HEX0[5] <= Bin7SegDecoder:hex.decOut_n[5]
HEX0[6] <= Bin7SegDecoder:hex.decOut_n[6]
CLOCK_50 => FreqDivider:inst1.clkIn
KEY[1] => inst3.IN0
SW[0] => CounterUpDown4:inst.upDown
|CounterDemo|Bin7SegDecoder:hex
binInput[0] => Equal0.IN3
binInput[0] => Equal1.IN0
binInput[0] => Equal2.IN3
binInput[0] => Equal3.IN1
binInput[0] => Equal4.IN3
binInput[0] => Equal5.IN1
binInput[0] => Equal6.IN3
binInput[0] => Equal7.IN2
binInput[0] => Equal8.IN3
binInput[0] => Equal9.IN1
binInput[0] => Equal10.IN3
binInput[0] => Equal11.IN2
binInput[0] => Equal12.IN3
binInput[0] => Equal13.IN2
binInput[0] => Equal14.IN3
binInput[1] => Equal0.IN2
binInput[1] => Equal1.IN3
binInput[1] => Equal2.IN0
binInput[1] => Equal3.IN0
binInput[1] => Equal4.IN2
binInput[1] => Equal5.IN3
binInput[1] => Equal6.IN1
binInput[1] => Equal7.IN1
binInput[1] => Equal8.IN2
binInput[1] => Equal9.IN3
binInput[1] => Equal10.IN1
binInput[1] => Equal11.IN1
binInput[1] => Equal12.IN2
binInput[1] => Equal13.IN3
binInput[1] => Equal14.IN2
binInput[2] => Equal0.IN1
binInput[2] => Equal1.IN2
binInput[2] => Equal2.IN2
binInput[2] => Equal3.IN3
binInput[2] => Equal4.IN0
binInput[2] => Equal5.IN0
binInput[2] => Equal6.IN0
binInput[2] => Equal7.IN0
binInput[2] => Equal8.IN1
binInput[2] => Equal9.IN2
binInput[2] => Equal10.IN2
binInput[2] => Equal11.IN3
binInput[2] => Equal12.IN1
binInput[2] => Equal13.IN1
binInput[2] => Equal14.IN1
binInput[3] => Equal0.IN0
binInput[3] => Equal1.IN1
binInput[3] => Equal2.IN1
binInput[3] => Equal3.IN2
binInput[3] => Equal4.IN1
binInput[3] => Equal5.IN2
binInput[3] => Equal6.IN2
binInput[3] => Equal7.IN3
binInput[3] => Equal8.IN0
binInput[3] => Equal9.IN0
binInput[3] => Equal10.IN0
binInput[3] => Equal11.IN0
binInput[3] => Equal12.IN0
binInput[3] => Equal13.IN0
binInput[3] => Equal14.IN0
decOut_n[0] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
decOut_n[1] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
decOut_n[2] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
decOut_n[3] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
decOut_n[4] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
decOut_n[5] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
decOut_n[6] <= decOut_n.DB_MAX_OUTPUT_PORT_TYPE
|CounterDemo|CounterUpDown4:inst
clock => s_count[0].CLK
clock => s_count[1].CLK
clock => s_count[2].CLK
clock => s_count[3].CLK
reset => s_count[0].ACLR
reset => s_count[1].ACLR
reset => s_count[2].ACLR
reset => s_count[3].ACLR
upDown => s_count.OUTPUTSELECT
upDown => s_count.OUTPUTSELECT
upDown => s_count.OUTPUTSELECT
upDown => s_count.OUTPUTSELECT
count[0] <= s_count[0].DB_MAX_OUTPUT_PORT_TYPE
count[1] <= s_count[1].DB_MAX_OUTPUT_PORT_TYPE
count[2] <= s_count[2].DB_MAX_OUTPUT_PORT_TYPE
count[3] <= s_count[3].DB_MAX_OUTPUT_PORT_TYPE
|CounterDemo|FreqDivider:inst1
clkIn => s_counter[0].CLK
clkIn => s_counter[1].CLK
clkIn => s_counter[2].CLK
clkIn => s_counter[3].CLK
clkIn => s_counter[4].CLK
clkIn => s_counter[5].CLK
clkIn => s_counter[6].CLK
clkIn => s_counter[7].CLK
clkIn => s_counter[8].CLK
clkIn => s_counter[9].CLK
clkIn => s_counter[10].CLK
clkIn => s_counter[11].CLK
clkIn => s_counter[12].CLK
clkIn => s_counter[13].CLK
clkIn => s_counter[14].CLK
clkIn => s_counter[15].CLK
clkIn => s_counter[16].CLK
clkIn => s_counter[17].CLK
clkIn => s_counter[18].CLK
clkIn => s_counter[19].CLK
clkIn => s_counter[20].CLK
clkIn => s_counter[21].CLK
clkIn => s_counter[22].CLK
clkIn => s_counter[23].CLK
clkIn => s_counter[24].CLK
clkIn => s_counter[25].CLK
clkIn => s_counter[26].CLK
clkIn => s_counter[27].CLK
clkIn => s_counter[28].CLK
clkIn => s_counter[29].CLK
clkIn => s_counter[30].CLK
clkIn => s_counter[31].CLK
clkIn => clkOut~reg0.CLK
clkOut <= clkOut~reg0.DB_MAX_OUTPUT_PORT_TYPE

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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >inst1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >hex</TD>
<TD >4</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >7</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; inst1 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst ; 3 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; hex ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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v1

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318115039 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318115039 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:15:14 2023 " "Processing started: Mon Mar 20 13:15:14 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318115039 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318115039 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318115039 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1679318115167 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1679318115167 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CounterUpDown4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file CounterUpDown4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CounterUpDown4-Behavioral " "Found design unit 1: CounterUpDown4-Behavioral" { } { { "CounterUpDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} { "Info" "ISGN_ENTITY_NAME" "1 CounterUpDown4 " "Found entity 1: CounterUpDown4" { } { { "CounterUpDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterUpDown4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119662 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CounterDown4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file CounterDown4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CounterDown4-Behavioral " "Found design unit 1: CounterDown4-Behavioral" { } { { "CounterDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} { "Info" "ISGN_ENTITY_NAME" "1 CounterDown4 " "Found entity 1: CounterDown4" { } { { "CounterDown4.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDown4.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119662 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119662 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CounterDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file CounterDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CounterDemo " "Found entity 1: CounterDemo" { } { { "CounterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119663 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Bin7SegDecoder.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Bin7SegDecoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Bin7SegDecoder-Behavioral " "Found design unit 1: Bin7SegDecoder-Behavioral" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} { "Info" "ISGN_ENTITY_NAME" "1 Bin7SegDecoder " "Found entity 1: Bin7SegDecoder" { } { { "Bin7SegDecoder.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/Bin7SegDecoder.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119663 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FreqDivider.vhd 2 1 " "Found 2 design units, including 1 entities, in source file FreqDivider.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FreqDivider-Behavioral " "Found design unit 1: FreqDivider-Behavioral" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} { "Info" "ISGN_ENTITY_NAME" "1 FreqDivider " "Found entity 1: FreqDivider" { } { { "FreqDivider.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd" 5 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1679318119663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318119663 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "CounterDemo " "Elaborating entity \"CounterDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1679318119688 ""}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst3 " "Block or symbol \"NOT\" of instance \"inst3\" overlaps another block or symbol" { } { { "CounterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 224 432 480 256 "inst3" "" } } } } } 0 275011 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "Analysis & Synthesis" 0 -1 1679318119688 ""}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "Bin7SegDecoder hex " "Block or symbol \"Bin7SegDecoder\" of instance \"hex\" overlaps another block or symbol" { } { { "CounterDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 192 672 880 272 "hex" "" } } } } } 0 275011 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0 "Analysis & Synthesis" 0 -1 1679318119688 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Bin7SegDecoder Bin7SegDecoder:hex " "Elaborating entity \"Bin7SegDecoder\" for hierarchy \"Bin7SegDecoder:hex\"" { } { { "CounterDemo.bdf" "hex" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 192 672 880 272 "hex" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318119690 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CounterUpDown4 CounterUpDown4:inst " "Elaborating entity \"CounterUpDown4\" for hierarchy \"CounterUpDown4:inst\"" { } { { "CounterDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 192 488 664 304 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318119691 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FreqDivider FreqDivider:inst1 " "Elaborating entity \"FreqDivider\" for hierarchy \"FreqDivider:inst1\"" { } { { "CounterDemo.bdf" "inst1" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/CounterDemo.bdf" { { 152 328 472 232 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318119691 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1679318120030 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1679318120333 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1679318120333 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "82 " "Implemented 82 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1679318120349 ""} { "Info" "ICUT_CUT_TM_OPINS" "7 " "Implemented 7 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1679318120349 ""} { "Info" "ICUT_CUT_TM_LCELLS" "72 " "Implemented 72 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1679318120349 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1679318120349 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "446 " "Peak virtual memory: 446 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318120352 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:15:20 2023 " "Processing ended: Mon Mar 20 13:15:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318120352 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318120352 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318120352 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1679318120352 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318131335 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318131336 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:15:31 2023 " "Processing started: Mon Mar 20 13:15:31 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318131336 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131336 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta CounterDemo -c CounterDemo " "Command: quartus_sta CounterDemo -c CounterDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131336 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1679318131355 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1679318131412 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1679318131412 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131454 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131454 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "CounterDemo.sdc " "Synopsys Design Constraints File file not found: 'CounterDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1679318131740 ""}
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131740 ""}
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name FreqDivider:inst1\|clkOut FreqDivider:inst1\|clkOut " "create_clock -period 1.000 -name FreqDivider:inst1\|clkOut FreqDivider:inst1\|clkOut" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1679318131740 ""} { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1679318131740 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131740 ""}
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131741 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131741 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1679318131741 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1679318131744 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679318131749 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679318131749 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.122 " "Worst-case setup slack is -4.122" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.122 -69.260 CLOCK_50 " " -4.122 -69.260 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.839 -1.988 FreqDivider:inst1\|clkOut " " -0.839 -1.988 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131750 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.408 " "Worst-case hold slack is 0.408" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.408 0.000 FreqDivider:inst1\|clkOut " " 0.408 0.000 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.652 0.000 CLOCK_50 " " 0.652 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131750 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131750 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318131751 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318131751 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131752 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -5.140 FreqDivider:inst1\|clkOut " " -1.285 -5.140 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131752 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131752 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679318131764 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1679318131776 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1679318131929 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131942 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679318131944 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679318131944 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -3.714 " "Worst-case setup slack is -3.714" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.714 -59.180 CLOCK_50 " " -3.714 -59.180 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131944 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.650 -1.486 FreqDivider:inst1\|clkOut " " -0.650 -1.486 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131944 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131944 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.364 " "Worst-case hold slack is 0.364" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.364 0.000 FreqDivider:inst1\|clkOut " " 0.364 0.000 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131945 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.596 0.000 CLOCK_50 " " 0.596 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131945 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131945 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318131946 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318131947 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131948 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131948 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -45.405 CLOCK_50 " " -3.000 -45.405 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131948 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.285 -5.140 FreqDivider:inst1\|clkOut " " -1.285 -5.140 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131948 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131948 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1679318131961 ""}
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1679318131998 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1679318131998 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1679318131998 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.587 " "Worst-case setup slack is -1.587" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131999 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131999 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.587 -18.604 CLOCK_50 " " -1.587 -18.604 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131999 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.109 0.000 FreqDivider:inst1\|clkOut " " 0.109 0.000 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318131999 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318131999 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.188 " "Worst-case hold slack is 0.188" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132000 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132000 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.188 0.000 FreqDivider:inst1\|clkOut " " 0.188 0.000 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132000 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.297 0.000 CLOCK_50 " " 0.297 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132000 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318132000 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318132001 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1679318132002 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132003 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132003 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -38.022 CLOCK_50 " " -3.000 -38.022 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132003 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.000 -4.000 FreqDivider:inst1\|clkOut " " -1.000 -4.000 FreqDivider:inst1\|clkOut " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1679318132003 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1679318132003 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679318132228 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1679318132228 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "538 " "Peak virtual memory: 538 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318132244 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:15:32 2023 " "Processing ended: Mon Mar 20 13:15:32 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318132244 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318132244 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318132244 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1679318132244 ""}

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7
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start_full_compilation:s:00:00:19
start_analysis_synthesis:s:00:00:06-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:08-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:02-start_full_compilation
start_eda_netlist_writer:s:00:00:01-start_full_compilation

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49
1ano/2semestre/lsd/pratica04/CounterDemo/db/CounterDemo_partition_pins.json Normal file
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{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "HEX0[6]",
"strict" : false
},
{
"name" : "HEX0[5]",
"strict" : false
},
{
"name" : "HEX0[4]",
"strict" : false
},
{
"name" : "HEX0[3]",
"strict" : false
},
{
"name" : "HEX0[2]",
"strict" : false
},
{
"name" : "HEX0[1]",
"strict" : false
},
{
"name" : "HEX0[0]",
"strict" : false
},
{
"name" : "SW[0]",
"strict" : false
},
{
"name" : "KEY[1]",
"strict" : false
},
{
"name" : "CLOCK_50",
"strict" : false
}
]
}
]
}

4
1ano/2semestre/lsd/pratica04/CounterDemo/db/prev_cmp_CounterDemo.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318059500 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus Prime " "Running Quartus Prime Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318059500 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:14:19 2023 " "Processing started: Mon Mar 20 13:14:19 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318059500 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1679318059500 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd " "Command: quartus_map --read_settings_files=on --write_settings_files=off CounterDemo -c CounterDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/FreqDivider.vhd" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1679318059500 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus Prime " "Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "696 " "Peak virtual memory: 696 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318059832 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:14:19 2023 " "Processing ended: Mon Mar 20 13:14:19 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318059832 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318059832 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318059832 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1679318059832 ""}

11
1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/README Normal file
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@ -0,0 +1,11 @@
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
1ano/2semestre/lsd/pratica04/CounterDemo/incremental_db/compiled_partitions/CounterDemo.db_info Normal file
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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Version_Index = 520278016
Creation_Time = Thu Mar 16 16:46:48 2023

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1
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v1

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c5eb7f6cdd530884c3b884e0a3668ea4

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92
1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.asm.rpt Normal file
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Assembler report for CounterDemo
Mon Mar 20 13:15:30 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: CounterDemo.sof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Mon Mar 20 13:15:30 2023 ;
; Revision Name ; CounterDemo ;
; Top-level Entity Name ; CounterDemo ;
; Family ; Cyclone IV E ;
; Device ; EP4CE115F29C7 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Generated Files ;
+--------------------------------------------------------------------------------------------------------+
; File Name ;
+--------------------------------------------------------------------------------------------------------+
; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.sof ;
+--------------------------------------------------------------------------------------------------------+
+-------------------------------------------+
; Assembler Device Options: CounterDemo.sof ;
+----------------+--------------------------+
; Option ; Setting ;
+----------------+--------------------------+
; JTAG usercode ; 0x0056A839 ;
; Checksum ; 0x0056A839 ;
+----------------+--------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Processing started: Mon Mar 20 13:15:29 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off CounterDemo -c CounterDemo
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
Info: Peak virtual memory: 364 megabytes
Info: Processing ended: Mon Mar 20 13:15:30 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:02

13
1ano/2semestre/lsd/pratica04/CounterDemo/output_files/CounterDemo.cdf Normal file
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/* Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP4CE115F29) Path("/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica04/CounterDemo/output_files/") File("CounterDemo.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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