diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf b/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf new file mode 100644 index 0000000..1e7ddd8 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf @@ -0,0 +1,435 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht" +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/" EqCmpDemo -c EqCmpDemo +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/" EqCmpDemo -c EqCmpDemo +onerror {exit -code 1} +vlib work +vcom -work work EqCmpDemo.vho +vcom -work work EqCmp4.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst +vcd file -direction EqCmpDemo.msim.vcd +vcd add -internal EqCmpDemo_vhd_vec_tst/* +vcd add -internal EqCmpDemo_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vcom -work work EqCmpDemo.vho +vcom -work work EqCmp4.vwf.vht +vsim -novopt -c -t 1ps -sdfmax EqCmpDemo_vhd_vec_tst/i1=EqCmpDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst +vcd file -direction EqCmpDemo.msim.vcd +vcd add -internal EqCmpDemo_vhd_vec_tst/* +vcd add -internal EqCmpDemo_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +vhdl +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDG") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDG[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDG") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDG[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 2; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + } + LEVEL 0 FOR 200.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 5; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 10; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 20; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 40; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 80; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 148; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + } + LEVEL 0 FOR 1.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmp8.bsf b/1ano/2semestre/lsd/pratica01/part4/EqCmp8.bsf new file mode 100644 index 0000000..bef6bb0 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/EqCmp8.bsf @@ -0,0 +1,51 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 192 96) + (text "EqCmp8" (rect 5 0 41 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "input0[7..0]" (rect 0 0 42 12)(font "Arial" )) + (text "input0[7..0]" (rect 21 27 63 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "input1[7..0]" (rect 0 0 41 12)(font "Arial" )) + (text "input1[7..0]" (rect 21 43 62 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 176 32) + (output) + (text "cmpOut" (rect 0 0 31 12)(font "Arial" )) + (text "cmpOut" (rect 124 27 155 39)(font "Arial" )) + (line (pt 176 32)(pt 160 32)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 160 64)(line_width 1)) + ) +) diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd b/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd new file mode 100644 index 0000000..61d4c6f --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd @@ -0,0 +1,16 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +entity EqCmp8 is + port + ( + input0 : in std_logic_vector(7 downto 0); + input1 : in std_logic_vector(7 downto 0); + cmpOut : out std_logic + ); +end EqCmp8; + +architecture Behavioral of EqCmp8 is +begin + cmpOut <= '1' when (input0 = input1) else '0'; +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd.bak b/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd.bak new file mode 100644 index 0000000..e69de29 diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vwf b/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vwf new file mode 100644 index 0000000..6364927 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vwf @@ -0,0 +1,2223 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp8.vwf.vht" +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp8.vwf.vht" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/" EqCmpDemo -c EqCmpDemo +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/" EqCmpDemo -c EqCmpDemo +onerror {exit -code 1} +vlib work +vcom -work work EqCmpDemo.vho +vcom -work work EqCmp8.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst +vcd file -direction EqCmpDemo.msim.vcd +vcd add -internal EqCmpDemo_vhd_vec_tst/* +vcd add -internal EqCmpDemo_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vcom -work work EqCmpDemo.vho +vcom -work work EqCmp8.vwf.vht +vsim -novopt -c -t 1ps -sdfmax EqCmpDemo_vhd_vec_tst/i1=EqCmpDemo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst +vcd file -direction EqCmpDemo.msim.vcd +vcd add -internal EqCmpDemo_vhd_vec_tst/* +vcd add -internal EqCmpDemo_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +vhdl +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDG") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDG[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 16; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[15]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[14]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDG") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDG[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("SW[15]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 40.0; + } +} + +TRANSITION_LIST("SW[14]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + } +} + +TRANSITION_LIST("SW[13]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + } +} + +TRANSITION_LIST("SW[12]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + } +} + +TRANSITION_LIST("SW[11]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 35.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + } +} + +TRANSITION_LIST("SW[10]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 45.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 45.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 35.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 45.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 35.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 35.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[15]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[14]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf index 75079ea..501b0b4 100644 --- a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf +++ b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf @@ -56,7 +56,7 @@ https://fpgasoftware.intel.com/eula. ) (pin (output) - (rect 648 200 824 216) + (rect 656 200 832 216) (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) (text "LEDG[0]" (rect 90 0 132 11)(font "Arial" )) (pt 0 8) @@ -69,12 +69,12 @@ https://fpgasoftware.intel.com/eula. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 824 216 880 232)) + (annotation_block (location)(rect 832 216 888 232)) ) (symbol (rect 472 176 640 272) (text "EqCmp4" (rect 5 0 55 15)(font "Intel Clear" (font_size 8))) - (text "inst" (rect 8 79 28 92)(font "Intel Clear" )) + (text "inst1" (rect 8 79 32 92)(font "Intel Clear" )) (port (pt 0 32) (input) @@ -111,6 +111,6 @@ https://fpgasoftware.intel.com/eula. (bus) ) (connector + (pt 656 208) (pt 640 208) - (pt 648 208) ) diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf index 0f4bd65..ca5a90b 100644 --- a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf +++ b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf @@ -1176,7 +1176,9 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] set_location_assignment PIN_D9 -to EX_IO[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] set_global_assignment -name BDF_FILE EqCmpDemo.bdf -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE EqCmp8.vhd +set_global_assignment -name VECTOR_WAVEFORM_FILE EqCmp8.vwf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf.bak b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf.bak index 75ab668..34c1f6f 100644 --- a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf.bak +++ b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qsf.bak @@ -57,4 +57,1127 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan set_global_assignment -name BDF_FILE EqCmp4.bdf set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" \ No newline at end of file +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_location_assignment PIN_Y2 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "2.5 V" -to CLOCK_50 +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to CLOCK3_50 +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT +set_location_assignment PIN_M23 -to KEY[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[0] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[1] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[2] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to KEY[3] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to KEY[3] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to KEY +set_location_assignment PIN_AB28 -to SW[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[0] +set_location_assignment PIN_AC28 -to SW[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[4] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[5] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[6] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[6] +set_location_assignment PIN_AB26 -to SW[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[7] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[8] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[9] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[10] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[11] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[12] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[13] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[14] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[15] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[16] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[17] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SW[17] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to SW +set_location_assignment PIN_G19 -to LEDR[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] +set_location_assignment PIN_F19 -to LEDR[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] +set_location_assignment PIN_E19 -to LEDR[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] +set_location_assignment PIN_F21 -to LEDR[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] +set_location_assignment PIN_E21 -to LEDG[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] +set_location_assignment PIN_G18 -to HEX0[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] +set_location_assignment PIN_E17 -to HEX0[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[6] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX0 +set_location_assignment PIN_M24 -to HEX1[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[0] +set_location_assignment PIN_Y22 -to HEX1[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX1[6] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX1 +set_location_assignment PIN_AA25 -to HEX2[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[4] +set_location_assignment PIN_W27 -to HEX2[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX2[6] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX2 +set_location_assignment PIN_V21 -to HEX3[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[0] +set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to HEX3[1] +set_location_assignment PIN_AB19 -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] +set_location_assignment PIN_AG17 -to HEX7[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] +set_location_assignment PIN_L6 -to LCD_BLON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON +set_location_assignment PIN_M1 -to LCD_RW +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW +set_location_assignment PIN_L4 -to LCD_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN +set_location_assignment PIN_M2 -to LCD_RS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON +set_location_assignment PIN_G9 -to UART_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD +set_location_assignment PIN_G12 -to UART_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to UART_RXD +set_location_assignment PIN_G14 -to UART_CTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS +set_location_assignment PIN_J13 -to UART_RTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to UART_RTS +set_location_assignment PIN_G6 -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_location_assignment PIN_H5 -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT +set_location_assignment PIN_G5 -to PS2_CLK2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 +set_location_assignment PIN_F5 -to PS2_DAT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 +set_location_assignment PIN_AE13 -to SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD +set_location_assignment PIN_AF14 -to SD_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to SD_WP_N +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] +set_location_assignment PIN_G13 -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N +set_location_assignment PIN_A12 -to VGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N +set_location_assignment PIN_E12 -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_location_assignment PIN_E11 -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_location_assignment PIN_D10 -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_location_assignment PIN_F12 -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_location_assignment PIN_G10 -to VGA_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] +set_location_assignment PIN_J12 -to VGA_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] +set_location_assignment PIN_H8 -to VGA_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] +set_location_assignment PIN_H10 -to VGA_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] +set_location_assignment PIN_G8 -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_location_assignment PIN_G11 -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_location_assignment PIN_F8 -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_location_assignment PIN_H12 -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_location_assignment PIN_C8 -to VGA_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] +set_location_assignment PIN_B8 -to VGA_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] +set_location_assignment PIN_F10 -to VGA_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] +set_location_assignment PIN_C9 -to VGA_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] +set_location_assignment PIN_B10 -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_location_assignment PIN_A10 -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_location_assignment PIN_C11 -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_location_assignment PIN_B11 -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_location_assignment PIN_A11 -to VGA_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] +set_location_assignment PIN_C12 -to VGA_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] +set_location_assignment PIN_D11 -to VGA_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] +set_location_assignment PIN_D12 -to VGA_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to AUD_ADCDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_location_assignment PIN_D1 -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_location_assignment PIN_E1 -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK +set_location_assignment PIN_F2 -to AUD_BCLK +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT +set_location_assignment PIN_B7 -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT +set_location_assignment PIN_A14 -to ENETCLK_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENETCLK_25 +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_LINK100 +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK +set_location_assignment PIN_C19 -to ENET0_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N +set_location_assignment PIN_C20 -to ENET0_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_MDIO +set_location_assignment PIN_A21 -to ENET0_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_INT_N +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_TX_CLK +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[0] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[1] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[2] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DATA[3] +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_CLK +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_ER +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_CRS +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET0_RX_COL +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_LINK100 +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK +set_location_assignment PIN_D22 -to ENET1_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N +set_location_assignment PIN_D23 -to ENET1_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_MDIO +set_location_assignment PIN_D24 -to ENET1_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_INT_N +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_TX_CLK +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[0] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[1] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[2] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DATA[3] +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_CLK +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_ER +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_CRS +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to ENET1_RX_COL +set_location_assignment PIN_E5 -to TD_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_HS +set_location_assignment PIN_E4 -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_VS +set_location_assignment PIN_B14 -to TD_CLK27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_CLK27 +set_location_assignment PIN_G7 -to TD_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N +set_location_assignment PIN_E8 -to TD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[0] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[1] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[2] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[3] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[4] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[5] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[6] +set_location_assignment PIN_F7 -to TD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to TD_DATA[7] +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DREQ[0] +set_location_assignment PIN_A3 -to OTG_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N +set_location_assignment PIN_A4 -to OTG_WR_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WR_N +set_location_assignment PIN_B3 -to OTG_RD_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N +set_location_assignment PIN_D5 -to OTG_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to OTG_INT +set_location_assignment PIN_C5 -to OTG_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N +set_location_assignment PIN_Y15 -to IRDA_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to IRDA_RXD +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_location_assignment PIN_AE5 -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_location_assignment PIN_V6 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] +set_location_assignment PIN_AG7 -to FL_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N +set_location_assignment PIN_Y1 -to FL_RY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to FL_RY +set_location_assignment PIN_AC10 -to FL_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N +set_location_assignment PIN_AB22 -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_location_assignment PIN_AD15 -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_location_assignment PIN_AC19 -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_location_assignment PIN_AH23 -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HSMC_CLKIN0 +set_instance_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -to HSMC_CLKIN0 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_CLKOUT0 +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[2] +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HSMC_D[3] +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N1 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_P2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKIN_N2 +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_CLKOUT_N2 +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[7] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_TX_D_N[16] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[0] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[1] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[2] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[3] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[4] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[5] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[6] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[7] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[8] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[9] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[10] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[11] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[12] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[13] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[14] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[15] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_P[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_instance_assignment -name IO_STANDARD LVDS -to HSMC_RX_D_N[16] +set_location_assignment PIN_J10 -to EX_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0] +set_location_assignment PIN_J14 -to EX_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1] +set_location_assignment PIN_H13 -to EX_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2] +set_location_assignment PIN_H14 -to EX_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3] +set_location_assignment PIN_F14 -to EX_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4] +set_location_assignment PIN_E10 -to EX_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] +set_location_assignment PIN_D9 -to EX_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] +set_global_assignment -name BDF_FILE EqCmpDemo.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE EqCmp8.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qws b/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qws deleted file mode 100644 index afc4658..0000000 Binary files a/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.qws and /dev/null differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.cdb index 3a07798..2e17b34 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.cdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.cdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.hdb index 99e57f0..5052fed 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.hdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(0).cnf.hdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.cdb new file mode 100644 index 0000000..eaf9f32 Binary files /dev/null and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.cdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.hdb new file mode 100644 index 0000000..ea0a1ed Binary files /dev/null and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.(2).cnf.hdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm.qmsg b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm.qmsg index 431cb38..1a626aa 100644 --- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm.qmsg +++ b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.asm.qmsg @@ -1,7 +1,7 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678212363509 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678212363509 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 18:06:03 2023 " "Processing started: Tue Mar 7 18:06:03 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678212363509 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678212363509 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678212363509 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678212363657 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678212365227 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678212365296 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "365 " "Peak virtual memory: 365 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678212365516 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 18:06:05 2023 " "Processing ended: Tue Mar 7 18:06:05 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678212365516 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678212365516 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678212365516 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678212365516 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678222514063 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222514063 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:55:13 2023 " "Processing started: Tue Mar 7 20:55:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678222514063 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678222514063 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678222514063 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. 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" "https://fpgasoftware.intel.com/eula." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:57:57 2023 " "Processing started: Tue Mar 7 20:57:57 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678222677858 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678222677858 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/ EqCmpDemo -c EqCmpDemo " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/ EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678222677858 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. 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Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. 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If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678212356261 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678212356261 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "AUD_ADCDAT " "Can't reserve pin AUD_ADCDAT -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK2_50 " "Can't reserve pin CLOCK2_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK3_50 " "Can't reserve pin CLOCK3_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK_50 " "Can't reserve pin CLOCK_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_INT_N " "Can't reserve pin ENET0_INT_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_LINK100 " "Can't reserve pin ENET0_LINK100 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_MDIO " "Can't reserve pin ENET0_MDIO -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_CLK " "Can't reserve pin ENET0_RX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_COL " "Can't reserve pin ENET0_RX_COL -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_CRS " "Can't reserve pin ENET0_RX_CRS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[0\] " "Can't reserve pin ENET0_RX_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[1\] " "Can't reserve pin ENET0_RX_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[2\] " "Can't reserve pin ENET0_RX_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[3\] " "Can't reserve pin ENET0_RX_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DV " "Can't reserve pin ENET0_RX_DV -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_ER " "Can't reserve pin ENET0_RX_ER -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_TX_CLK " "Can't reserve pin ENET0_TX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_INT_N " "Can't reserve pin ENET1_INT_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_LINK100 " "Can't reserve pin ENET1_LINK100 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_MDIO " "Can't reserve pin ENET1_MDIO -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_CLK " "Can't reserve pin ENET1_RX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_COL " "Can't reserve pin ENET1_RX_COL -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_CRS " "Can't reserve pin ENET1_RX_CRS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[0\] " "Can't reserve pin ENET1_RX_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[1\] " "Can't reserve pin ENET1_RX_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[2\] " "Can't reserve pin ENET1_RX_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[3\] " "Can't reserve pin ENET1_RX_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DV " "Can't reserve pin ENET1_RX_DV -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_ER " "Can't reserve pin ENET1_RX_ER -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_TX_CLK " "Can't reserve pin ENET1_TX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENETCLK_25 " "Can't reserve pin ENETCLK_25 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "FL_RY " "Can't reserve pin FL_RY -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "HSMC_CLKIN0 " "Can't reserve pin HSMC_CLKIN0 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "IRDA_RXD " "Can't reserve pin IRDA_RXD -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[0\] " "Can't reserve pin KEY\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[1\] " "Can't reserve pin KEY\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[2\] " "Can't reserve pin KEY\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[3\] " "Can't reserve pin KEY\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "OTG_INT " "Can't reserve pin OTG_INT -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SD_WP_N " "Can't reserve pin SD_WP_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SMA_CLKIN " "Can't reserve pin SMA_CLKIN -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[0\] " "Can't reserve pin SW\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[0\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[0\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 14 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[10\] " "Can't reserve pin SW\[10\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356271 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[11\] " "Can't reserve pin SW\[11\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[12\] " "Can't reserve pin SW\[12\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[13\] " "Can't reserve pin SW\[13\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[14\] " "Can't reserve pin SW\[14\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[15\] " "Can't reserve pin SW\[15\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[16\] " "Can't reserve pin SW\[16\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[17\] " "Can't reserve pin SW\[17\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[1\] " "Can't reserve pin SW\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[1\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[1\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 13 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[2\] " "Can't reserve pin SW\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[2\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[2\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[3\] " "Can't reserve pin SW\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[3\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[3\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[4\] " "Can't reserve pin SW\[4\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[4\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[4\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[4] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[5\] " "Can't reserve pin SW\[5\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[5\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[5\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[5] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[6\] " "Can't reserve pin SW\[6\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[6\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[6\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[6] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 8 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[7\] " "Can't reserve pin SW\[7\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[7\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[7\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[7] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 7 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[8\] " "Can't reserve pin SW\[8\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[9\] " "Can't reserve pin SW\[9\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_CLK27 " "Can't reserve pin TD_CLK27 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[0\] " "Can't reserve pin TD_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[1\] " "Can't reserve pin TD_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[2\] " "Can't reserve pin TD_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[3\] " "Can't reserve pin TD_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[4\] " "Can't reserve pin TD_DATA\[4\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[5\] " "Can't reserve pin TD_DATA\[5\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[6\] " "Can't reserve pin TD_DATA\[6\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[7\] " "Can't reserve pin TD_DATA\[7\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_HS " "Can't reserve pin TD_HS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_VS " "Can't reserve pin TD_VS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "UART_RTS " "Can't reserve pin UART_RTS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "UART_RXD " "Can't reserve pin UART_RXD -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678212356272 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 643 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678212356274 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 645 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678212356274 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 647 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678212356274 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 649 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678212356274 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 651 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678212356274 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678212356274 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678212356283 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EqCmpDemo.sdc " "Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678212357060 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678212357061 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678212357061 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678212357061 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678212357062 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678212357062 ""} -{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678212357063 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678212357067 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678212357067 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678212357067 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678212357068 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678212357068 ""} -{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678212357069 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678212357069 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678212357069 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678212357069 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678212357069 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678212357069 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678212357120 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678212357120 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678212357129 ""} -{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678212357135 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678212358762 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678212358856 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678212358888 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678212359068 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678212359068 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678212359312 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y12 X115_Y23 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23"} { { 12 { 0 ""} 104 12 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678212361389 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678212361389 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678212361492 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678212361492 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678212361492 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678212361494 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678212361579 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678212361584 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678212361775 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678212361775 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678212361944 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678212362197 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678212362388 ""} -{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "25 Cyclone IV E " "25 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D2 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 15 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK2_50 3.3-V LVTTL AG14 " "Pin CLOCK2_50 uses I/O standard 3.3-V LVTTL at AG14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { CLOCK2_50 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 21 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK3_50 3.3-V LVTTL AG15 " "Pin CLOCK3_50 uses I/O standard 3.3-V LVTTL at AG15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { CLOCK3_50 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 22 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENET0_LINK100 3.3-V LVTTL C14 " "Pin ENET0_LINK100 uses I/O standard 3.3-V LVTTL at C14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENET0_LINK100 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 89 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENET1_LINK100 3.3-V LVTTL D13 " "Pin ENET1_LINK100 uses I/O standard 3.3-V LVTTL at D13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENET1_LINK100 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 113 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENETCLK_25 3.3-V LVTTL A14 " "Pin ENETCLK_25 uses I/O standard 3.3-V LVTTL at A14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENETCLK_25 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 135 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "FL_RY 3.3-V LVTTL Y1 " "Pin FL_RY uses I/O standard 3.3-V LVTTL at Y1" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { FL_RY } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 180 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "HSMC_CLKIN0 3.3-V LVTTL AH15 " "Pin HSMC_CLKIN0 uses I/O standard 3.3-V LVTTL at AH15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { HSMC_CLKIN0 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 284 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "IRDA_RXD 3.3-V LVTTL Y15 " "Pin IRDA_RXD uses I/O standard 3.3-V LVTTL at Y15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { IRDA_RXD } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 373 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "OTG_INT 3.3-V LVTTL D5 " "Pin OTG_INT uses I/O standard 3.3-V LVTTL at D5" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { OTG_INT } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 443 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SD_WP_N 3.3-V LVTTL AF14 " "Pin SD_WP_N uses I/O standard 3.3-V LVTTL at AF14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SD_WP_N } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 458 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SMA_CLKIN 3.3-V LVTTL AH14 " "Pin SMA_CLKIN uses I/O standard 3.3-V LVTTL at AH14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SMA_CLKIN } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 459 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_CLK27 3.3-V LVTTL B14 " "Pin TD_CLK27 uses I/O standard 3.3-V LVTTL at B14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_CLK27 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 514 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[0\] 3.3-V LVTTL E8 " "Pin TD_DATA\[0\] uses I/O standard 3.3-V LVTTL at E8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 516 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[1\] 3.3-V LVTTL A7 " "Pin TD_DATA\[1\] uses I/O standard 3.3-V LVTTL at A7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 517 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[2\] 3.3-V LVTTL D8 " "Pin TD_DATA\[2\] uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 518 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[3\] 3.3-V LVTTL C7 " "Pin TD_DATA\[3\] uses I/O standard 3.3-V LVTTL at C7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 519 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[4\] 3.3-V LVTTL D7 " "Pin TD_DATA\[4\] uses I/O standard 3.3-V LVTTL at D7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[4] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 520 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[5\] 3.3-V LVTTL D6 " "Pin TD_DATA\[5\] uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[5] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 521 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[6\] 3.3-V LVTTL E7 " "Pin TD_DATA\[6\] uses I/O standard 3.3-V LVTTL at E7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[6] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 522 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[7\] 3.3-V LVTTL F7 " "Pin TD_DATA\[7\] uses I/O standard 3.3-V LVTTL at F7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[7] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 523 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_HS 3.3-V LVTTL E5 " "Pin TD_HS uses I/O standard 3.3-V LVTTL at E5" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_HS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 524 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_VS 3.3-V LVTTL E4 " "Pin TD_VS uses I/O standard 3.3-V LVTTL at E4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_VS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 526 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART_RTS 3.3-V LVTTL J13 " "Pin UART_RTS uses I/O standard 3.3-V LVTTL at J13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { UART_RTS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 528 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART_RXD 3.3-V LVTTL G12 " "Pin UART_RXD uses I/O standard 3.3-V LVTTL at G12" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { UART_RXD } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 529 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678212362391 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1678212362391 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678212362443 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 534 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 534 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1155 " "Peak virtual memory: 1155 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678212362604 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 18:06:02 2023 " "Processing ended: Tue Mar 7 18:06:02 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678212362604 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678212362604 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678212362604 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678212362604 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1678222504333 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1678222504333 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "EqCmpDemo EP4CE115F29C7 " "Selected device EP4CE115F29C7 for design \"EqCmpDemo\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504339 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678222504440 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1678222504440 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1678222504830 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1678222504834 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C7 " "Device EP4CE40F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29I7 " "Device EP4CE40F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C7 " "Device EP4CE30F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29I7 " "Device EP4CE30F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C7 " "Device EP4CE55F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29I7 " "Device EP4CE55F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29C7 " "Device EP4CE75F29C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE75F29I7 " "Device EP4CE75F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29I7 " "Device EP4CE115F29I7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1678222504892 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1678222504892 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "AUD_ADCDAT " "Can't reserve pin AUD_ADCDAT -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK2_50 " "Can't reserve pin CLOCK2_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK3_50 " "Can't reserve pin CLOCK3_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "CLOCK_50 " "Can't reserve pin CLOCK_50 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_INT_N " "Can't reserve pin ENET0_INT_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_LINK100 " "Can't reserve pin ENET0_LINK100 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_MDIO " "Can't reserve pin ENET0_MDIO -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_CLK " "Can't reserve pin ENET0_RX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_COL " "Can't reserve pin ENET0_RX_COL -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_CRS " "Can't reserve pin ENET0_RX_CRS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[0\] " "Can't reserve pin ENET0_RX_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[1\] " "Can't reserve pin ENET0_RX_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[2\] " "Can't reserve pin ENET0_RX_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DATA\[3\] " "Can't reserve pin ENET0_RX_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_DV " "Can't reserve pin ENET0_RX_DV -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_RX_ER " "Can't reserve pin ENET0_RX_ER -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET0_TX_CLK " "Can't reserve pin ENET0_TX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_INT_N " "Can't reserve pin ENET1_INT_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_LINK100 " "Can't reserve pin ENET1_LINK100 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_MDIO " "Can't reserve pin ENET1_MDIO -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_CLK " "Can't reserve pin ENET1_RX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_COL " "Can't reserve pin ENET1_RX_COL -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_CRS " "Can't reserve pin ENET1_RX_CRS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[0\] " "Can't reserve pin ENET1_RX_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504897 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[1\] " "Can't reserve pin ENET1_RX_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[2\] " "Can't reserve pin ENET1_RX_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DATA\[3\] " "Can't reserve pin ENET1_RX_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_DV " "Can't reserve pin ENET1_RX_DV -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_RX_ER " "Can't reserve pin ENET1_RX_ER -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENET1_TX_CLK " "Can't reserve pin ENET1_TX_CLK -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "ENETCLK_25 " "Can't reserve pin ENETCLK_25 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "FL_RY " "Can't reserve pin FL_RY -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "HSMC_CLKIN0 " "Can't reserve pin HSMC_CLKIN0 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "IRDA_RXD " "Can't reserve pin IRDA_RXD -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[0\] " "Can't reserve pin KEY\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[1\] " "Can't reserve pin KEY\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[2\] " "Can't reserve pin KEY\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "KEY\[3\] " "Can't reserve pin KEY\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "OTG_INT " "Can't reserve pin OTG_INT -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SD_WP_N " "Can't reserve pin SD_WP_N -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SMA_CLKIN " "Can't reserve pin SMA_CLKIN -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[0\] " "Can't reserve pin SW\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[0\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[0\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[0\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 14 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[10\] " "Can't reserve pin SW\[10\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[11\] " "Can't reserve pin SW\[11\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[12\] " "Can't reserve pin SW\[12\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[13\] " "Can't reserve pin SW\[13\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[14\] " "Can't reserve pin SW\[14\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[15\] " "Can't reserve pin SW\[15\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[16\] " "Can't reserve pin SW\[16\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[17\] " "Can't reserve pin SW\[17\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[1\] " "Can't reserve pin SW\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[1\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[1\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[1\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 13 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[2\] " "Can't reserve pin SW\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[2\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[2\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[2\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 12 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[3\] " "Can't reserve pin SW\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[3\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[3\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[3\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 11 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[4\] " "Can't reserve pin SW\[4\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[4\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[4\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[4] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[4\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 10 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[5\] " "Can't reserve pin SW\[5\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[5\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[5\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[5] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[5\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 9 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[6\] " "Can't reserve pin SW\[6\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[6\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[6\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[6] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[6\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 8 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[7\] " "Can't reserve pin SW\[7\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_RESERVE_PIN_NAME_EXISTS_SAME_DIRECTION" "SW\[7\] " "Reserve pin assignment ignored because of existing pin with name \"SW\[7\]\"" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SW[7] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SW\[7\]" } } } } { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 200 296 464 216 "SW" "" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 7 14177 15141 0 0 "" 0 "" "" } } } } } 0 169140 "Reserve pin assignment ignored because of existing pin with name \"%1!s!\"" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[8\] " "Can't reserve pin SW\[8\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "SW\[9\] " "Can't reserve pin SW\[9\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_CLK27 " "Can't reserve pin TD_CLK27 -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[0\] " "Can't reserve pin TD_DATA\[0\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[1\] " "Can't reserve pin TD_DATA\[1\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[2\] " "Can't reserve pin TD_DATA\[2\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[3\] " "Can't reserve pin TD_DATA\[3\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[4\] " "Can't reserve pin TD_DATA\[4\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[5\] " "Can't reserve pin TD_DATA\[5\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[6\] " "Can't reserve pin TD_DATA\[6\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_DATA\[7\] " "Can't reserve pin TD_DATA\[7\] -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_HS " "Can't reserve pin TD_HS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "TD_VS " "Can't reserve pin TD_VS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504898 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "UART_RTS " "Can't reserve pin UART_RTS -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504899 ""} +{ "Warning" "WFIOMGR_INVALID_RESERVE_PIN_NAME" "UART_RXD " "Can't reserve pin UART_RXD -- pin name is an illegal or unsupported format" { } { } 0 169133 "Can't reserve pin %1!s! -- pin name is an illegal or unsupported format" 0 0 "Fitter" 0 -1 1678222504899 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 643 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678222504900 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 645 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678222504900 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 647 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678222504900 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 649 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678222504900 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 651 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1678222504900 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1678222504900 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1678222504901 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EqCmpDemo.sdc " "Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1678222505711 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1678222505711 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Fitter" 0 -1 1678222505712 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Fitter" 0 -1 1678222505712 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1678222505713 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1678222505713 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1678222505713 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1678222505716 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678222505716 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1678222505716 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678222505717 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1678222505717 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1678222505718 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1678222505718 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1678222505718 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1678222505718 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1678222505718 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1678222505718 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_ADCLRCK " "Node \"AUD_ADCLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_BCLK " "Node \"AUD_BCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACDAT " "Node \"AUD_DACDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_DACLRCK " "Node \"AUD_DACLRCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "AUD_XCK " "Node \"AUD_XCK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[0\] " "Node \"DRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[10\] " "Node \"DRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[11\] " "Node \"DRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[12\] " "Node \"DRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[1\] " "Node \"DRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[2\] " "Node \"DRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[3\] " "Node \"DRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[4\] " "Node \"DRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[5\] " "Node \"DRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[6\] " "Node \"DRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[7\] " "Node \"DRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[8\] " "Node \"DRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_ADDR\[9\] " "Node \"DRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[0\] " "Node \"DRAM_BA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_BA\[1\] " "Node \"DRAM_BA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_BA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CAS_N " "Node \"DRAM_CAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CKE " "Node \"DRAM_CKE\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CLK " "Node \"DRAM_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_CS_N " "Node \"DRAM_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[0\] " "Node \"DRAM_DQM\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[1\] " "Node \"DRAM_DQM\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[2\] " "Node \"DRAM_DQM\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQM\[3\] " "Node \"DRAM_DQM\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQM\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[0\] " "Node \"DRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[10\] " "Node \"DRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[11\] " "Node \"DRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[12\] " "Node \"DRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[13\] " "Node \"DRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[14\] " "Node \"DRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[15\] " "Node \"DRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[16\] " "Node \"DRAM_DQ\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[17\] " "Node \"DRAM_DQ\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[18\] " "Node \"DRAM_DQ\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[19\] " "Node \"DRAM_DQ\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[1\] " "Node \"DRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[20\] " "Node \"DRAM_DQ\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[21\] " "Node \"DRAM_DQ\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[22\] " "Node \"DRAM_DQ\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[23\] " "Node \"DRAM_DQ\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[24\] " "Node \"DRAM_DQ\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[25\] " "Node \"DRAM_DQ\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[26\] " "Node \"DRAM_DQ\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[27\] " "Node \"DRAM_DQ\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[28\] " "Node \"DRAM_DQ\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[29\] " "Node \"DRAM_DQ\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[2\] " "Node \"DRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[30\] " "Node \"DRAM_DQ\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[31\] " "Node \"DRAM_DQ\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[3\] " "Node \"DRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[4\] " "Node \"DRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[5\] " "Node \"DRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[6\] " "Node \"DRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[7\] " "Node \"DRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[8\] " "Node \"DRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_DQ\[9\] " "Node \"DRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_RAS_N " "Node \"DRAM_RAS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_RAS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "DRAM_WE_N " "Node \"DRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "DRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SCLK " "Node \"EEP_I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EEP_I2C_SDAT " "Node \"EEP_I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EEP_I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_GTX_CLK " "Node \"ENET0_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_MDC " "Node \"ENET0_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_RST_N " "Node \"ENET0_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[0\] " "Node \"ENET0_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[1\] " "Node \"ENET0_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[2\] " "Node \"ENET0_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_DATA\[3\] " "Node \"ENET0_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_EN " "Node \"ENET0_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET0_TX_ER " "Node \"ENET0_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_GTX_CLK " "Node \"ENET1_GTX_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_GTX_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_MDC " "Node \"ENET1_MDC\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_MDC" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_RST_N " "Node \"ENET1_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[0\] " "Node \"ENET1_TX_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[1\] " "Node \"ENET1_TX_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[2\] " "Node \"ENET1_TX_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_DATA\[3\] " "Node \"ENET1_TX_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_EN " "Node \"ENET1_TX_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ENET1_TX_ER " "Node \"ENET1_TX_ER\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_TX_ER" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[0\] " "Node \"EX_IO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[1\] " "Node \"EX_IO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[2\] " "Node \"EX_IO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[3\] " "Node \"EX_IO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[4\] " "Node \"EX_IO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[5\] " "Node \"EX_IO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "EX_IO\[6\] " "Node \"EX_IO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "EX_IO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[0\] " "Node \"FL_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[10\] " "Node \"FL_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[11\] " "Node \"FL_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[12\] " "Node \"FL_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[13\] " "Node \"FL_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[14\] " "Node \"FL_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[15\] " "Node \"FL_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[16\] " "Node \"FL_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[17\] " "Node \"FL_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[18\] " "Node \"FL_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[19\] " "Node \"FL_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[1\] " "Node \"FL_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[20\] " "Node \"FL_ADDR\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[21\] " "Node \"FL_ADDR\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[22\] " "Node \"FL_ADDR\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[2\] " "Node \"FL_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[3\] " "Node \"FL_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[4\] " "Node \"FL_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[5\] " "Node \"FL_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[6\] " "Node \"FL_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[7\] " "Node \"FL_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[8\] " "Node \"FL_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_ADDR\[9\] " "Node \"FL_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_CE_N " "Node \"FL_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[0\] " "Node \"FL_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[1\] " "Node \"FL_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[2\] " "Node \"FL_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[3\] " "Node \"FL_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[4\] " "Node \"FL_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[5\] " "Node \"FL_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[6\] " "Node \"FL_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_DQ\[7\] " "Node \"FL_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_OE_N " "Node \"FL_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_RST_N " "Node \"FL_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WE_N " "Node \"FL_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "FL_WP_N " "Node \"FL_WP_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_WP_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[0\] " "Node \"GPIO\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[10\] " "Node \"GPIO\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[11\] " "Node \"GPIO\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[12\] " "Node \"GPIO\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[13\] " "Node \"GPIO\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[14\] " "Node \"GPIO\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[15\] " "Node \"GPIO\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[16\] " "Node \"GPIO\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[17\] " "Node \"GPIO\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[18\] " "Node \"GPIO\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[19\] " "Node \"GPIO\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[1\] " "Node \"GPIO\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[20\] " "Node \"GPIO\[20\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[20\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[21\] " "Node \"GPIO\[21\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[21\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[22\] " "Node \"GPIO\[22\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[22\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[23\] " "Node \"GPIO\[23\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[23\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[24\] " "Node \"GPIO\[24\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[24\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[25\] " "Node \"GPIO\[25\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[25\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[26\] " "Node \"GPIO\[26\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[26\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[27\] " "Node \"GPIO\[27\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[27\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[28\] " "Node \"GPIO\[28\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[28\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[29\] " "Node \"GPIO\[29\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[29\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[2\] " "Node \"GPIO\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[30\] " "Node \"GPIO\[30\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[30\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[31\] " "Node \"GPIO\[31\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[31\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[32\] " "Node \"GPIO\[32\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[32\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[33\] " "Node \"GPIO\[33\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[33\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[34\] " "Node \"GPIO\[34\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[34\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[35\] " "Node \"GPIO\[35\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[35\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[3\] " "Node \"GPIO\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[4\] " "Node \"GPIO\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[5\] " "Node \"GPIO\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[6\] " "Node \"GPIO\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[7\] " "Node \"GPIO\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[8\] " "Node \"GPIO\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO\[9\] " "Node \"GPIO\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "GPIO\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[0\] " "Node \"HEX0\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[1\] " "Node \"HEX0\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[2\] " "Node \"HEX0\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[3\] " "Node \"HEX0\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[4\] " "Node \"HEX0\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[5\] " "Node \"HEX0\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX0\[6\] " "Node \"HEX0\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[0\] " "Node \"HEX1\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[1\] " "Node \"HEX1\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[2\] " "Node \"HEX1\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[3\] " "Node \"HEX1\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[4\] " "Node \"HEX1\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[5\] " "Node \"HEX1\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX1\[6\] " "Node \"HEX1\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[0\] " "Node \"HEX2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[1\] " "Node \"HEX2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[2\] " "Node \"HEX2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[3\] " "Node \"HEX2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[4\] " "Node \"HEX2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[5\] " "Node \"HEX2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX2\[6\] " "Node \"HEX2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[0\] " "Node \"HEX3\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[1\] " "Node \"HEX3\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[2\] " "Node \"HEX3\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[3\] " "Node \"HEX3\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[4\] " "Node \"HEX3\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[5\] " "Node \"HEX3\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX3\[6\] " "Node \"HEX3\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[0\] " "Node \"HEX4\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[1\] " "Node \"HEX4\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[2\] " "Node \"HEX4\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[3\] " "Node \"HEX4\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[4\] " "Node \"HEX4\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[5\] " "Node \"HEX4\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX4\[6\] " "Node \"HEX4\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[0\] " "Node \"HEX5\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[1\] " "Node \"HEX5\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[2\] " "Node \"HEX5\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[3\] " "Node \"HEX5\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[4\] " "Node \"HEX5\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[5\] " "Node \"HEX5\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX5\[6\] " "Node \"HEX5\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[0\] " "Node \"HEX6\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[1\] " "Node \"HEX6\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[2\] " "Node \"HEX6\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[3\] " "Node \"HEX6\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[4\] " "Node \"HEX6\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[5\] " "Node \"HEX6\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX6\[6\] " "Node \"HEX6\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[0\] " "Node \"HEX7\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[1\] " "Node \"HEX7\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[2\] " "Node \"HEX7\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[3\] " "Node \"HEX7\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[4\] " "Node \"HEX7\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[5\] " "Node \"HEX7\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HEX7\[6\] " "Node \"HEX7\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N1 " "Node \"HSMC_CLKIN_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_N2 " "Node \"HSMC_CLKIN_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P1 " "Node \"HSMC_CLKIN_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKIN_P2 " "Node \"HSMC_CLKIN_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT0 " "Node \"HSMC_CLKOUT0\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT0" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N1 " "Node \"HSMC_CLKOUT_N1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_N2 " "Node \"HSMC_CLKOUT_N2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_N2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P1 " "Node \"HSMC_CLKOUT_P1\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P1" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_CLKOUT_P2 " "Node \"HSMC_CLKOUT_P2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKOUT_P2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[0\] " "Node \"HSMC_D\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[1\] " "Node \"HSMC_D\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[2\] " "Node \"HSMC_D\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_D\[3\] " "Node \"HSMC_D\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_D\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[0\] " "Node \"HSMC_RX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[10\] " "Node \"HSMC_RX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[11\] " "Node \"HSMC_RX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[12\] " "Node \"HSMC_RX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[13\] " "Node \"HSMC_RX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[14\] " "Node \"HSMC_RX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[15\] " "Node \"HSMC_RX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[16\] " "Node \"HSMC_RX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[1\] " "Node \"HSMC_RX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[2\] " "Node \"HSMC_RX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[3\] " "Node \"HSMC_RX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[4\] " "Node \"HSMC_RX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[5\] " "Node \"HSMC_RX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[6\] " "Node \"HSMC_RX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[7\] " "Node \"HSMC_RX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[8\] " "Node \"HSMC_RX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_N\[9\] " "Node \"HSMC_RX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[0\] " "Node \"HSMC_RX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[10\] " "Node \"HSMC_RX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[11\] " "Node \"HSMC_RX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[12\] " "Node \"HSMC_RX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[13\] " "Node \"HSMC_RX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[14\] " "Node \"HSMC_RX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[15\] " "Node \"HSMC_RX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[16\] " "Node \"HSMC_RX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[1\] " "Node \"HSMC_RX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[2\] " "Node \"HSMC_RX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[3\] " "Node \"HSMC_RX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[4\] " "Node \"HSMC_RX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[5\] " "Node \"HSMC_RX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[6\] " "Node \"HSMC_RX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[7\] " "Node \"HSMC_RX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[8\] " "Node \"HSMC_RX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_RX_D_P\[9\] " "Node \"HSMC_RX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_RX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[0\] " "Node \"HSMC_TX_D_N\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[10\] " "Node \"HSMC_TX_D_N\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[11\] " "Node \"HSMC_TX_D_N\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[12\] " "Node \"HSMC_TX_D_N\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[13\] " "Node \"HSMC_TX_D_N\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[14\] " "Node \"HSMC_TX_D_N\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[15\] " "Node \"HSMC_TX_D_N\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[16\] " "Node \"HSMC_TX_D_N\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[1\] " "Node \"HSMC_TX_D_N\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[2\] " "Node \"HSMC_TX_D_N\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[3\] " "Node \"HSMC_TX_D_N\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[4\] " "Node \"HSMC_TX_D_N\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[5\] " "Node \"HSMC_TX_D_N\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[6\] " "Node \"HSMC_TX_D_N\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[7\] " "Node \"HSMC_TX_D_N\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[8\] " "Node \"HSMC_TX_D_N\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_N\[9\] " "Node \"HSMC_TX_D_N\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_N\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[0\] " "Node \"HSMC_TX_D_P\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[10\] " "Node \"HSMC_TX_D_P\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[11\] " "Node \"HSMC_TX_D_P\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[12\] " "Node \"HSMC_TX_D_P\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[13\] " "Node \"HSMC_TX_D_P\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[14\] " "Node \"HSMC_TX_D_P\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[15\] " "Node \"HSMC_TX_D_P\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[16\] " "Node \"HSMC_TX_D_P\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[1\] " "Node \"HSMC_TX_D_P\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[2\] " "Node \"HSMC_TX_D_P\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[3\] " "Node \"HSMC_TX_D_P\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[4\] " "Node \"HSMC_TX_D_P\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[5\] " "Node \"HSMC_TX_D_P\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[6\] " "Node \"HSMC_TX_D_P\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[7\] " "Node \"HSMC_TX_D_P\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[8\] " "Node \"HSMC_TX_D_P\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "HSMC_TX_D_P\[9\] " "Node \"HSMC_TX_D_P\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_TX_D_P\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_BLON " "Node \"LCD_BLON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[0\] " "Node \"LCD_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[1\] " "Node \"LCD_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[2\] " "Node \"LCD_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[3\] " "Node \"LCD_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[4\] " "Node \"LCD_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[5\] " "Node \"LCD_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[6\] " "Node \"LCD_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_DATA\[7\] " "Node \"LCD_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_EN " "Node \"LCD_EN\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_ON " "Node \"LCD_ON\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RS " "Node \"LCD_RS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LCD_RW " "Node \"LCD_RW\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[1\] " "Node \"LEDG\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[2\] " "Node \"LEDG\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[3\] " "Node \"LEDG\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[4\] " "Node \"LEDG\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[5\] " "Node \"LEDG\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[6\] " "Node \"LEDG\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[7\] " "Node \"LEDG\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDG\[8\] " "Node \"LEDG\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[0\] " "Node \"LEDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[10\] " "Node \"LEDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[11\] " "Node \"LEDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[12\] " "Node \"LEDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[13\] " "Node \"LEDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[14\] " "Node \"LEDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[15\] " "Node \"LEDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[16\] " "Node \"LEDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[17\] " "Node \"LEDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[1\] " "Node \"LEDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[2\] " "Node \"LEDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[3\] " "Node \"LEDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[4\] " "Node \"LEDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[5\] " "Node \"LEDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[6\] " "Node \"LEDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[7\] " "Node \"LEDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[8\] " "Node \"LEDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "LEDR\[9\] " "Node \"LEDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[0\] " "Node \"OTG_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_ADDR\[1\] " "Node \"OTG_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_CS_N " "Node \"OTG_CS_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[0\] " "Node \"OTG_DATA\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[10\] " "Node \"OTG_DATA\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[11\] " "Node \"OTG_DATA\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[12\] " "Node \"OTG_DATA\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[13\] " "Node \"OTG_DATA\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[14\] " "Node \"OTG_DATA\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[15\] " "Node \"OTG_DATA\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[1\] " "Node \"OTG_DATA\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[2\] " "Node \"OTG_DATA\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[3\] " "Node \"OTG_DATA\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[4\] " "Node \"OTG_DATA\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[5\] " "Node \"OTG_DATA\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[6\] " "Node \"OTG_DATA\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[7\] " "Node \"OTG_DATA\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[8\] " "Node \"OTG_DATA\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DATA\[9\] " "Node \"OTG_DATA\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_DREQ\[0\] " "Node \"OTG_DREQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_DREQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RD_N " "Node \"OTG_RD_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_RST_N " "Node \"OTG_RST_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "OTG_WR_N " "Node \"OTG_WR_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK " "Node \"PS2_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_CLK2 " "Node \"PS2_CLK2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_CLK2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT " "Node \"PS2_DAT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "PS2_DAT2 " "Node \"PS2_DAT2\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "PS2_DAT2" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CLK " "Node \"SD_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_CMD " "Node \"SD_CMD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[0\] " "Node \"SD_DAT\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[1\] " "Node \"SD_DAT\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[2\] " "Node \"SD_DAT\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SD_DAT\[3\] " "Node \"SD_DAT\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_DAT\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SMA_CLKOUT " "Node \"SMA_CLKOUT\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKOUT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[0\] " "Node \"SRAM_ADDR\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[10\] " "Node \"SRAM_ADDR\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[11\] " "Node \"SRAM_ADDR\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[12\] " "Node \"SRAM_ADDR\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[13\] " "Node \"SRAM_ADDR\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[14\] " "Node \"SRAM_ADDR\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[15\] " "Node \"SRAM_ADDR\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[16\] " "Node \"SRAM_ADDR\[16\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[16\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[17\] " "Node \"SRAM_ADDR\[17\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[17\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[18\] " "Node \"SRAM_ADDR\[18\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[18\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[19\] " "Node \"SRAM_ADDR\[19\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[19\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[1\] " "Node \"SRAM_ADDR\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[2\] " "Node \"SRAM_ADDR\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[3\] " "Node \"SRAM_ADDR\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[4\] " "Node \"SRAM_ADDR\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[5\] " "Node \"SRAM_ADDR\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[6\] " "Node \"SRAM_ADDR\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[7\] " "Node \"SRAM_ADDR\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[8\] " "Node \"SRAM_ADDR\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_ADDR\[9\] " "Node \"SRAM_ADDR\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_ADDR\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_CE_N " "Node \"SRAM_CE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_CE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[0\] " "Node \"SRAM_DQ\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[10\] " "Node \"SRAM_DQ\[10\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[11\] " "Node \"SRAM_DQ\[11\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[12\] " "Node \"SRAM_DQ\[12\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[13\] " "Node \"SRAM_DQ\[13\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[14\] " "Node \"SRAM_DQ\[14\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[15\] " "Node \"SRAM_DQ\[15\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[1\] " "Node \"SRAM_DQ\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[2\] " "Node \"SRAM_DQ\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[3\] " "Node \"SRAM_DQ\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[4\] " "Node \"SRAM_DQ\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[5\] " "Node \"SRAM_DQ\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[6\] " "Node \"SRAM_DQ\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[7\] " "Node \"SRAM_DQ\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[8\] " "Node \"SRAM_DQ\[8\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_DQ\[9\] " "Node \"SRAM_DQ\[9\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_LB_N " "Node \"SRAM_LB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_LB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_OE_N " "Node \"SRAM_OE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_OE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_UB_N " "Node \"SRAM_UB_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_UB_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "SRAM_WE_N " "Node \"SRAM_WE_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SRAM_WE_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "TD_RESET_N " "Node \"TD_RESET_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_RESET_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_CTS " "Node \"UART_CTS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_CTS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "UART_TXD " "Node \"UART_TXD\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_BLANK_N " "Node \"VGA_BLANK_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_BLANK_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[0\] " "Node \"VGA_B\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[1\] " "Node \"VGA_B\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[2\] " "Node \"VGA_B\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[3\] " "Node \"VGA_B\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[4\] " "Node \"VGA_B\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[5\] " "Node \"VGA_B\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[6\] " "Node \"VGA_B\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_B\[7\] " "Node \"VGA_B\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_CLK " "Node \"VGA_CLK\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[0\] " "Node \"VGA_G\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[1\] " "Node \"VGA_G\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[2\] " "Node \"VGA_G\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[3\] " "Node \"VGA_G\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[4\] " "Node \"VGA_G\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[5\] " "Node \"VGA_G\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[6\] " "Node \"VGA_G\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_G\[7\] " "Node \"VGA_G\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_HS " "Node \"VGA_HS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[0\] " "Node \"VGA_R\[0\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[1\] " "Node \"VGA_R\[1\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[2\] " "Node \"VGA_R\[2\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[3\] " "Node \"VGA_R\[3\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[4\] " "Node \"VGA_R\[4\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[5\] " "Node \"VGA_R\[5\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[6\] " "Node \"VGA_R\[6\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_R\[7\] " "Node \"VGA_R\[7\]\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_SYNC_N " "Node \"VGA_SYNC_N\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_SYNC_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "VGA_VS " "Node \"VGA_VS\" is assigned to location or region, but does not exist in design" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Design Software" 0 -1 1678222505774 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1678222505774 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678222505785 ""} +{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1678222505788 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1678222508212 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678222508347 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1678222508393 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1678222508641 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678222508641 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1678222508841 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X104_Y12 X115_Y23 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23" { } { { "loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X104_Y12 to location X115_Y23"} { { 12 { 0 ""} 104 12 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1678222511923 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1678222511923 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1678222512080 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1678222512080 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1678222512080 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678222512081 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.01 " "Total time spent on timing analysis during the Fitter is 0.01 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1678222512176 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678222512185 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678222512399 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1678222512399 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1678222512603 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1678222512913 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1678222513160 ""} +{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "25 Cyclone IV E " "25 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "AUD_ADCDAT 3.3-V LVTTL D2 " "Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D2" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { AUD_ADCDAT } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 15 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK2_50 3.3-V LVTTL AG14 " "Pin CLOCK2_50 uses I/O standard 3.3-V LVTTL at AG14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { CLOCK2_50 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK2_50" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 21 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "CLOCK3_50 3.3-V LVTTL AG15 " "Pin CLOCK3_50 uses I/O standard 3.3-V LVTTL at AG15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { CLOCK3_50 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "CLOCK3_50" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 22 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENET0_LINK100 3.3-V LVTTL C14 " "Pin ENET0_LINK100 uses I/O standard 3.3-V LVTTL at C14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENET0_LINK100 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET0_LINK100" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 89 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENET1_LINK100 3.3-V LVTTL D13 " "Pin ENET1_LINK100 uses I/O standard 3.3-V LVTTL at D13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENET1_LINK100 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENET1_LINK100" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 113 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "ENETCLK_25 3.3-V LVTTL A14 " "Pin ENETCLK_25 uses I/O standard 3.3-V LVTTL at A14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { ENETCLK_25 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "ENETCLK_25" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 135 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "FL_RY 3.3-V LVTTL Y1 " "Pin FL_RY uses I/O standard 3.3-V LVTTL at Y1" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { FL_RY } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "FL_RY" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 180 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "HSMC_CLKIN0 3.3-V LVTTL AH15 " "Pin HSMC_CLKIN0 uses I/O standard 3.3-V LVTTL at AH15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { HSMC_CLKIN0 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "HSMC_CLKIN0" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 284 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "IRDA_RXD 3.3-V LVTTL Y15 " "Pin IRDA_RXD uses I/O standard 3.3-V LVTTL at Y15" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { IRDA_RXD } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "IRDA_RXD" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 373 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "OTG_INT 3.3-V LVTTL D5 " "Pin OTG_INT uses I/O standard 3.3-V LVTTL at D5" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { OTG_INT } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "OTG_INT" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 443 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SD_WP_N 3.3-V LVTTL AF14 " "Pin SD_WP_N uses I/O standard 3.3-V LVTTL at AF14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SD_WP_N } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SD_WP_N" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 458 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SMA_CLKIN 3.3-V LVTTL AH14 " "Pin SMA_CLKIN uses I/O standard 3.3-V LVTTL at AH14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { SMA_CLKIN } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "SMA_CLKIN" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 459 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_CLK27 3.3-V LVTTL B14 " "Pin TD_CLK27 uses I/O standard 3.3-V LVTTL at B14" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_CLK27 } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_CLK27" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 514 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[0\] 3.3-V LVTTL E8 " "Pin TD_DATA\[0\] uses I/O standard 3.3-V LVTTL at E8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[0] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[0\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 516 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[1\] 3.3-V LVTTL A7 " "Pin TD_DATA\[1\] uses I/O standard 3.3-V LVTTL at A7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[1] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[1\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 517 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[2\] 3.3-V LVTTL D8 " "Pin TD_DATA\[2\] uses I/O standard 3.3-V LVTTL at D8" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[2] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[2\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 518 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[3\] 3.3-V LVTTL C7 " "Pin TD_DATA\[3\] uses I/O standard 3.3-V LVTTL at C7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[3] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[3\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 519 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[4\] 3.3-V LVTTL D7 " "Pin TD_DATA\[4\] uses I/O standard 3.3-V LVTTL at D7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[4] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[4\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 520 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[5\] 3.3-V LVTTL D6 " "Pin TD_DATA\[5\] uses I/O standard 3.3-V LVTTL at D6" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[5] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[5\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 521 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[6\] 3.3-V LVTTL E7 " "Pin TD_DATA\[6\] uses I/O standard 3.3-V LVTTL at E7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[6] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[6\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 522 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_DATA\[7\] 3.3-V LVTTL F7 " "Pin TD_DATA\[7\] uses I/O standard 3.3-V LVTTL at F7" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_DATA[7] } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_DATA\[7\]" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 523 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_HS 3.3-V LVTTL E5 " "Pin TD_HS uses I/O standard 3.3-V LVTTL at E5" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_HS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_HS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 524 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TD_VS 3.3-V LVTTL E4 " "Pin TD_VS uses I/O standard 3.3-V LVTTL at E4" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { TD_VS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "TD_VS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 526 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART_RTS 3.3-V LVTTL J13 " "Pin UART_RTS uses I/O standard 3.3-V LVTTL at J13" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { UART_RTS } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RTS" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 528 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART_RXD 3.3-V LVTTL G12 " "Pin UART_RXD uses I/O standard 3.3-V LVTTL at G12" { } { { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/pin_planner.ppl" { UART_RXD } } } { "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/tiagorg/intelFPGA_lite/20.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "UART_RXD" } } } } { "temporary_test_loc" "" { Generic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/" { { 0 { 0 ""} 0 529 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1678222513165 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1678222513165 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg " "Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1678222513214 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 534 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 534 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1157 " "Peak virtual memory: 1157 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678222513382 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:55:13 2023 " "Processing ended: Tue Mar 7 20:55:13 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678222513382 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678222513382 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678222513382 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1678222513382 ""} diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hier_info b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hier_info index 9b4730f..e6791d5 100644 --- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hier_info +++ b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hier_info @@ -1,16 +1,16 @@ |EqCmpDemo -LEDG[0] <= EqCmp4:inst.cmpOut -SW[0] => EqCmp4:inst.input0[0] -SW[1] => EqCmp4:inst.input0[1] -SW[2] => EqCmp4:inst.input0[2] -SW[3] => EqCmp4:inst.input0[3] -SW[4] => EqCmp4:inst.input1[0] -SW[5] => EqCmp4:inst.input1[1] -SW[6] => EqCmp4:inst.input1[2] -SW[7] => EqCmp4:inst.input1[3] +LEDG[0] <= EqCmp4:inst1.cmpOut +SW[0] => EqCmp4:inst1.input0[0] +SW[1] => EqCmp4:inst1.input0[1] +SW[2] => EqCmp4:inst1.input0[2] +SW[3] => EqCmp4:inst1.input0[3] +SW[4] => EqCmp4:inst1.input1[0] +SW[5] => EqCmp4:inst1.input1[1] +SW[6] => EqCmp4:inst1.input1[2] +SW[7] => EqCmp4:inst1.input1[3] -|EqCmpDemo|EqCmp4:inst +|EqCmpDemo|EqCmp4:inst1 cmpOut <= inst.DB_MAX_OUTPUT_PORT_TYPE input0[0] => xnor_0.IN0 input0[1] => xnor_1.IN0 diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hif b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hif index aaa5fe9..a91b9dd 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hif and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.hif differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.html b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.html index e4e8afa..5859494 100644 --- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.html +++ b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.html @@ -16,7 +16,7 @@ Output only Bidir -inst +inst1 8 0 0 diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.rdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.rdb index 4f95f8b..aaaa5a4 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.rdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.rdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.txt b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.txt index a88a48d..b4fb91f 100644 --- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.txt +++ b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.lpc.txt @@ -3,5 +3,5 @@ +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ -; inst ; 8 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst1 ; 8 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.bpm b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.bpm index 9d07719..0b2563e 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.bpm and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.bpm differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.cdb index df9d6b6..232c792 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.cdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.cdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.hdb index 29b086f..0ed1b63 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.hdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.hdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.qmsg b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.qmsg index cd8b8d3..48ae82d 100644 --- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.qmsg +++ b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.qmsg @@ -1,13 +1,14 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678212348006 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678212348007 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 18:05:47 2023 " "Processing started: Tue Mar 7 18:05:47 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678212348007 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678212348007 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678212348007 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678212348170 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678212348170 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EqCmp4.bdf 1 1 " "Found 1 design units, including 1 entities, in source file EqCmp4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EqCmp4 " "Found entity 1: EqCmp4" { } { { "EqCmp4.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678212353697 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678212353697 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EqCmpDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file EqCmpDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EqCmpDemo " "Found entity 1: EqCmpDemo" { } { { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678212353698 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678212353698 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "EqCmpDemo " "Elaborating entity \"EqCmpDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678212353772 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "EqCmp4 EqCmp4:inst " "Elaborating entity \"EqCmp4\" for hierarchy \"EqCmp4:inst\"" { } { { "EqCmpDemo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 176 472 640 272 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678212353784 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678212354268 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678212354636 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678212354636 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "12 " "Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678212354880 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678212354880 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678212354880 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678212354880 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "403 " "Peak virtual memory: 403 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678212354885 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 18:05:54 2023 " "Processing ended: Tue Mar 7 18:05:54 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678212354885 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678212354885 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678212354885 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678212354885 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678222495047 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222495052 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:54:54 2023 " "Processing started: Tue Mar 7 20:54:54 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678222495052 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222495052 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo " "Command: quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222495052 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678222495248 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678222495248 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EqCmp4.bdf 1 1 " "Found 1 design units, including 1 entities, in source file EqCmp4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EqCmp4 " "Found entity 1: EqCmp4" { } { { "EqCmp4.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678222501791 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222501791 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EqCmpDemo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file EqCmpDemo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 EqCmpDemo " "Found entity 1: EqCmpDemo" { } { { "EqCmpDemo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678222501792 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222501792 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "EqCmp8.vhd 2 1 " "Found 2 design units, including 1 entities, in source file EqCmp8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 EqCmp8-Behavioral " "Found design unit 1: EqCmp8-Behavioral" { } { { "EqCmp8.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd" 13 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678222502146 ""} { "Info" "ISGN_ENTITY_NAME" "1 EqCmp8 " "Found entity 1: EqCmp8" { } { { "EqCmp8.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678222502146 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222502146 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "EqCmpDemo " "Elaborating entity \"EqCmpDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678222502196 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "EqCmp4 EqCmp4:inst1 " "Elaborating entity \"EqCmp4\" for hierarchy \"EqCmp4:inst1\"" { } { { "EqCmpDemo.bdf" "inst1" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf" { { 176 472 640 272 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678222502199 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678222502763 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678222503335 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678222503335 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "12 " "Implemented 12 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678222503360 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678222503360 ""} { "Info" "ICUT_CUT_TM_LCELLS" "3 " "Implemented 3 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678222503360 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678222503360 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678222503366 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:55:03 2023 " "Processing ended: Tue Mar 7 20:55:03 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678222503366 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678222503366 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:20 " "Total CPU time (on all processors): 00:00:20" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678222503366 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678222503366 ""} diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.rdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.rdb index 4d1f685..9afbbed 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.rdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map.rdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.cdb index 33f4da6..dbe9fc1 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.cdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.cdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.hdb index 25ddf84..d889edc 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.hdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.map_bb.hdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.pre_map.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.pre_map.hdb index 6147943..674633b 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.pre_map.hdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.pre_map.hdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.quiproj.4510.rdr.flock b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.quiproj.4510.rdr.flock new file mode 100644 index 0000000..e69de29 diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv.hdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv.hdb index 9df47e7..21b96f5 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv.hdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv.hdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv_sg.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv_sg.cdb index 0425e65..9f20d8e 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv_sg.cdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv_sg.cdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv_sg_swap.cdb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv_sg_swap.cdb index b4a15e9..694dfbe 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv_sg_swap.cdb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.rtlv_sg_swap.cdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.smart_action.txt b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.smart_action.txt index c8e8a13..11b531f 100644 --- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.smart_action.txt +++ b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.smart_action.txt @@ -1 +1 @@ -DONE +SOURCE diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta.qmsg b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta.qmsg index 57e290c..c74c8d4 100644 --- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta.qmsg +++ b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.sta.qmsg @@ -1,49 +1,49 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678212366574 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678212366575 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 18:06:06 2023 " "Processing started: Tue Mar 7 18:06:06 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678212366575 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678212366575 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta EqCmpDemo -c EqCmpDemo " "Command: quartus_sta EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678212366575 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678212366599 ""} -{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678212366685 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678212366685 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678212366739 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678212366739 ""} -{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EqCmpDemo.sdc " "Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678212367062 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678212367062 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678212367062 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678212367063 ""} -{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678212367063 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678212367063 ""} -{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678212367063 ""} -{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678212367067 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678212367068 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367069 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367072 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367072 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367073 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367073 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367074 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678212367075 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678212367091 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678212367348 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678212367362 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678212367362 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678212367362 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678212367362 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367363 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367364 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367364 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367364 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367365 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367365 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678212367366 ""} -{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678212367412 ""} -{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678212367412 ""} -{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678212367413 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678212367413 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367414 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367415 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367416 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367416 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678212367417 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678212367647 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678212367648 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678212367658 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 18:06:07 2023 " "Processing ended: Tue Mar 7 18:06:07 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678212367658 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678212367658 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678212367658 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678212367658 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678222517412 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678222517412 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:55:17 2023 " "Processing started: Tue Mar 7 20:55:17 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678222517412 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678222517412 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta EqCmpDemo -c EqCmpDemo " "Command: quartus_sta EqCmpDemo -c EqCmpDemo" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678222517412 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678222517445 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678222517549 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678222517549 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678222517618 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678222517618 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "EqCmpDemo.sdc " "Synopsys Design Constraints File file not found: 'EqCmpDemo.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678222518044 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678222518044 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678222518044 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678222518045 ""} +{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678222518045 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678222518045 ""} +{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678222518045 ""} +{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678222518051 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678222518052 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518052 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518055 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518056 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518056 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518056 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518057 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678222518060 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678222518078 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678222518288 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678222518306 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678222518306 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678222518306 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678222518306 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518306 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518307 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518307 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518308 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518308 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518308 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678222518310 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678222518359 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678222518359 ""} +{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678222518360 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678222518360 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518360 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518361 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518361 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518362 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678222518362 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678222518664 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678222518664 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "534 " "Peak virtual memory: 534 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678222518679 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:55:18 2023 " "Processing ended: Tue Mar 7 20:55:18 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678222518679 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678222518679 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678222518679 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678222518679 ""} diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.fast_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.fast_1200mv_0c.ddb index 7405cb4..7fe17c1 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.fast_1200mv_0c.ddb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.fast_1200mv_0c.ddb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_0c.ddb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_0c.ddb index d4a0934..29483f5 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_0c.ddb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_0c.ddb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_85c.ddb b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_85c.ddb index 6609238..046dbb0 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_85c.ddb and b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tiscmp.slow_1200mv_85c.ddb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tmw_info b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tmw_info index 1bd50f7..6d8f47e 100644 --- a/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tmw_info +++ b/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.tmw_info @@ -1,4 +1,7 @@ -start_full_compilation:s -start_assembler:s-start_full_compilation -start_timing_analyzer:s-start_full_compilation -start_eda_netlist_writer:s-start_full_compilation +start_full_compilation:s:00:00:25 +start_analysis_synthesis:s:00:00:09-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:10-start_full_compilation +start_assembler:s:00:00:03-start_full_compilation +start_timing_analyzer:s:00:00:02-start_full_compilation +start_eda_netlist_writer:s:00:00:01-start_full_compilation diff --git a/1ano/2semestre/lsd/pratica01/part4/db/prev_cmp_EqCmpDemo.qmsg b/1ano/2semestre/lsd/pratica01/part4/db/prev_cmp_EqCmpDemo.qmsg new file mode 100644 index 0000000..0a466e3 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/db/prev_cmp_EqCmpDemo.qmsg @@ -0,0 +1,4 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678220103838 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus Prime " "Running Quartus Prime Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678220103838 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:15:03 2023 " "Processing started: Tue Mar 7 20:15:03 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678220103838 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Design Software" 0 -1 1678220103838 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd " "Command: quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo --generate_symbol=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd" { } { } 0 0 "Command: %1!s!" 0 0 "Design Software" 0 -1 1678220103838 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus Prime " "Quartus Prime Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "695 " "Peak virtual memory: 695 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678220104340 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:15:04 2023 " "Processing ended: Tue Mar 7 20:15:04 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678220104340 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678220104340 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678220104340 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Design Software" 0 -1 1678220104340 ""} diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.cdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.cdb index cb9282a..6fc9667 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.cdb and b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.cdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.hdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.hdb index 38e5f65..7667ce2 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.hdb and b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.hdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.rcfdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.rcfdb index e34a14e..c0bf5b7 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.rcfdb and b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.cmp.rcfdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.cdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.cdb index d2e2cd6..9f9bce5 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.cdb and b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.cdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.dpi b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.dpi index 2000773..b916213 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.dpi and b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.dpi differ diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.cdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.cdb index ddcbdc8..4a76b64 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.cdb and b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.cdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.hdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.hdb index 4f3c972..c233428 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.hdb and b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hbdb.hdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hdb index 511b475..bfed99a 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hdb and b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.root_partition.map.hdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.rrp.hdb b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.rrp.hdb index 0335509..b5da8e9 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.rrp.hdb and b/1ano/2semestre/lsd/pratica01/part4/incremental_db/compiled_partitions/EqCmpDemo.rrp.hdb differ diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.asm.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.asm.rpt index 6a30fb0..4188696 100644 --- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.asm.rpt +++ b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.asm.rpt @@ -1,5 +1,5 @@ Assembler report for EqCmpDemo -Tue Mar 7 18:06:05 2023 +Tue Mar 7 20:55:16 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Mar 7 18:06:05 2023 ; +; Assembler Status ; Successful - Tue Mar 7 20:55:16 2023 ; ; Revision Name ; EqCmpDemo ; ; Top-level Entity Name ; EqCmpDemo ; ; Family ; Cyclone IV E ; @@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Tue Mar 7 18:06:03 2023 + Info: Processing started: Tue Mar 7 20:55:13 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 1 warning - Info: Peak virtual memory: 365 megabytes - Info: Processing ended: Tue Mar 7 18:06:05 2023 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:02 + Info: Peak virtual memory: 366 megabytes + Info: Processing ended: Tue Mar 7 20:55:16 2023 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.done b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.done index 90e5cb2..184a80f 100644 --- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.done +++ b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.done @@ -1 +1 @@ -Tue Mar 7 18:06:09 2023 +Tue Mar 7 20:55:19 2023 diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.eda.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.eda.rpt index 6b5518c..0387fc4 100644 --- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.eda.rpt +++ b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.eda.rpt @@ -1,5 +1,5 @@ EDA Netlist Writer report for EqCmpDemo -Tue Mar 7 18:06:08 2023 +Tue Mar 7 20:57:58 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------------------------------------+ ; EDA Netlist Writer Summary ; +---------------------------+---------------------------------------+ -; EDA Netlist Writer Status ; Successful - Tue Mar 7 18:06:08 2023 ; +; EDA Netlist Writer Status ; Successful - Tue Mar 7 20:57:58 2023 ; ; Revision Name ; EqCmpDemo ; ; Top-level Entity Name ; EqCmpDemo ; ; Family ; Cyclone IV E ; @@ -66,13 +66,13 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------------------------------+------------------------+ -+-------------------------------------------------------------------------------------------------------+ -; Simulation Generated Files ; -+-------------------------------------------------------------------------------------------------------+ -; Generated Files ; -+-------------------------------------------------------------------------------------------------------+ -; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.vho ; -+-------------------------------------------------------------------------------------------------------+ ++----------------------------------------------------------------------------------------------------+ +; Simulation Generated Files ; ++----------------------------------------------------------------------------------------------------+ +; Generated Files ; ++----------------------------------------------------------------------------------------------------+ +; /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim//EqCmpDemo.vho ; ++----------------------------------------------------------------------------------------------------+ +-----------------------------+ @@ -81,14 +81,28 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Tue Mar 7 18:06:08 2023 -Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo + Info: Copyright (C) 2020 Intel Corporation. All rights reserved. + Info: Your use of Intel Corporation's design tools, logic functions + Info: and other software and tools, and any partner logic + Info: functions, and any output files from any of the foregoing + Info: (including device programming or simulation files), and any + Info: associated documentation or information are expressly subject + Info: to the terms and conditions of the Intel Program License + Info: Subscription Agreement, the Intel Quartus Prime License Agreement, + Info: the Intel FPGA IP License Agreement, or other applicable license + Info: agreement, including, without limitation, that your use is for + Info: the sole purpose of programming logic devices manufactured by + Info: Intel and sold by Intel or its authorized distributors. Please + Info: refer to the applicable agreement for further details, at + Info: https://fpgasoftware.intel.com/eula. + Info: Processing started: Tue Mar 7 20:57:57 2023 +Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/ EqCmpDemo -c EqCmpDemo Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. -Info (204019): Generated file EqCmpDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/" for EDA simulation tool +Info (204019): Generated file EqCmpDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 614 megabytes - Info: Processing ended: Tue Mar 7 18:06:08 2023 - Info: Elapsed time: 00:00:00 + Info: Peak virtual memory: 613 megabytes + Info: Processing ended: Tue Mar 7 20:57:58 2023 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.rpt index e2e7bed..747b54c 100644 --- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.rpt +++ b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.rpt @@ -1,5 +1,5 @@ Fitter report for EqCmpDemo -Tue Mar 7 18:06:02 2023 +Tue Mar 7 20:55:13 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -64,7 +64,7 @@ https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+---------------------------------------------+ -; Fitter Status ; Successful - Tue Mar 7 18:06:02 2023 ; +; Fitter Status ; Successful - Tue Mar 7 20:55:13 2023 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Revision Name ; EqCmpDemo ; ; Top-level Entity Name ; EqCmpDemo ; @@ -151,12 +151,12 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 8 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.01 ; +; Average used ; 1.00 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processors 2-4 ; 0.2% ; +; Processors 2-4 ; 0.0% ; +----------------------------+-------------+ @@ -2171,14 +2171,14 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------+--------------------------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------+-------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------+-------------+--------------+ -; |EqCmpDemo ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 73 ; 0 ; 3 (0) ; 0 (0) ; 0 (0) ; |EqCmpDemo ; EqCmpDemo ; work ; -; |EqCmp4:inst| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |EqCmpDemo|EqCmp4:inst ; EqCmp4 ; work ; -+----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------------------+-------------+--------------+ ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+ +; |EqCmpDemo ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 73 ; 0 ; 3 (0) ; 0 (0) ; 0 (0) ; |EqCmpDemo ; EqCmpDemo ; work ; +; |EqCmp4:inst1| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |EqCmpDemo|EqCmp4:inst1 ; EqCmp4 ; work ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -2199,28 +2199,28 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------+----------+---------------+---------------+-----------------------+-----+------+ -+---------------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+---------------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+---------------------------+-------------------+---------+ -; SW[4] ; ; ; -; - EqCmp4:inst|inst~0 ; 0 ; 6 ; -; SW[5] ; ; ; -; - EqCmp4:inst|inst~0 ; 0 ; 6 ; -; SW[1] ; ; ; -; - EqCmp4:inst|inst~0 ; 0 ; 6 ; -; SW[0] ; ; ; -; - EqCmp4:inst|inst~0 ; 0 ; 6 ; -; SW[6] ; ; ; -; - EqCmp4:inst|inst~1 ; 0 ; 6 ; -; SW[7] ; ; ; -; - EqCmp4:inst|inst~1 ; 1 ; 6 ; -; SW[3] ; ; ; -; - EqCmp4:inst|inst~1 ; 0 ; 6 ; -; SW[2] ; ; ; -; - EqCmp4:inst|inst~1 ; 0 ; 6 ; -+---------------------------+-------------------+---------+ ++----------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++----------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++----------------------------+-------------------+---------+ +; SW[4] ; ; ; +; - EqCmp4:inst1|inst~0 ; 0 ; 6 ; +; SW[5] ; ; ; +; - EqCmp4:inst1|inst~0 ; 0 ; 6 ; +; SW[1] ; ; ; +; - EqCmp4:inst1|inst~0 ; 0 ; 6 ; +; SW[0] ; ; ; +; - EqCmp4:inst1|inst~0 ; 0 ; 6 ; +; SW[6] ; ; ; +; - EqCmp4:inst1|inst~1 ; 0 ; 6 ; +; SW[7] ; ; ; +; - EqCmp4:inst1|inst~1 ; 1 ; 6 ; +; SW[3] ; ; ; +; - EqCmp4:inst1|inst~1 ; 0 ; 6 ; +; SW[2] ; ; ; +; - EqCmp4:inst1|inst~1 ; 0 ; 6 ; ++----------------------------+-------------------+---------+ +------------------------------------------------+ @@ -3058,7 +3058,7 @@ Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01 +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Warning (169177): 25 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Info (169178): Pin AUD_ADCDAT uses I/O standard 3.3-V LVTTL at D2 @@ -3088,10 +3088,10 @@ Warning (169177): 25 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and Info (169178): Pin UART_RXD uses I/O standard 3.3-V LVTTL at G12 Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 534 warnings - Info: Peak virtual memory: 1155 megabytes - Info: Processing ended: Tue Mar 7 18:06:02 2023 - Info: Elapsed time: 00:00:07 - Info: Total CPU time (on all processors): 00:00:10 + Info: Peak virtual memory: 1157 megabytes + Info: Processing ended: Tue Mar 7 20:55:13 2023 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:15 +----------------------------+ diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.summary b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.summary index 4782e9a..49dc7e3 100644 --- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.summary +++ b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Tue Mar 7 18:06:02 2023 +Fitter Status : Successful - Tue Mar 7 20:55:13 2023 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition Revision Name : EqCmpDemo Top-level Entity Name : EqCmpDemo diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.flow.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.flow.rpt index e3cd9fc..2c4a393 100644 --- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.flow.rpt +++ b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.flow.rpt @@ -1,5 +1,5 @@ Flow report for EqCmpDemo -Tue Mar 7 18:06:08 2023 +Tue Mar 7 20:57:58 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+---------------------------------------------+ -; Flow Status ; Successful - Tue Mar 7 18:06:08 2023 ; +; Flow Status ; Successful - Tue Mar 7 20:57:58 2023 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Revision Name ; EqCmpDemo ; ; Top-level Entity Name ; EqCmpDemo ; @@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/07/2023 18:05:48 ; +; Start date & time ; 03/07/2023 20:54:55 ; ; Main task ; Compilation ; ; Revision Name ; EqCmpDemo ; +-------------------+---------------------+ @@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+ -; COMPILER_SIGNATURE_ID ; 198516037997543.167821234811082 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 2690080394329.167822249510628 ; -- ; -- ; -- ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ; ; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ; @@ -101,12 +101,14 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 399 MB ; 00:00:17 ; -; Fitter ; 00:00:07 ; 1.0 ; 1155 MB ; 00:00:10 ; -; Assembler ; 00:00:02 ; 1.0 ; 365 MB ; 00:00:02 ; -; Timing Analyzer ; 00:00:01 ; 1.0 ; 533 MB ; 00:00:01 ; -; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 614 MB ; 00:00:00 ; -; Total ; 00:00:17 ; -- ; -- ; 00:00:30 ; +; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 433 MB ; 00:00:20 ; +; Fitter ; 00:00:10 ; 1.0 ; 1157 MB ; 00:00:15 ; +; Assembler ; 00:00:03 ; 1.0 ; 366 MB ; 00:00:03 ; +; Timing Analyzer ; 00:00:01 ; 1.0 ; 534 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:00 ; 1.0 ; 612 MB ; 00:00:00 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 609 MB ; 00:00:00 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 613 MB ; 00:00:00 ; +; Total ; 00:00:25 ; -- ; -- ; 00:00:39 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ @@ -120,6 +122,8 @@ https://fpgasoftware.intel.com/eula. ; Assembler ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; ; Timing Analyzer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; ; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; +; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; +; EDA Netlist Writer ; rendlaptop ; Ubuntu 22.04.2 ; 22 ; x86_64 ; +----------------------+------------------+----------------+------------+----------------+ @@ -131,6 +135,8 @@ quartus_fit --read_settings_files=off --write_settings_files=off EqCmpDemo -c Eq quartus_asm --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo quartus_sta EqCmpDemo -c EqCmpDemo quartus_eda --read_settings_files=off --write_settings_files=off EqCmpDemo -c EqCmpDemo +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht +quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/ EqCmpDemo -c EqCmpDemo diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.rpt index fb2cd59..e7e75bd 100644 --- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.rpt +++ b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for EqCmpDemo -Tue Mar 7 18:05:54 2023 +Tue Mar 7 20:55:03 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -43,7 +43,7 @@ https://fpgasoftware.intel.com/eula. +----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Mar 7 18:05:54 2023 ; +; Analysis & Synthesis Status ; Successful - Tue Mar 7 20:55:03 2023 ; ; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ; ; Revision Name ; EqCmpDemo ; ; Top-level Entity Name ; EqCmpDemo ; @@ -172,46 +172,46 @@ https://fpgasoftware.intel.com/eula. +----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------------------------+---------+ -+------------------------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+--------------------+ -; Resource ; Usage ; -+---------------------------------------------+--------------------+ -; Estimated Total logic elements ; 3 ; -; ; ; -; Total combinational functions ; 3 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 2 ; -; -- 3 input functions ; 0 ; -; -- <=2 input functions ; 1 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 3 ; -; -- arithmetic mode ; 0 ; -; ; ; -; Total registers ; 0 ; -; -- Dedicated logic registers ; 0 ; -; -- I/O registers ; 0 ; -; ; ; -; I/O pins ; 9 ; -; ; ; -; Embedded Multiplier 9-bit elements ; 0 ; -; ; ; -; Maximum fan-out node ; EqCmp4:inst|inst~0 ; -; Maximum fan-out ; 1 ; -; Total fan-out ; 20 ; -; Average fan-out ; 0.95 ; -+---------------------------------------------+--------------------+ ++-------------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+---------------------+ +; Resource ; Usage ; ++---------------------------------------------+---------------------+ +; Estimated Total logic elements ; 3 ; +; ; ; +; Total combinational functions ; 3 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 2 ; +; -- 3 input functions ; 0 ; +; -- <=2 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 3 ; +; -- arithmetic mode ; 0 ; +; ; ; +; Total registers ; 0 ; +; -- Dedicated logic registers ; 0 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 9 ; +; ; ; +; Embedded Multiplier 9-bit elements ; 0 ; +; ; ; +; Maximum fan-out node ; EqCmp4:inst1|inst~0 ; +; Maximum fan-out ; 1 ; +; Total fan-out ; 20 ; +; Average fan-out ; 0.95 ; ++---------------------------------------------+---------------------+ -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------+-------------+--------------+ -; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; -+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------+-------------+--------------+ -; |EqCmpDemo ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; |EqCmpDemo ; EqCmpDemo ; work ; -; |EqCmp4:inst| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |EqCmpDemo|EqCmp4:inst ; EqCmp4 ; work ; -+----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+------------------------+-------------+--------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; ++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+ +; |EqCmpDemo ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 9 ; 0 ; |EqCmpDemo ; EqCmpDemo ; work ; +; |EqCmp4:inst1| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |EqCmpDemo|EqCmp4:inst1 ; EqCmp4 ; work ; ++----------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-------------------------+-------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. @@ -261,7 +261,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Tue Mar 7 18:05:47 2023 + Info: Processing started: Tue Mar 7 20:54:54 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EqCmpDemo -c EqCmpDemo Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected @@ -269,8 +269,11 @@ Info (12021): Found 1 design units, including 1 entities, in source file EqCmp4. Info (12023): Found entity 1: EqCmp4 Info (12021): Found 1 design units, including 1 entities, in source file EqCmpDemo.bdf Info (12023): Found entity 1: EqCmpDemo +Info (12021): Found 2 design units, including 1 entities, in source file EqCmp8.vhd + Info (12022): Found design unit 1: EqCmp8-Behavioral File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd Line: 13 + Info (12023): Found entity 1: EqCmp8 File: /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd Line: 4 Info (12127): Elaborating entity "EqCmpDemo" for the top level hierarchy -Info (12128): Elaborating entity "EqCmp4" for hierarchy "EqCmp4:inst" +Info (12128): Elaborating entity "EqCmp4" for hierarchy "EqCmp4:inst1" Info (286030): Timing-Driven Synthesis is running Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL @@ -279,9 +282,9 @@ Info (21057): Implemented 12 device resources after synthesis - the final resour Info (21059): Implemented 1 output pins Info (21061): Implemented 3 logic cells Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning - Info: Peak virtual memory: 403 megabytes - Info: Processing ended: Tue Mar 7 18:05:54 2023 - Info: Elapsed time: 00:00:07 - Info: Total CPU time (on all processors): 00:00:17 + Info: Peak virtual memory: 433 megabytes + Info: Processing ended: Tue Mar 7 20:55:03 2023 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:20 diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.summary b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.summary index a1a9a52..c58dcd9 100644 --- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.summary +++ b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Tue Mar 7 18:05:54 2023 +Analysis & Synthesis Status : Successful - Tue Mar 7 20:55:03 2023 Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition Revision Name : EqCmpDemo Top-level Entity Name : EqCmpDemo diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sof b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sof index 37c9161..f99b8e7 100644 Binary files a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sof and b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sof differ diff --git a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sta.rpt b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sta.rpt index f763a92..4f64170 100644 --- a/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sta.rpt +++ b/1ano/2semestre/lsd/pratica01/part4/output_files/EqCmpDemo.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for EqCmpDemo -Tue Mar 7 18:06:07 2023 +Tue Mar 7 20:55:18 2023 Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition @@ -457,7 +457,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition - Info: Processing started: Tue Mar 7 18:06:06 2023 + Info: Processing started: Tue Mar 7 20:55:17 2023 Info: Command: quartus_sta EqCmpDemo -c EqCmpDemo Info: qsta_default_script.tcl version: #1 Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. @@ -505,8 +505,8 @@ Info (332140): No Minimum Pulse Width paths to report Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings - Info: Peak virtual memory: 533 megabytes - Info: Processing ended: Tue Mar 7 18:06:07 2023 + Info: Peak virtual memory: 534 megabytes + Info: Processing ended: Tue Mar 7 20:55:18 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.vho b/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.vho index e7b7561..0d06772 100644 --- a/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.vho +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo.vho @@ -17,7 +17,7 @@ -- PROGRAM "Quartus Prime" -- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" --- DATE "03/07/2023 18:06:08" +-- DATE "03/07/2023 20:55:19" -- -- Device: Altera EP4CE115F29C7 Package FBGA780 @@ -294,13 +294,13 @@ SIGNAL \SW[1]~input_o\ : std_logic; SIGNAL \SW[0]~input_o\ : std_logic; SIGNAL \SW[5]~input_o\ : std_logic; SIGNAL \SW[4]~input_o\ : std_logic; -SIGNAL \inst|inst~0_combout\ : std_logic; +SIGNAL \inst1|inst~0_combout\ : std_logic; SIGNAL \SW[7]~input_o\ : std_logic; SIGNAL \SW[6]~input_o\ : std_logic; SIGNAL \SW[3]~input_o\ : std_logic; SIGNAL \SW[2]~input_o\ : std_logic; -SIGNAL \inst|inst~1_combout\ : std_logic; -SIGNAL \inst|inst~combout\ : std_logic; +SIGNAL \inst1|inst~1_combout\ : std_logic; +SIGNAL \inst1|inst~combout\ : std_logic; COMPONENT hard_block PORT ( @@ -330,7 +330,7 @@ GENERIC MAP ( open_drain_output => "false") -- pragma translate_on PORT MAP ( - i => \inst|inst~combout\, + i => \inst1|inst~combout\, devoe => ww_devoe, o => \LEDG[0]~output_o\); @@ -379,9 +379,9 @@ PORT MAP ( o => \SW[4]~input_o\); -- Location: LCCOMB_X114_Y15_N24 -\inst|inst~0\ : cycloneive_lcell_comb +\inst1|inst~0\ : cycloneive_lcell_comb -- Equation(s): --- \inst|inst~0_combout\ = (\SW[1]~input_o\ & (\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\)))) +-- \inst1|inst~0_combout\ = (\SW[1]~input_o\ & (\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\)))) -- pragma translate_off GENERIC MAP ( @@ -393,7 +393,7 @@ PORT MAP ( datab => \SW[0]~input_o\, datac => \SW[5]~input_o\, datad => \SW[4]~input_o\, - combout => \inst|inst~0_combout\); + combout => \inst1|inst~0_combout\); -- Location: IOIBUF_X115_Y15_N1 \SW[7]~input\ : cycloneive_io_ibuf @@ -440,9 +440,9 @@ PORT MAP ( o => \SW[2]~input_o\); -- Location: LCCOMB_X114_Y15_N10 -\inst|inst~1\ : cycloneive_lcell_comb +\inst1|inst~1\ : cycloneive_lcell_comb -- Equation(s): --- \inst|inst~1_combout\ = (\SW[7]~input_o\ & (\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[7]~input_o\ & (!\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) +-- \inst1|inst~1_combout\ = (\SW[7]~input_o\ & (\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[7]~input_o\ & (!\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) -- pragma translate_off GENERIC MAP ( @@ -454,12 +454,12 @@ PORT MAP ( datab => \SW[6]~input_o\, datac => \SW[3]~input_o\, datad => \SW[2]~input_o\, - combout => \inst|inst~1_combout\); + combout => \inst1|inst~1_combout\); -- Location: LCCOMB_X114_Y15_N28 -\inst|inst\ : cycloneive_lcell_comb +\inst1|inst\ : cycloneive_lcell_comb -- Equation(s): --- \inst|inst~combout\ = (\inst|inst~0_combout\ & \inst|inst~1_combout\) +-- \inst1|inst~combout\ = (\inst1|inst~0_combout\ & \inst1|inst~1_combout\) -- pragma translate_off GENERIC MAP ( @@ -467,9 +467,9 @@ GENERIC MAP ( sum_lutc_input => "datac") -- pragma translate_on PORT MAP ( - datab => \inst|inst~0_combout\, - datad => \inst|inst~1_combout\, - combout => \inst|inst~combout\); + datab => \inst1|inst~0_combout\, + datad => \inst1|inst~1_combout\, + combout => \inst1|inst~combout\); ww_LEDG(0) <= \LEDG[0]~output_o\; END structure; diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo_modelsim.xrf index 75d52c0..c16151c 100644 --- a/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo_modelsim.xrf +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/modelsim/EqCmpDemo_modelsim.xrf @@ -1,6 +1,12 @@ vendor_name = ModelSim source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf +source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd +source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vwf +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cbx.xml design_name = hard_block design_name = EqCmpDemo @@ -9,10 +15,10 @@ instance = comp, \SW[1]~input\, SW[1]~input, EqCmpDemo, 1 instance = comp, \SW[0]~input\, SW[0]~input, EqCmpDemo, 1 instance = comp, \SW[5]~input\, SW[5]~input, EqCmpDemo, 1 instance = comp, \SW[4]~input\, SW[4]~input, EqCmpDemo, 1 -instance = comp, \inst|inst~0\, inst|inst~0, EqCmpDemo, 1 +instance = comp, \inst1|inst~0\, inst1|inst~0, EqCmpDemo, 1 instance = comp, \SW[7]~input\, SW[7]~input, EqCmpDemo, 1 instance = comp, \SW[6]~input\, SW[6]~input, EqCmpDemo, 1 instance = comp, \SW[3]~input\, SW[3]~input, EqCmpDemo, 1 instance = comp, \SW[2]~input\, SW[2]~input, EqCmpDemo, 1 -instance = comp, \inst|inst~1\, inst|inst~1, EqCmpDemo, 1 -instance = comp, \inst|inst\, inst|inst, EqCmpDemo, 1 +instance = comp, \inst1|inst~1\, inst1|inst~1, EqCmpDemo, 1 +instance = comp, \inst1|inst\, inst1|inst, EqCmpDemo, 1 diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht new file mode 100644 index 0000000..904ac82 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht @@ -0,0 +1,143 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- ***************************************************************************** +-- This file contains a Vhdl test bench with test vectors .The test vectors +-- are exported from a vector file in the Quartus Waveform Editor and apply to +-- the top level entity of the current Quartus project .The user can use this +-- testbench to simulate his design using a third-party simulation tool . +-- ***************************************************************************** +-- Generated on "03/07/2023 20:57:57" + +-- Vhdl Test Bench(with test vectors) for design : EqCmpDemo +-- +-- Simulation tool : 3rd Party +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY EqCmpDemo_vhd_vec_tst IS +END EqCmpDemo_vhd_vec_tst; +ARCHITECTURE EqCmpDemo_arch OF EqCmpDemo_vhd_vec_tst IS +-- constants +-- signals +SIGNAL LEDG : STD_LOGIC_VECTOR(0 DOWNTO 0); +SIGNAL SW : STD_LOGIC_VECTOR(7 DOWNTO 0); +COMPONENT EqCmpDemo + PORT ( + LEDG : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + SW : IN STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; +BEGIN + i1 : EqCmpDemo + PORT MAP ( +-- list connections between master ports and signals + LEDG => LEDG, + SW => SW + ); +-- SW[7] +t_prcs_SW_7: PROCESS +BEGIN + SW(7) <= '0'; + WAIT FOR 400000 ps; + SW(7) <= '1'; + WAIT FOR 400000 ps; + SW(7) <= '0'; +WAIT; +END PROCESS t_prcs_SW_7; +-- SW[6] +t_prcs_SW_6: PROCESS +BEGIN + FOR i IN 1 TO 2 + LOOP + SW(6) <= '0'; + WAIT FOR 200000 ps; + SW(6) <= '1'; + WAIT FOR 200000 ps; + END LOOP; + SW(6) <= '0'; +WAIT; +END PROCESS t_prcs_SW_6; +-- SW[5] +t_prcs_SW_5: PROCESS +BEGIN +LOOP + SW(5) <= '0'; + WAIT FOR 100000 ps; + SW(5) <= '1'; + WAIT FOR 100000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_SW_5; +-- SW[4] +t_prcs_SW_4: PROCESS +BEGIN +LOOP + SW(4) <= '0'; + WAIT FOR 50000 ps; + SW(4) <= '1'; + WAIT FOR 50000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_SW_4; +-- SW[3] +t_prcs_SW_3: PROCESS +BEGIN +LOOP + SW(3) <= '0'; + WAIT FOR 25000 ps; + SW(3) <= '1'; + WAIT FOR 25000 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_SW_3; +-- SW[2] +t_prcs_SW_2: PROCESS +BEGIN +LOOP + SW(2) <= '0'; + WAIT FOR 12500 ps; + SW(2) <= '1'; + WAIT FOR 12500 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_SW_2; +-- SW[1] +t_prcs_SW_1: PROCESS +BEGIN +LOOP + SW(1) <= '0'; + WAIT FOR 6250 ps; + SW(1) <= '1'; + WAIT FOR 6250 ps; + IF (NOW >= 1000000 ps) THEN WAIT; END IF; +END LOOP; +END PROCESS t_prcs_SW_1; +-- SW[0] +t_prcs_SW_0: PROCESS +BEGIN + FOR i IN 1 TO 148 + LOOP + SW(0) <= '0'; + WAIT FOR 3375 ps; + SW(0) <= '1'; + WAIT FOR 3375 ps; + END LOOP; + SW(0) <= '0'; +WAIT; +END PROCESS t_prcs_SW_0; +END EqCmpDemo_arch; diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp8.vwf.vht b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp8.vwf.vht new file mode 100644 index 0000000..26a6fbf --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp8.vwf.vht @@ -0,0 +1,3346 @@ +-- Copyright (C) 2020 Intel Corporation. All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- ***************************************************************************** +-- This file contains a Vhdl test bench with test vectors .The test vectors +-- are exported from a vector file in the Quartus Waveform Editor and apply to +-- the top level entity of the current Quartus project .The user can use this +-- testbench to simulate his design using a third-party simulation tool . +-- ***************************************************************************** +-- Generated on "03/07/2023 20:53:51" + +-- Vhdl Test Bench(with test vectors) for design : EqCmpDemo +-- +-- Simulation tool : 3rd Party +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY EqCmpDemo_vhd_vec_tst IS +END EqCmpDemo_vhd_vec_tst; +ARCHITECTURE EqCmpDemo_arch OF EqCmpDemo_vhd_vec_tst IS +-- constants +-- signals +SIGNAL LEDG : STD_LOGIC_VECTOR(0 DOWNTO 0); +SIGNAL SW : STD_LOGIC_VECTOR(15 DOWNTO 0); +COMPONENT EqCmpDemo + PORT ( + LEDG : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + SW : IN STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +BEGIN + i1 : EqCmpDemo + PORT MAP ( +-- list connections between master ports and signals + LEDG => LEDG, + SW => SW + ); +-- SW[15] +t_prcs_SW_15: PROCESS +BEGIN + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 10000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 15000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 30000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 25000 ps; + SW(15) <= '1'; + WAIT FOR 50000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 10000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 10000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 35000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 15000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 10000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 15000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 50000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 25000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 10000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 15000 ps; + SW(15) <= '1'; + WAIT FOR 15000 ps; + SW(15) <= '0'; + WAIT FOR 10000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 10000 ps; + SW(15) <= '1'; + WAIT FOR 15000 ps; + SW(15) <= '0'; + WAIT FOR 20000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 20000 ps; + SW(15) <= '1'; + WAIT FOR 20000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 25000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 20000 ps; + SW(15) <= '0'; + WAIT FOR 10000 ps; + SW(15) <= '1'; + WAIT FOR 15000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 30000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 15000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 35000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 10000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 15000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 10000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 20000 ps; + SW(15) <= '0'; + WAIT FOR 5000 ps; + SW(15) <= '1'; + WAIT FOR 10000 ps; + SW(15) <= '0'; + WAIT FOR 20000 ps; + SW(15) <= '1'; + WAIT FOR 5000 ps; + SW(15) <= '0'; +WAIT; +END PROCESS t_prcs_SW_15; +-- SW[14] +t_prcs_SW_14: PROCESS +BEGIN + SW(14) <= '1'; + WAIT FOR 25000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 15000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 15000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 25000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 15000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 20000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 20000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 15000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 20000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 25000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 30000 ps; + SW(14) <= '1'; + WAIT FOR 25000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 15000 ps; + SW(14) <= '1'; + WAIT FOR 15000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 30000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 20000 ps; + SW(14) <= '0'; + WAIT FOR 15000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 15000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 20000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 20000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 25000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 5000 ps; + SW(14) <= '0'; + WAIT FOR 10000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 5000 ps; + SW(14) <= '1'; + WAIT FOR 10000 ps; + SW(14) <= '0'; + WAIT FOR 15000 ps; + SW(14) <= '1'; +WAIT; +END PROCESS t_prcs_SW_14; +-- SW[13] +t_prcs_SW_13: PROCESS +BEGIN + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 25000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 30000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 20000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 20000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 15000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 20000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 15000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 15000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 10000 ps; + SW(13) <= '0'; + WAIT FOR 15000 ps; + SW(13) <= '1'; + WAIT FOR 10000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 10000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 10000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 20000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 20000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 10000 ps; + SW(13) <= '0'; + WAIT FOR 15000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 10000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 15000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 15000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 10000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 10000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 15000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 10000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 30000 ps; + SW(13) <= '0'; + WAIT FOR 20000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 10000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 20000 ps; + SW(13) <= '0'; + WAIT FOR 15000 ps; + SW(13) <= '1'; + WAIT FOR 40000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; + WAIT FOR 30000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 10000 ps; + SW(13) <= '1'; + WAIT FOR 5000 ps; + SW(13) <= '0'; + WAIT FOR 5000 ps; + SW(13) <= '1'; +WAIT; +END PROCESS t_prcs_SW_13; +-- SW[12] +t_prcs_SW_12: PROCESS +BEGIN + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 25000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 15000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 15000 ps; + SW(12) <= '1'; + WAIT FOR 30000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 20000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 15000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 15000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 15000 ps; + SW(12) <= '1'; + WAIT FOR 15000 ps; + SW(12) <= '0'; + WAIT FOR 15000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 15000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 20000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 15000 ps; + SW(12) <= '0'; + WAIT FOR 25000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 20000 ps; + SW(12) <= '1'; + WAIT FOR 40000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 15000 ps; + SW(12) <= '0'; + WAIT FOR 25000 ps; + SW(12) <= '1'; + WAIT FOR 15000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 25000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 10000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 15000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 15000 ps; + SW(12) <= '0'; + WAIT FOR 5000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; + WAIT FOR 5000 ps; + SW(12) <= '0'; + WAIT FOR 10000 ps; + SW(12) <= '1'; +WAIT; +END PROCESS t_prcs_SW_12; +-- SW[11] +t_prcs_SW_11: PROCESS +BEGIN + SW(11) <= '1'; + WAIT FOR 20000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 20000 ps; + SW(11) <= '0'; + WAIT FOR 15000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 15000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 25000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 15000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 15000 ps; + SW(11) <= '0'; + WAIT FOR 15000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 15000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 35000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 30000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 30000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 20000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 15000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 15000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 30000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 40000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 20000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 15000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 10000 ps; + SW(11) <= '0'; + WAIT FOR 15000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 20000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 10000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; + WAIT FOR 5000 ps; + SW(11) <= '1'; + WAIT FOR 5000 ps; + SW(11) <= '0'; +WAIT; +END PROCESS t_prcs_SW_11; +-- SW[10] +t_prcs_SW_10: PROCESS +BEGIN + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 15000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 15000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 15000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 15000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 20000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 50000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 20000 ps; + SW(10) <= '0'; + WAIT FOR 15000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 15000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 15000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 15000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 15000 ps; + SW(10) <= '1'; + WAIT FOR 25000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 15000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 20000 ps; + SW(10) <= '0'; + WAIT FOR 15000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 20000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 20000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 15000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 25000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 15000 ps; + SW(10) <= '0'; + WAIT FOR 20000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 10000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 20000 ps; + SW(10) <= '0'; + WAIT FOR 20000 ps; + SW(10) <= '1'; + WAIT FOR 10000 ps; + SW(10) <= '0'; + WAIT FOR 5000 ps; + SW(10) <= '1'; + WAIT FOR 5000 ps; + SW(10) <= '0'; + WAIT FOR 15000 ps; + SW(10) <= '1'; +WAIT; +END PROCESS t_prcs_SW_10; +-- SW[9] +t_prcs_SW_9: PROCESS +BEGIN + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 30000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 15000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 15000 ps; + SW(9) <= '1'; + WAIT FOR 45000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 20000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 20000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 25000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 15000 ps; + SW(9) <= '1'; + WAIT FOR 25000 ps; + SW(9) <= '0'; + WAIT FOR 25000 ps; + SW(9) <= '1'; + WAIT FOR 25000 ps; + SW(9) <= '0'; + WAIT FOR 25000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 25000 ps; + SW(9) <= '1'; + WAIT FOR 15000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 15000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 45000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 20000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 15000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 20000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 15000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 25000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 10000 ps; + SW(9) <= '1'; + WAIT FOR 5000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 5000 ps; + SW(9) <= '1'; + WAIT FOR 10000 ps; + SW(9) <= '0'; + WAIT FOR 15000 ps; + SW(9) <= '1'; + WAIT FOR 15000 ps; + SW(9) <= '0'; +WAIT; +END PROCESS t_prcs_SW_9; +-- SW[8] +t_prcs_SW_8: PROCESS +BEGIN + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 15000 ps; + SW(8) <= '0'; + WAIT FOR 15000 ps; + SW(8) <= '1'; + WAIT FOR 15000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; + WAIT FOR 20000 ps; + SW(8) <= '0'; + WAIT FOR 20000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 15000 ps; + SW(8) <= '1'; + WAIT FOR 20000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 15000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 20000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 15000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 20000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 15000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 20000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 15000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 15000 ps; + SW(8) <= '1'; + WAIT FOR 15000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 20000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 25000 ps; + SW(8) <= '1'; + WAIT FOR 20000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 25000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; + WAIT FOR 20000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 10000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 15000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 5000 ps; + SW(8) <= '1'; + WAIT FOR 5000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; + WAIT FOR 25000 ps; + SW(8) <= '0'; + WAIT FOR 10000 ps; + SW(8) <= '1'; +WAIT; +END PROCESS t_prcs_SW_8; +-- SW[7] +t_prcs_SW_7: PROCESS +BEGIN + SW(7) <= '0'; + WAIT FOR 20000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 10000 ps; + SW(7) <= '1'; + WAIT FOR 15000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 15000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 35000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 20000 ps; + SW(7) <= '1'; + WAIT FOR 20000 ps; + SW(7) <= '0'; + WAIT FOR 15000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 15000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 15000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 25000 ps; + SW(7) <= '0'; + WAIT FOR 10000 ps; + SW(7) <= '1'; + WAIT FOR 15000 ps; + SW(7) <= '0'; + WAIT FOR 15000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 20000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 20000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 10000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 15000 ps; + SW(7) <= '1'; + WAIT FOR 20000 ps; + SW(7) <= '0'; + WAIT FOR 15000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 15000 ps; + SW(7) <= '0'; + WAIT FOR 25000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 10000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 20000 ps; + SW(7) <= '1'; + WAIT FOR 15000 ps; + SW(7) <= '0'; + WAIT FOR 25000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 15000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 10000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 15000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 10000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 20000 ps; + SW(7) <= '0'; + WAIT FOR 30000 ps; + SW(7) <= '1'; + WAIT FOR 10000 ps; + SW(7) <= '0'; + WAIT FOR 15000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 15000 ps; + SW(7) <= '0'; + WAIT FOR 5000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 15000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 10000 ps; + SW(7) <= '1'; + WAIT FOR 5000 ps; + SW(7) <= '0'; + WAIT FOR 10000 ps; + SW(7) <= '1'; +WAIT; +END PROCESS t_prcs_SW_7; +-- SW[6] +t_prcs_SW_6: PROCESS +BEGIN + SW(6) <= '0'; + WAIT FOR 20000 ps; + SW(6) <= '1'; + WAIT FOR 20000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 15000 ps; + SW(6) <= '0'; + WAIT FOR 20000 ps; + SW(6) <= '1'; + WAIT FOR 20000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 15000 ps; + SW(6) <= '1'; + WAIT FOR 35000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 20000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 20000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 35000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 25000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 15000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 20000 ps; + SW(6) <= '0'; + WAIT FOR 15000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 25000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 20000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 25000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 15000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 15000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 30000 ps; + SW(6) <= '1'; + WAIT FOR 15000 ps; + SW(6) <= '0'; + WAIT FOR 15000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 15000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 25000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 15000 ps; + SW(6) <= '1'; + WAIT FOR 5000 ps; + SW(6) <= '0'; + WAIT FOR 10000 ps; + SW(6) <= '1'; + WAIT FOR 10000 ps; + SW(6) <= '0'; + WAIT FOR 5000 ps; + SW(6) <= '1'; +WAIT; +END PROCESS t_prcs_SW_6; +-- SW[5] +t_prcs_SW_5: PROCESS +BEGIN + SW(5) <= '1'; + WAIT FOR 20000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 40000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 25000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 20000 ps; + SW(5) <= '0'; + WAIT FOR 30000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 20000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 15000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 15000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 15000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 20000 ps; + SW(5) <= '1'; + WAIT FOR 15000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 20000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 20000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 10000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 15000 ps; + SW(5) <= '0'; + WAIT FOR 15000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 5000 ps; + SW(5) <= '1'; + WAIT FOR 5000 ps; + SW(5) <= '0'; + WAIT FOR 10000 ps; + SW(5) <= '1'; +WAIT; +END PROCESS t_prcs_SW_5; +-- SW[4] +t_prcs_SW_4: PROCESS +BEGIN + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 25000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 25000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 15000 ps; + SW(4) <= '1'; + WAIT FOR 20000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 30000 ps; + SW(4) <= '0'; + WAIT FOR 40000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 15000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 15000 ps; + SW(4) <= '0'; + WAIT FOR 25000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 15000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 25000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 20000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 30000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 15000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 30000 ps; + SW(4) <= '0'; + WAIT FOR 20000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 15000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 15000 ps; + SW(4) <= '1'; + WAIT FOR 15000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 15000 ps; + SW(4) <= '1'; + WAIT FOR 10000 ps; + SW(4) <= '0'; + WAIT FOR 10000 ps; + SW(4) <= '1'; + WAIT FOR 30000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 15000 ps; + SW(4) <= '1'; + WAIT FOR 5000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; + WAIT FOR 15000 ps; + SW(4) <= '0'; + WAIT FOR 5000 ps; + SW(4) <= '1'; +WAIT; +END PROCESS t_prcs_SW_4; +-- SW[3] +t_prcs_SW_3: PROCESS +BEGIN + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 10000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 10000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 10000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 15000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 10000 ps; + SW(3) <= '1'; + WAIT FOR 15000 ps; + SW(3) <= '0'; + WAIT FOR 20000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 10000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 15000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 25000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 15000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 15000 ps; + SW(3) <= '0'; + WAIT FOR 10000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 20000 ps; + SW(3) <= '1'; + WAIT FOR 15000 ps; + SW(3) <= '0'; + WAIT FOR 20000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 15000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 30000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 15000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 20000 ps; + SW(3) <= '0'; + WAIT FOR 25000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 20000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 10000 ps; + SW(3) <= '1'; + WAIT FOR 15000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 40000 ps; + SW(3) <= '0'; + WAIT FOR 15000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 10000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 20000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 10000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 15000 ps; + SW(3) <= '1'; + WAIT FOR 15000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 15000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 5000 ps; + SW(3) <= '0'; + WAIT FOR 35000 ps; + SW(3) <= '1'; + WAIT FOR 15000 ps; + SW(3) <= '0'; + WAIT FOR 5000 ps; + SW(3) <= '1'; + WAIT FOR 10000 ps; + SW(3) <= '0'; +WAIT; +END PROCESS t_prcs_SW_3; +-- SW[2] +t_prcs_SW_2: PROCESS +BEGIN + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 20000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 25000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 10000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 10000 ps; + SW(2) <= '0'; + WAIT FOR 15000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 25000 ps; + SW(2) <= '1'; + WAIT FOR 10000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 25000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 15000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 20000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 20000 ps; + SW(2) <= '1'; + WAIT FOR 20000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 10000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 20000 ps; + SW(2) <= '0'; + WAIT FOR 15000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 35000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 10000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 10000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 10000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 10000 ps; + SW(2) <= '0'; + WAIT FOR 20000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 15000 ps; + SW(2) <= '0'; + WAIT FOR 15000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 20000 ps; + SW(2) <= '1'; + WAIT FOR 30000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 20000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 15000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 10000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 20000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 15000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 15000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 15000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 15000 ps; + SW(2) <= '0'; + WAIT FOR 10000 ps; + SW(2) <= '1'; + WAIT FOR 30000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; + WAIT FOR 5000 ps; + SW(2) <= '1'; + WAIT FOR 5000 ps; + SW(2) <= '0'; +WAIT; +END PROCESS t_prcs_SW_2; +-- SW[1] +t_prcs_SW_1: PROCESS +BEGIN + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 15000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 15000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 15000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 15000 ps; + SW(1) <= '0'; + WAIT FOR 15000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 45000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 15000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 15000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 15000 ps; + SW(1) <= '1'; + WAIT FOR 15000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 15000 ps; + SW(1) <= '1'; + WAIT FOR 25000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 15000 ps; + SW(1) <= '0'; + WAIT FOR 15000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 25000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 25000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 35000 ps; + SW(1) <= '1'; + WAIT FOR 25000 ps; + SW(1) <= '0'; + WAIT FOR 15000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 15000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 20000 ps; + SW(1) <= '1'; + WAIT FOR 20000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 30000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 15000 ps; + SW(1) <= '0'; + WAIT FOR 10000 ps; + SW(1) <= '1'; + WAIT FOR 10000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 5000 ps; + SW(1) <= '0'; + WAIT FOR 5000 ps; + SW(1) <= '1'; + WAIT FOR 30000 ps; + SW(1) <= '0'; +WAIT; +END PROCESS t_prcs_SW_1; +-- SW[0] +t_prcs_SW_0: PROCESS +BEGIN + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 25000 ps; + SW(0) <= '1'; + WAIT FOR 20000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 15000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 25000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 25000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 15000 ps; + SW(0) <= '1'; + WAIT FOR 30000 ps; + SW(0) <= '0'; + WAIT FOR 15000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 35000 ps; + SW(0) <= '1'; + WAIT FOR 35000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 25000 ps; + SW(0) <= '1'; + WAIT FOR 35000 ps; + SW(0) <= '0'; + WAIT FOR 15000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 15000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 15000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 15000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 15000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 25000 ps; + SW(0) <= '1'; + WAIT FOR 15000 ps; + SW(0) <= '0'; + WAIT FOR 20000 ps; + SW(0) <= '1'; + WAIT FOR 15000 ps; + SW(0) <= '0'; + WAIT FOR 15000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 5000 ps; + SW(0) <= '0'; + WAIT FOR 10000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 15000 ps; + SW(0) <= '1'; + WAIT FOR 10000 ps; + SW(0) <= '0'; + WAIT FOR 5000 ps; + SW(0) <= '1'; +WAIT; +END PROCESS t_prcs_SW_0; +END EqCmpDemo_arch; diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.do b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.do new file mode 100644 index 0000000..d3c3e9b --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.do @@ -0,0 +1,17 @@ +onerror {exit -code 1} +vlib work +vcom -work work EqCmpDemo.vho +vcom -work work EqCmp4.vwf.vht +vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst +vcd file -direction EqCmpDemo.msim.vcd +vcd add -internal EqCmpDemo_vhd_vec_tst/* +vcd add -internal EqCmpDemo_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.msim.vcd b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.msim.vcd new file mode 100644 index 0000000..5253dce --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.msim.vcd @@ -0,0 +1,2883 @@ +$comment + File created using the following command: + vcd file EqCmpDemo.msim.vcd -direction +$end +$date + Tue Mar 7 20:57:58 2023 +$end +$version + ModelSim Version 2020.1 +$end +$timescale + 1ps +$end + +$scope module eqcmpdemo_vhd_vec_tst $end +$var wire 1 ! LEDG [0] $end +$var wire 1 " SW [7] $end +$var wire 1 # SW [6] $end +$var wire 1 $ SW [5] $end +$var wire 1 % SW [4] $end +$var wire 1 & SW [3] $end +$var wire 1 ' SW [2] $end +$var wire 1 ( SW [1] $end +$var wire 1 ) SW [0] $end + +$scope module i1 $end +$var wire 1 * gnd $end +$var wire 1 + vcc $end +$var wire 1 , unknown $end +$var wire 1 - devoe $end +$var wire 1 . devclrn $end +$var wire 1 / devpor $end +$var wire 1 0 ww_devoe $end +$var wire 1 1 ww_devclrn $end +$var wire 1 2 ww_devpor $end +$var wire 1 3 ww_LEDG [0] $end +$var wire 1 4 ww_SW [7] $end +$var wire 1 5 ww_SW [6] $end +$var wire 1 6 ww_SW [5] $end +$var wire 1 7 ww_SW [4] $end +$var wire 1 8 ww_SW [3] $end +$var wire 1 9 ww_SW [2] $end +$var wire 1 : ww_SW [1] $end +$var wire 1 ; ww_SW [0] $end +$var wire 1 < \LEDG[0]~output_o\ $end +$var wire 1 = \SW[1]~input_o\ $end +$var wire 1 > \SW[0]~input_o\ $end +$var wire 1 ? \SW[5]~input_o\ $end +$var wire 1 @ \SW[4]~input_o\ $end +$var wire 1 A \inst1|inst~0_combout\ $end +$var wire 1 B \SW[7]~input_o\ $end +$var wire 1 C \SW[6]~input_o\ $end +$var wire 1 D \SW[3]~input_o\ $end +$var wire 1 E \SW[2]~input_o\ $end +$var wire 1 F \inst1|inst~1_combout\ $end +$var wire 1 G \inst1|inst~combout\ $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0* +1+ +x, +1- +1. +1/ +10 +11 +12 +1< +0= +0> +0? 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All rights reserved. +-- Your use of Intel Corporation's design tools, logic functions +-- and other software and tools, and any partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Intel Program License +-- Subscription Agreement, the Intel Quartus Prime License Agreement, +-- the Intel FPGA IP License Agreement, or other applicable license +-- agreement, including, without limitation, that your use is for +-- the sole purpose of programming logic devices manufactured by +-- Intel and sold by Intel or its authorized distributors. Please +-- refer to the applicable agreement for further details, at +-- https://fpgasoftware.intel.com/eula. + +-- VENDOR "Altera" +-- PROGRAM "Quartus Prime" +-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" + +-- DATE "03/07/2023 20:57:58" + +-- +-- Device: Altera EP4CE115F29C7 Package FBGA780 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY hard_block IS + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic + ); +END hard_block; + +-- Design Ports Information +-- AUD_ADCDAT => Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- CLOCK2_50 => Location: PIN_AG14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- CLOCK3_50 => Location: PIN_AG15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- CLOCK_50 => Location: PIN_Y2, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_INT_N => Location: PIN_A21, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_LINK100 => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ENET0_MDIO => Location: PIN_B21, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_CLK => Location: PIN_A15, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_COL => Location: PIN_E15, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_CRS => Location: PIN_D15, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_DATA[0] => Location: PIN_C16, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_DATA[1] => Location: PIN_D16, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_DATA[2] => Location: PIN_D17, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_DATA[3] => Location: PIN_C15, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_DV => Location: PIN_C17, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_RX_ER => Location: PIN_D18, I/O Standard: 2.5 V, Current Strength: Default +-- ENET0_TX_CLK => Location: PIN_B17, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_INT_N => Location: PIN_D24, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_LINK100 => Location: PIN_D13, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ENET1_MDIO => Location: PIN_D25, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_CLK => Location: PIN_B15, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_COL => Location: PIN_B22, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_CRS => Location: PIN_D20, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_DATA[0] => Location: PIN_B23, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_DATA[1] => Location: PIN_C21, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_DATA[2] => Location: PIN_A23, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_DATA[3] => Location: PIN_D21, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_DV => Location: PIN_A22, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_RX_ER => Location: PIN_C24, I/O Standard: 2.5 V, Current Strength: Default +-- ENET1_TX_CLK => Location: PIN_C22, I/O Standard: 2.5 V, Current Strength: Default +-- ENETCLK_25 => Location: PIN_A14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- FL_RY => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- HSMC_CLKIN0 => Location: PIN_AH15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- IRDA_RXD => Location: PIN_Y15, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- KEY[0] => Location: PIN_M23, I/O Standard: 2.5 V, Current Strength: Default +-- KEY[1] => Location: PIN_M21, I/O Standard: 2.5 V, Current Strength: Default +-- KEY[2] => Location: PIN_N21, I/O Standard: 2.5 V, Current Strength: Default +-- KEY[3] => Location: PIN_R24, I/O Standard: 2.5 V, Current Strength: Default +-- OTG_INT => Location: PIN_D5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- SD_WP_N => Location: PIN_AF14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- SMA_CLKIN => Location: PIN_AH14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- SW[10] => Location: PIN_AC24, I/O Standard: 2.5 V, Current Strength: Default +-- SW[11] => Location: PIN_AB24, I/O Standard: 2.5 V, Current Strength: Default +-- SW[12] => Location: PIN_AB23, I/O Standard: 2.5 V, Current Strength: Default +-- SW[13] => Location: PIN_AA24, I/O Standard: 2.5 V, Current Strength: Default +-- SW[14] => Location: PIN_AA23, I/O Standard: 2.5 V, Current Strength: Default +-- SW[15] => Location: PIN_AA22, I/O Standard: 2.5 V, Current Strength: Default +-- SW[16] => Location: PIN_Y24, I/O Standard: 2.5 V, Current Strength: Default +-- SW[17] => Location: PIN_Y23, I/O Standard: 2.5 V, Current Strength: Default +-- SW[8] => Location: PIN_AC25, I/O Standard: 2.5 V, Current Strength: Default +-- SW[9] => Location: PIN_AB25, I/O Standard: 2.5 V, Current Strength: Default +-- TD_CLK27 => Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[0] => Location: PIN_E8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[1] => Location: PIN_A7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[2] => Location: PIN_D8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[3] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[4] => Location: PIN_D7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[5] => Location: PIN_D6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[6] => Location: PIN_E7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_DATA[7] => Location: PIN_F7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_HS => Location: PIN_E5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- TD_VS => Location: PIN_E4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- UART_RTS => Location: PIN_J13, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- UART_RXD => Location: PIN_G12, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ~ALTERA_ASDO_DATA1~ => Location: PIN_F4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_E2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ~ALTERA_DCLK~ => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ~ALTERA_DATA0~ => Location: PIN_N7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- ~ALTERA_nCEO~ => Location: PIN_P28, I/O Standard: 2.5 V, Current Strength: 8mA + + +ARCHITECTURE structure OF hard_block IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL \AUD_ADCDAT~padout\ : std_logic; +SIGNAL \CLOCK2_50~padout\ : std_logic; +SIGNAL \CLOCK3_50~padout\ : std_logic; +SIGNAL \CLOCK_50~padout\ : std_logic; +SIGNAL \ENET0_INT_N~padout\ : std_logic; +SIGNAL \ENET0_LINK100~padout\ : std_logic; +SIGNAL \ENET0_MDIO~padout\ : std_logic; +SIGNAL \ENET0_RX_CLK~padout\ : std_logic; +SIGNAL \ENET0_RX_COL~padout\ : std_logic; +SIGNAL \ENET0_RX_CRS~padout\ : std_logic; +SIGNAL \ENET0_RX_DATA[0]~padout\ : std_logic; +SIGNAL \ENET0_RX_DATA[1]~padout\ : std_logic; +SIGNAL \ENET0_RX_DATA[2]~padout\ : std_logic; +SIGNAL \ENET0_RX_DATA[3]~padout\ : std_logic; +SIGNAL \ENET0_RX_DV~padout\ : std_logic; +SIGNAL \ENET0_RX_ER~padout\ : std_logic; +SIGNAL \ENET0_TX_CLK~padout\ : std_logic; +SIGNAL \ENET1_INT_N~padout\ : std_logic; +SIGNAL \ENET1_LINK100~padout\ : std_logic; +SIGNAL \ENET1_MDIO~padout\ : std_logic; +SIGNAL \ENET1_RX_CLK~padout\ : std_logic; +SIGNAL \ENET1_RX_COL~padout\ : std_logic; +SIGNAL \ENET1_RX_CRS~padout\ : std_logic; +SIGNAL \ENET1_RX_DATA[0]~padout\ : std_logic; +SIGNAL \ENET1_RX_DATA[1]~padout\ : std_logic; +SIGNAL \ENET1_RX_DATA[2]~padout\ : std_logic; +SIGNAL \ENET1_RX_DATA[3]~padout\ : std_logic; +SIGNAL \ENET1_RX_DV~padout\ : std_logic; +SIGNAL \ENET1_RX_ER~padout\ : std_logic; +SIGNAL \ENET1_TX_CLK~padout\ : std_logic; +SIGNAL \ENETCLK_25~padout\ : std_logic; +SIGNAL \FL_RY~padout\ : std_logic; +SIGNAL \HSMC_CLKIN0~padout\ : std_logic; +SIGNAL \IRDA_RXD~padout\ : std_logic; +SIGNAL \KEY[0]~padout\ : std_logic; +SIGNAL \KEY[1]~padout\ : std_logic; +SIGNAL \KEY[2]~padout\ : std_logic; +SIGNAL \KEY[3]~padout\ : std_logic; +SIGNAL \OTG_INT~padout\ : std_logic; +SIGNAL \SD_WP_N~padout\ : std_logic; +SIGNAL \SMA_CLKIN~padout\ : std_logic; +SIGNAL \TD_CLK27~padout\ : std_logic; +SIGNAL \TD_DATA[0]~padout\ : std_logic; +SIGNAL \TD_DATA[1]~padout\ : std_logic; +SIGNAL \TD_DATA[2]~padout\ : std_logic; +SIGNAL \TD_DATA[3]~padout\ : std_logic; +SIGNAL \TD_DATA[4]~padout\ : std_logic; +SIGNAL \TD_DATA[5]~padout\ : std_logic; +SIGNAL \TD_DATA[6]~padout\ : std_logic; +SIGNAL \TD_DATA[7]~padout\ : std_logic; +SIGNAL \TD_HS~padout\ : std_logic; +SIGNAL \TD_VS~padout\ : std_logic; +SIGNAL \UART_RTS~padout\ : std_logic; +SIGNAL \UART_RXD~padout\ : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic; +SIGNAL \~ALTERA_DATA0~~padout\ : std_logic; +SIGNAL \AUD_ADCDAT~ibuf_o\ : std_logic; +SIGNAL \CLOCK2_50~ibuf_o\ : std_logic; +SIGNAL \CLOCK3_50~ibuf_o\ : std_logic; +SIGNAL \CLOCK_50~ibuf_o\ : std_logic; +SIGNAL \ENET0_INT_N~ibuf_o\ : std_logic; +SIGNAL \ENET0_LINK100~ibuf_o\ : std_logic; +SIGNAL \ENET0_MDIO~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_CLK~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_COL~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_CRS~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_DATA[0]~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_DATA[1]~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_DATA[2]~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_DATA[3]~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_DV~ibuf_o\ : std_logic; +SIGNAL \ENET0_RX_ER~ibuf_o\ : std_logic; +SIGNAL \ENET0_TX_CLK~ibuf_o\ : std_logic; +SIGNAL \ENET1_INT_N~ibuf_o\ : std_logic; +SIGNAL \ENET1_LINK100~ibuf_o\ : std_logic; +SIGNAL \ENET1_MDIO~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_CLK~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_COL~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_CRS~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_DATA[0]~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_DATA[1]~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_DATA[2]~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_DATA[3]~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_DV~ibuf_o\ : std_logic; +SIGNAL \ENET1_RX_ER~ibuf_o\ : std_logic; +SIGNAL \ENET1_TX_CLK~ibuf_o\ : std_logic; +SIGNAL \ENETCLK_25~ibuf_o\ : std_logic; +SIGNAL \FL_RY~ibuf_o\ : std_logic; +SIGNAL \HSMC_CLKIN0~ibuf_o\ : std_logic; +SIGNAL \IRDA_RXD~ibuf_o\ : std_logic; +SIGNAL \KEY[0]~ibuf_o\ : std_logic; +SIGNAL \KEY[1]~ibuf_o\ : std_logic; +SIGNAL \KEY[2]~ibuf_o\ : std_logic; +SIGNAL \KEY[3]~ibuf_o\ : std_logic; +SIGNAL \OTG_INT~ibuf_o\ : std_logic; +SIGNAL \SD_WP_N~ibuf_o\ : std_logic; +SIGNAL \SMA_CLKIN~ibuf_o\ : std_logic; +SIGNAL \SW[10]~ibuf_o\ : std_logic; +SIGNAL \SW[11]~ibuf_o\ : std_logic; +SIGNAL \SW[12]~ibuf_o\ : std_logic; +SIGNAL \SW[13]~ibuf_o\ : std_logic; +SIGNAL \SW[14]~ibuf_o\ : std_logic; +SIGNAL \SW[15]~ibuf_o\ : std_logic; +SIGNAL \SW[16]~ibuf_o\ : std_logic; +SIGNAL \SW[17]~ibuf_o\ : std_logic; +SIGNAL \SW[8]~ibuf_o\ : std_logic; +SIGNAL \SW[9]~ibuf_o\ : std_logic; +SIGNAL \TD_CLK27~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[0]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[1]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[2]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[3]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[4]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[5]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[6]~ibuf_o\ : std_logic; +SIGNAL \TD_DATA[7]~ibuf_o\ : std_logic; +SIGNAL \TD_HS~ibuf_o\ : std_logic; +SIGNAL \TD_VS~ibuf_o\ : std_logic; +SIGNAL \UART_RTS~ibuf_o\ : std_logic; +SIGNAL \UART_RXD~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic; +SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic; +SIGNAL SW : std_logic_vector(7 DOWNTO 0); + +BEGIN + +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +END structure; + + +LIBRARY CYCLONEIVE; +LIBRARY IEEE; +USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY EqCmpDemo IS + PORT ( + LEDG : OUT std_logic_vector(0 DOWNTO 0); + SW : IN std_logic_vector(7 DOWNTO 0) + ); +END EqCmpDemo; + +-- Design Ports Information +-- LEDG[0] => Location: PIN_E21, I/O Standard: 2.5 V, Current Strength: Default +-- SW[4] => Location: PIN_AB27, I/O Standard: 2.5 V, Current Strength: Default +-- SW[5] => Location: PIN_AC26, I/O Standard: 2.5 V, Current Strength: Default +-- SW[1] => Location: PIN_AC28, I/O Standard: 2.5 V, Current Strength: Default +-- SW[0] => Location: PIN_AB28, I/O Standard: 2.5 V, Current Strength: Default +-- SW[6] => Location: PIN_AD26, I/O Standard: 2.5 V, Current Strength: Default +-- SW[7] => Location: PIN_AB26, I/O Standard: 2.5 V, Current Strength: Default +-- SW[3] => Location: PIN_AD27, I/O Standard: 2.5 V, Current Strength: Default +-- SW[2] => Location: PIN_AC27, I/O Standard: 2.5 V, Current Strength: Default + + +ARCHITECTURE structure OF EqCmpDemo IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_LEDG : std_logic_vector(0 DOWNTO 0); +SIGNAL ww_SW : std_logic_vector(7 DOWNTO 0); +SIGNAL \LEDG[0]~output_o\ : std_logic; +SIGNAL \SW[1]~input_o\ : std_logic; +SIGNAL \SW[0]~input_o\ : std_logic; +SIGNAL \SW[5]~input_o\ : std_logic; +SIGNAL \SW[4]~input_o\ : std_logic; +SIGNAL \inst1|inst~0_combout\ : std_logic; +SIGNAL \SW[7]~input_o\ : std_logic; +SIGNAL \SW[6]~input_o\ : std_logic; +SIGNAL \SW[3]~input_o\ : std_logic; +SIGNAL \SW[2]~input_o\ : std_logic; +SIGNAL \inst1|inst~1_combout\ : std_logic; +SIGNAL \inst1|inst~combout\ : std_logic; + +COMPONENT hard_block + PORT ( + devoe : IN std_logic; + devclrn : IN std_logic; + devpor : IN std_logic); +END COMPONENT; + +BEGIN + +LEDG <= ww_LEDG; +ww_SW <= SW; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; +auto_generated_inst : hard_block +PORT MAP ( + devoe => ww_devoe, + devclrn => ww_devclrn, + devpor => ww_devpor); + +-- Location: IOOBUF_X107_Y73_N9 +\LEDG[0]~output\ : cycloneive_io_obuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + open_drain_output => "false") +-- pragma translate_on +PORT MAP ( + i => \inst1|inst~combout\, + devoe => ww_devoe, + o => \LEDG[0]~output_o\); + +-- Location: IOIBUF_X115_Y14_N1 +\SW[1]~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SW(1), + o => \SW[1]~input_o\); + +-- Location: IOIBUF_X115_Y17_N1 +\SW[0]~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SW(0), + o => \SW[0]~input_o\); + +-- Location: IOIBUF_X115_Y11_N8 +\SW[5]~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SW(5), + o => \SW[5]~input_o\); + +-- Location: IOIBUF_X115_Y18_N8 +\SW[4]~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SW(4), + o => \SW[4]~input_o\); + +-- Location: LCCOMB_X114_Y15_N24 +\inst1|inst~0\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst1|inst~0_combout\ = (\SW[1]~input_o\ & (\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\)))) # (!\SW[1]~input_o\ & (!\SW[5]~input_o\ & (\SW[0]~input_o\ $ (!\SW[4]~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \SW[1]~input_o\, + datab => \SW[0]~input_o\, + datac => \SW[5]~input_o\, + datad => \SW[4]~input_o\, + combout => \inst1|inst~0_combout\); + +-- Location: IOIBUF_X115_Y15_N1 +\SW[7]~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SW(7), + o => \SW[7]~input_o\); + +-- Location: IOIBUF_X115_Y10_N1 +\SW[6]~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SW(6), + o => \SW[6]~input_o\); + +-- Location: IOIBUF_X115_Y13_N8 +\SW[3]~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SW(3), + o => \SW[3]~input_o\); + +-- Location: IOIBUF_X115_Y15_N8 +\SW[2]~input\ : cycloneive_io_ibuf +-- pragma translate_off +GENERIC MAP ( + bus_hold => "false", + simulate_z_as => "z") +-- pragma translate_on +PORT MAP ( + i => ww_SW(2), + o => \SW[2]~input_o\); + +-- Location: LCCOMB_X114_Y15_N10 +\inst1|inst~1\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst1|inst~1_combout\ = (\SW[7]~input_o\ & (\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) # (!\SW[7]~input_o\ & (!\SW[3]~input_o\ & (\SW[6]~input_o\ $ (!\SW[2]~input_o\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \SW[7]~input_o\, + datab => \SW[6]~input_o\, + datac => \SW[3]~input_o\, + datad => \SW[2]~input_o\, + combout => \inst1|inst~1_combout\); + +-- Location: LCCOMB_X114_Y15_N28 +\inst1|inst\ : cycloneive_lcell_comb +-- Equation(s): +-- \inst1|inst~combout\ = (\inst1|inst~0_combout\ & \inst1|inst~1_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100110000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst1|inst~0_combout\, + datad => \inst1|inst~1_combout\, + combout => \inst1|inst~combout\); + +ww_LEDG(0) <= \LEDG[0]~output_o\; +END structure; + + diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205001.sim.vwf b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205001.sim.vwf new file mode 100644 index 0000000..955b9f3 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205001.sim.vwf @@ -0,0 +1,1863 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDG") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDG[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 16; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[15]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[14]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDG") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDG[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[15]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("SW[14]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("SW[13]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("SW[12]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("SW[11]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("SW[10]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; 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+ LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; 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+ LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 1.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[15]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[14]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205136.sim.vwf b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205136.sim.vwf new file mode 100644 index 0000000..955b9f3 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205136.sim.vwf @@ -0,0 +1,1863 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDG") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDG[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 16; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[15]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[14]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDG") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDG[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } + } +} + +TRANSITION_LIST("SW[15]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("SW[14]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("SW[13]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("SW[12]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("SW[11]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; 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+ LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + } + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; + LEVEL 1 FOR 6.25; + LEVEL 0 FOR 6.25; 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+} + +DISPLAY_LINE +{ + CHANNEL = "SW[15]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[14]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205353.sim.vwf b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205353.sim.vwf new file mode 100644 index 0000000..fdfad9c --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205353.sim.vwf @@ -0,0 +1,2252 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDG") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDG[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 16; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[15]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[14]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDG") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDG[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 525.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 395.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 70.0; + } + } +} + +TRANSITION_LIST("SW[15]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 40.0; + } + } +} + +TRANSITION_LIST("SW[14]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + } + } +} + +TRANSITION_LIST("SW[13]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("SW[12]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + } + } +} + +TRANSITION_LIST("SW[11]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 35.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + } + } +} + +TRANSITION_LIST("SW[10]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + } + } +} + +TRANSITION_LIST("SW[9]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 45.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 45.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + } + } +} + +TRANSITION_LIST("SW[8]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 35.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + } + } +} + +TRANSITION_LIST("SW[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 45.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 10.0; + } + } +} + +TRANSITION_LIST("SW[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 35.0; + LEVEL 1 FOR 35.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 35.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 15.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 5.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 15.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "SW"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[15]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[14]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205759.sim.vwf b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205759.sim.vwf new file mode 100644 index 0000000..54f277d --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_20230307205759.sim.vwf @@ -0,0 +1,1053 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("LEDG") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("LEDG[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("SW") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("SW[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +SIGNAL("SW[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "SW"; +} + +TRANSITION_LIST("LEDG") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("LEDG[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 47.25; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 54.0; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 47.25; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 50.5; + LEVEL 1 FOR 0.125; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 2.75; + LEVEL 0 FOR 43.75; + LEVEL 1 FOR 0.75; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 2.125; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 1.875; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 1.0; + LEVEL 0 FOR 43.75; + LEVEL 1 FOR 2.5; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 0.375; + LEVEL 0 FOR 50.25; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 47.25; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 54.0; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 47.25; + LEVEL 1 FOR 3.375; + LEVEL 0 FOR 50.25; + LEVEL 1 FOR 0.375; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 2.5; + LEVEL 0 FOR 43.75; + LEVEL 1 FOR 1.0; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 1.875; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 2.125; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 0.75; + LEVEL 0 FOR 43.75; + LEVEL 1 FOR 2.75; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 0.125; + LEVEL 0 FOR 3.25; + LEVEL 1 FOR 3.0; + LEVEL 0 FOR 43.75; + LEVEL 1 FOR 0.5; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 2.375; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 1.625; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 1.25; + LEVEL 0 FOR 43.75; + LEVEL 1 FOR 2.25; + LEVEL 0 FOR 3.375; + LEVEL 1 FOR 0.625; + LEVEL 0 FOR 37.5; + } + } +} + +TRANSITION_LIST("SW[7]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 400.0; + LEVEL 1 FOR 400.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("SW[6]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 200.0; + } + } +} + +TRANSITION_LIST("SW[5]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 100.0; + } + } +} + +TRANSITION_LIST("SW[4]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 50.0; + } + } +} + +TRANSITION_LIST("SW[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + LEVEL 0 FOR 25.0; + LEVEL 1 FOR 25.0; + } + } +} + +TRANSITION_LIST("SW[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 1; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + LEVEL 1 FOR 12.5; + LEVEL 0 FOR 12.5; + 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COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "SW[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "LEDG[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_modelsim.xrf b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_modelsim.xrf new file mode 100644 index 0000000..c16151c --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo_modelsim.xrf @@ -0,0 +1,24 @@ +vendor_name = ModelSim +source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.bdf +source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmpDemo.bdf +source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vhd +source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp8.vwf +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_b.vhd +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/prmtvs_p.vhd +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_b.vhd +source_file = 1, /home/tiagorg/intelFPGA_lite/20.1/quartus/libraries/vhdl/ieee/timing_p.vhd +source_file = 1, /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/db/EqCmpDemo.cbx.xml +design_name = hard_block +design_name = EqCmpDemo +instance = comp, \LEDG[0]~output\, LEDG[0]~output, EqCmpDemo, 1 +instance = comp, \SW[1]~input\, SW[1]~input, EqCmpDemo, 1 +instance = comp, \SW[0]~input\, SW[0]~input, EqCmpDemo, 1 +instance = comp, \SW[5]~input\, SW[5]~input, EqCmpDemo, 1 +instance = comp, \SW[4]~input\, SW[4]~input, EqCmpDemo, 1 +instance = comp, \inst1|inst~0\, inst1|inst~0, EqCmpDemo, 1 +instance = comp, \SW[7]~input\, SW[7]~input, EqCmpDemo, 1 +instance = comp, \SW[6]~input\, SW[6]~input, EqCmpDemo, 1 +instance = comp, \SW[3]~input\, SW[3]~input, EqCmpDemo, 1 +instance = comp, \SW[2]~input\, SW[2]~input, EqCmpDemo, 1 +instance = comp, \inst1|inst~1\, inst1|inst~1, EqCmpDemo, 1 +instance = comp, \inst1|inst\, inst1|inst, EqCmpDemo, 1 diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/transcript b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/transcript new file mode 100644 index 0000000..3de5311 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/transcript @@ -0,0 +1,47 @@ +# do EqCmpDemo.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 20:57:58 on Mar 07,2023 +# vcom -work work EqCmpDemo.vho +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package VITAL_Timing +# -- Loading package VITAL_Primitives +# -- Loading package cycloneive_atom_pack +# -- Loading package cycloneive_components +# -- Compiling entity hard_block +# -- Compiling architecture structure of hard_block +# -- Compiling entity EqCmpDemo +# -- Compiling architecture structure of EqCmpDemo +# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 20:57:58 on Mar 07,2023 +# vcom -work work EqCmp4.vwf.vht +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling entity EqCmpDemo_vhd_vec_tst +# -- Compiling architecture EqCmpDemo_arch of EqCmpDemo_vhd_vec_tst +# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst +# Start time: 20:57:58 on Mar 07,2023 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading work.eqcmpdemo_vhd_vec_tst(eqcmpdemo_arch) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading cycloneive.cycloneive_atom_pack(body) +# Loading cycloneive.cycloneive_components +# Loading work.eqcmpdemo(structure) +# Loading work.hard_block(structure) +# Loading ieee.std_logic_arith(body) +# Loading cycloneive.cycloneive_io_obuf(arch) +# Loading cycloneive.cycloneive_io_ibuf(arch) +# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb) +# after#33 +# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 diff --git a/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/vwf_sim_transcript b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/vwf_sim_transcript new file mode 100644 index 0000000..ba96e97 --- /dev/null +++ b/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/vwf_sim_transcript @@ -0,0 +1,60 @@ +Determining the location of the ModelSim executable... + +Using: /home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem/ + +To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options +Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. + +**** Generating the ModelSim Testbench **** + +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vht" + +Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 20:57:56 2023Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off EqCmpDemo -c EqCmpDemo --vector_source=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf --testbench_file=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmp4.vwf.vhtWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. +Completed successfully. + +**** Generating the functional simulation netlist **** + +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/" EqCmpDemo -c EqCmpDemo + +Info: *******************************************************************Info: Running Quartus Prime EDA Netlist Writer Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition Info: Copyright (C) 2020 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Tue Mar 7 20:57:57 2023Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/ EqCmpDemo -c EqCmpDemoWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (204019): Generated file EqCmpDemo.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim//" for EDA simulation toolInfo: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 613 megabytes Info: Processing ended: Tue Mar 7 20:57:58 2023 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 +Completed successfully. + +**** Generating the ModelSim .do script **** + +/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.do generated. + +Completed successfully. + +**** Running the ModelSim simulation **** + +/home/tiagorg/intelFPGA_lite/20.1/modelsim_ase/linuxaloem//vsim -c -do EqCmpDemo.do + +Reading pref.tcl +# 2020.1 +# do EqCmpDemo.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 +# Start time: 20:57:58 on Mar 07,2023# vcom -work work EqCmpDemo.vho # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Loading package VITAL_Timing# -- Loading package VITAL_Primitives# -- Loading package cycloneive_atom_pack# -- Loading package cycloneive_components# -- Compiling entity hard_block# -- Compiling architecture structure of hard_block# -- Compiling entity EqCmpDemo# -- Compiling architecture structure of EqCmpDemo# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020# Start time: 20:57:58 on Mar 07,2023# vcom -work work EqCmp4.vwf.vht # -- Loading package STANDARD# -- Loading package TEXTIO# -- Loading package std_logic_1164# -- Compiling entity EqCmpDemo_vhd_vec_tst# -- Compiling architecture EqCmpDemo_arch of EqCmpDemo_vhd_vec_tst +# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0 +# vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.EqCmpDemo_vhd_vec_tst # Start time: 20:57:58 on Mar 07,2023# Loading std.standard# Loading std.textio(body)# Loading ieee.std_logic_1164(body)# Loading work.eqcmpdemo_vhd_vec_tst(eqcmpdemo_arch)# Loading ieee.vital_timing(body)# Loading ieee.vital_primitives(body)# Loading cycloneive.cycloneive_atom_pack(body)# Loading cycloneive.cycloneive_components# Loading work.eqcmpdemo(structure)# Loading work.hard_block(structure)# Loading ieee.std_logic_arith(body)# Loading cycloneive.cycloneive_io_obuf(arch)# Loading cycloneive.cycloneive_io_ibuf(arch)# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb) +# after#33 +# End time: 20:57:58 on Mar 07,2023, Elapsed time: 0:00:00# Errors: 0, Warnings: 0 +Completed successfully. + +**** Converting ModelSim VCD to vector waveform **** + +Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/EqCmp4.vwf... + +Reading /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part4/simulation/qsim/EqCmpDemo.msim.vcd... + +Processing channel transitions... + +Warning: LEDG - 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