Merge pull request #36 from TiagoRG/dev-tiagorg
[LSD] pratica02 part2 added (untested) [LSD] Compiled pratica01 part2 [LSD] Removed unnecessary master.qsf files [LSD] Recreated master.qsf at lsd root
This commit is contained in:
Tiago Garcia
GitHub
commit
7784b275cb
GPG Key ID:
DFCD48E3F420DB42
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@ -39,7 +39,7 @@
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE115F29C7
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set_global_assignment -name TOP_LEVEL_ENTITY AND2Gate
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set_global_assignment -name TOP_LEVEL_ENTITY GateDemo
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:12:52 FEBRUARY 18, 2023"
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set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
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@ -55,8 +55,534 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
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set_global_assignment -name VHDL_FILE AND2Gate.vhd
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_location_assignment PIN_Y2 -to CLOCK_50
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set_location_assignment PIN_AG14 -to CLOCK2_50
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set_location_assignment PIN_AG15 -to CLOCK3_50
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set_location_assignment PIN_AH14 -to SMA_CLKIN
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set_location_assignment PIN_AE23 -to SMA_CLKOUT
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set_location_assignment PIN_M23 -to KEY[0]
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set_location_assignment PIN_M21 -to KEY[1]
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set_location_assignment PIN_N21 -to KEY[2]
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set_location_assignment PIN_R24 -to KEY[3]
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set_location_assignment PIN_AB28 -to SW[0]
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set_location_assignment PIN_AC28 -to SW[1]
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set_location_assignment PIN_AC27 -to SW[2]
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set_location_assignment PIN_AD27 -to SW[3]
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set_location_assignment PIN_AB27 -to SW[4]
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set_location_assignment PIN_AC26 -to SW[5]
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set_location_assignment PIN_AD26 -to SW[6]
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set_location_assignment PIN_AB26 -to SW[7]
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set_location_assignment PIN_AC25 -to SW[8]
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set_location_assignment PIN_AB25 -to SW[9]
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set_location_assignment PIN_AC24 -to SW[10]
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set_location_assignment PIN_AB24 -to SW[11]
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set_location_assignment PIN_AB23 -to SW[12]
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set_location_assignment PIN_AA24 -to SW[13]
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set_location_assignment PIN_AA23 -to SW[14]
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set_location_assignment PIN_AA22 -to SW[15]
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set_location_assignment PIN_Y24 -to SW[16]
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set_location_assignment PIN_Y23 -to SW[17]
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set_location_assignment PIN_G19 -to LEDR[0]
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set_location_assignment PIN_F19 -to LEDR[1]
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set_location_assignment PIN_E19 -to LEDR[2]
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set_location_assignment PIN_F21 -to LEDR[3]
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set_location_assignment PIN_F18 -to LEDR[4]
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set_location_assignment PIN_E18 -to LEDR[5]
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set_location_assignment PIN_J19 -to LEDR[6]
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set_location_assignment PIN_H19 -to LEDR[7]
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set_location_assignment PIN_J17 -to LEDR[8]
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set_location_assignment PIN_G17 -to LEDR[9]
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set_location_assignment PIN_J15 -to LEDR[10]
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set_location_assignment PIN_H16 -to LEDR[11]
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set_location_assignment PIN_J16 -to LEDR[12]
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set_location_assignment PIN_H17 -to LEDR[13]
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set_location_assignment PIN_F15 -to LEDR[14]
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set_location_assignment PIN_G15 -to LEDR[15]
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set_location_assignment PIN_G16 -to LEDR[16]
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set_location_assignment PIN_H15 -to LEDR[17]
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set_location_assignment PIN_E21 -to LEDG[0]
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set_location_assignment PIN_E22 -to LEDG[1]
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set_location_assignment PIN_E25 -to LEDG[2]
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set_location_assignment PIN_E24 -to LEDG[3]
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set_location_assignment PIN_H21 -to LEDG[4]
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set_location_assignment PIN_G20 -to LEDG[5]
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set_location_assignment PIN_G22 -to LEDG[6]
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set_location_assignment PIN_G21 -to LEDG[7]
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set_location_assignment PIN_F17 -to LEDG[8]
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set_location_assignment PIN_G18 -to HEX0[0]
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set_location_assignment PIN_F22 -to HEX0[1]
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set_location_assignment PIN_E17 -to HEX0[2]
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set_location_assignment PIN_L26 -to HEX0[3]
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set_location_assignment PIN_L25 -to HEX0[4]
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set_location_assignment PIN_J22 -to HEX0[5]
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set_location_assignment PIN_H22 -to HEX0[6]
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set_location_assignment PIN_M24 -to HEX1[0]
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set_location_assignment PIN_Y22 -to HEX1[1]
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set_location_assignment PIN_W21 -to HEX1[2]
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set_location_assignment PIN_W22 -to HEX1[3]
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set_location_assignment PIN_W25 -to HEX1[4]
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set_location_assignment PIN_U23 -to HEX1[5]
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set_location_assignment PIN_U24 -to HEX1[6]
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set_location_assignment PIN_AA25 -to HEX2[0]
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set_location_assignment PIN_AA26 -to HEX2[1]
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set_location_assignment PIN_Y25 -to HEX2[2]
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set_location_assignment PIN_W26 -to HEX2[3]
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set_location_assignment PIN_Y26 -to HEX2[4]
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set_location_assignment PIN_W27 -to HEX2[5]
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set_location_assignment PIN_W28 -to HEX2[6]
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set_location_assignment PIN_V21 -to HEX3[0]
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set_location_assignment PIN_U21 -to HEX3[1]
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set_location_assignment PIN_AB20 -to HEX3[2]
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set_location_assignment PIN_AA21 -to HEX3[3]
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set_location_assignment PIN_AD24 -to HEX3[4]
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set_location_assignment PIN_AF23 -to HEX3[5]
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set_location_assignment PIN_Y19 -to HEX3[6]
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set_location_assignment PIN_AB19 -to HEX4[0]
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set_location_assignment PIN_AA19 -to HEX4[1]
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set_location_assignment PIN_AG21 -to HEX4[2]
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set_location_assignment PIN_AH21 -to HEX4[3]
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set_location_assignment PIN_AE19 -to HEX4[4]
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set_location_assignment PIN_AF19 -to HEX4[5]
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set_location_assignment PIN_AE18 -to HEX4[6]
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set_location_assignment PIN_AD18 -to HEX5[0]
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set_location_assignment PIN_AC18 -to HEX5[1]
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set_location_assignment PIN_AB18 -to HEX5[2]
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set_location_assignment PIN_AH19 -to HEX5[3]
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set_location_assignment PIN_AG19 -to HEX5[4]
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set_location_assignment PIN_AF18 -to HEX5[5]
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set_location_assignment PIN_AH18 -to HEX5[6]
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set_location_assignment PIN_AA17 -to HEX6[0]
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set_location_assignment PIN_AB16 -to HEX6[1]
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set_location_assignment PIN_AA16 -to HEX6[2]
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set_location_assignment PIN_AB17 -to HEX6[3]
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set_location_assignment PIN_AB15 -to HEX6[4]
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set_location_assignment PIN_AA15 -to HEX6[5]
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set_location_assignment PIN_AC17 -to HEX6[6]
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set_location_assignment PIN_AD17 -to HEX7[0]
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set_location_assignment PIN_AE17 -to HEX7[1]
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set_location_assignment PIN_AG17 -to HEX7[2]
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set_location_assignment PIN_AH17 -to HEX7[3]
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set_location_assignment PIN_AF17 -to HEX7[4]
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set_location_assignment PIN_AG18 -to HEX7[5]
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set_location_assignment PIN_AA14 -to HEX7[6]
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set_location_assignment PIN_L3 -to LCD_DATA[0]
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set_location_assignment PIN_L1 -to LCD_DATA[1]
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set_location_assignment PIN_L2 -to LCD_DATA[2]
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set_location_assignment PIN_K7 -to LCD_DATA[3]
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set_location_assignment PIN_K1 -to LCD_DATA[4]
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set_location_assignment PIN_K2 -to LCD_DATA[5]
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set_location_assignment PIN_M3 -to LCD_DATA[6]
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set_location_assignment PIN_M5 -to LCD_DATA[7]
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set_location_assignment PIN_L6 -to LCD_BLON
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set_location_assignment PIN_M1 -to LCD_RW
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set_location_assignment PIN_L4 -to LCD_EN
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set_location_assignment PIN_M2 -to LCD_RS
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set_location_assignment PIN_L5 -to LCD_ON
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set_location_assignment PIN_G9 -to UART_TXD
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set_location_assignment PIN_G12 -to UART_RXD
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set_location_assignment PIN_G14 -to UART_CTS
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set_location_assignment PIN_J13 -to UART_RTS
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set_location_assignment PIN_G6 -to PS2_CLK
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set_location_assignment PIN_H5 -to PS2_DAT
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set_location_assignment PIN_G5 -to PS2_CLK2
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set_location_assignment PIN_F5 -to PS2_DAT2
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set_location_assignment PIN_AE13 -to SD_CLK
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set_location_assignment PIN_AD14 -to SD_CMD
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set_location_assignment PIN_AF14 -to SD_WP_N
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set_location_assignment PIN_AE14 -to SD_DAT[0]
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set_location_assignment PIN_AF13 -to SD_DAT[1]
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set_location_assignment PIN_AB14 -to SD_DAT[2]
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set_location_assignment PIN_AC14 -to SD_DAT[3]
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set_location_assignment PIN_G13 -to VGA_HS
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set_location_assignment PIN_C13 -to VGA_VS
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set_location_assignment PIN_C10 -to VGA_SYNC_N
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set_location_assignment PIN_A12 -to VGA_CLK
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set_location_assignment PIN_F11 -to VGA_BLANK_N
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set_location_assignment PIN_E12 -to VGA_R[0]
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set_location_assignment PIN_E11 -to VGA_R[1]
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set_location_assignment PIN_D10 -to VGA_R[2]
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set_location_assignment PIN_F12 -to VGA_R[3]
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set_location_assignment PIN_G10 -to VGA_R[4]
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set_location_assignment PIN_J12 -to VGA_R[5]
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set_location_assignment PIN_H8 -to VGA_R[6]
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set_location_assignment PIN_H10 -to VGA_R[7]
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set_location_assignment PIN_G8 -to VGA_G[0]
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set_location_assignment PIN_G11 -to VGA_G[1]
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set_location_assignment PIN_F8 -to VGA_G[2]
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set_location_assignment PIN_H12 -to VGA_G[3]
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set_location_assignment PIN_C8 -to VGA_G[4]
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set_location_assignment PIN_B8 -to VGA_G[5]
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set_location_assignment PIN_F10 -to VGA_G[6]
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set_location_assignment PIN_C9 -to VGA_G[7]
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set_location_assignment PIN_B10 -to VGA_B[0]
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set_location_assignment PIN_A10 -to VGA_B[1]
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set_location_assignment PIN_C11 -to VGA_B[2]
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set_location_assignment PIN_B11 -to VGA_B[3]
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set_location_assignment PIN_A11 -to VGA_B[4]
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set_location_assignment PIN_C12 -to VGA_B[5]
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set_location_assignment PIN_D11 -to VGA_B[6]
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set_location_assignment PIN_D12 -to VGA_B[7]
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set_location_assignment PIN_C2 -to AUD_ADCLRCK
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set_location_assignment PIN_D2 -to AUD_ADCDAT
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set_location_assignment PIN_E3 -to AUD_DACLRCK
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set_location_assignment PIN_D1 -to AUD_DACDAT
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set_location_assignment PIN_E1 -to AUD_XCK
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set_location_assignment PIN_F2 -to AUD_BCLK
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set_location_assignment PIN_D14 -to EEP_I2C_SCLK
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set_location_assignment PIN_E14 -to EEP_I2C_SDAT
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set_location_assignment PIN_B7 -to I2C_SCLK
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set_location_assignment PIN_A8 -to I2C_SDAT
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set_location_assignment PIN_A14 -to ENETCLK_25
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set_location_assignment PIN_C14 -to ENET0_LINK100
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set_location_assignment PIN_A17 -to ENET0_GTX_CLK
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set_location_assignment PIN_C19 -to ENET0_RST_N
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set_location_assignment PIN_C20 -to ENET0_MDC
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set_location_assignment PIN_B21 -to ENET0_MDIO
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set_location_assignment PIN_A21 -to ENET0_INT_N
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set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
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set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
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set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
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set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
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set_location_assignment PIN_B17 -to ENET0_TX_CLK
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set_location_assignment PIN_A18 -to ENET0_TX_EN
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set_location_assignment PIN_B18 -to ENET0_TX_ER
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set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
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set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
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set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
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set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
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set_location_assignment PIN_A15 -to ENET0_RX_CLK
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set_location_assignment PIN_C17 -to ENET0_RX_DV
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set_location_assignment PIN_D18 -to ENET0_RX_ER
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set_location_assignment PIN_D15 -to ENET0_RX_CRS
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set_location_assignment PIN_E15 -to ENET0_RX_COL
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set_location_assignment PIN_D13 -to ENET1_LINK100
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set_location_assignment PIN_C23 -to ENET1_GTX_CLK
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set_location_assignment PIN_D22 -to ENET1_RST_N
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set_location_assignment PIN_D23 -to ENET1_MDC
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set_location_assignment PIN_D25 -to ENET1_MDIO
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set_location_assignment PIN_D24 -to ENET1_INT_N
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set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
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set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
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set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
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set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
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set_location_assignment PIN_C22 -to ENET1_TX_CLK
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set_location_assignment PIN_B25 -to ENET1_TX_EN
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set_location_assignment PIN_A25 -to ENET1_TX_ER
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set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
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set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
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set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
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set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
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set_location_assignment PIN_B15 -to ENET1_RX_CLK
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set_location_assignment PIN_A22 -to ENET1_RX_DV
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set_location_assignment PIN_C24 -to ENET1_RX_ER
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set_location_assignment PIN_D20 -to ENET1_RX_CRS
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set_location_assignment PIN_B22 -to ENET1_RX_COL
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set_location_assignment PIN_E5 -to TD_HS
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set_location_assignment PIN_E4 -to TD_VS
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set_location_assignment PIN_B14 -to TD_CLK27
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set_location_assignment PIN_G7 -to TD_RESET_N
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set_location_assignment PIN_E8 -to TD_DATA[0]
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set_location_assignment PIN_A7 -to TD_DATA[1]
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set_location_assignment PIN_D8 -to TD_DATA[2]
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set_location_assignment PIN_C7 -to TD_DATA[3]
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set_location_assignment PIN_D7 -to TD_DATA[4]
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set_location_assignment PIN_D6 -to TD_DATA[5]
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set_location_assignment PIN_E7 -to TD_DATA[6]
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set_location_assignment PIN_F7 -to TD_DATA[7]
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set_location_assignment PIN_J6 -to OTG_DATA[0]
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set_location_assignment PIN_K4 -to OTG_DATA[1]
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set_location_assignment PIN_J5 -to OTG_DATA[2]
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set_location_assignment PIN_K3 -to OTG_DATA[3]
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set_location_assignment PIN_J4 -to OTG_DATA[4]
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set_location_assignment PIN_J3 -to OTG_DATA[5]
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set_location_assignment PIN_J7 -to OTG_DATA[6]
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set_location_assignment PIN_H6 -to OTG_DATA[7]
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set_location_assignment PIN_H3 -to OTG_DATA[8]
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set_location_assignment PIN_H4 -to OTG_DATA[9]
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set_location_assignment PIN_G1 -to OTG_DATA[10]
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set_location_assignment PIN_G2 -to OTG_DATA[11]
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set_location_assignment PIN_G3 -to OTG_DATA[12]
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set_location_assignment PIN_F1 -to OTG_DATA[13]
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set_location_assignment PIN_F3 -to OTG_DATA[14]
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||||
set_location_assignment PIN_G4 -to OTG_DATA[15]
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||||
set_location_assignment PIN_H7 -to OTG_ADDR[0]
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||||
set_location_assignment PIN_C3 -to OTG_ADDR[1]
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||||
set_location_assignment PIN_J1 -to OTG_DREQ[0]
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||||
set_location_assignment PIN_A3 -to OTG_CS_N
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||||
set_location_assignment PIN_A4 -to OTG_WR_N
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||||
set_location_assignment PIN_B3 -to OTG_RD_N
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||||
set_location_assignment PIN_D5 -to OTG_INT
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||||
set_location_assignment PIN_C5 -to OTG_RST_N
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set_location_assignment PIN_Y15 -to IRDA_RXD
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||||
set_location_assignment PIN_U7 -to DRAM_BA[0]
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||||
set_location_assignment PIN_R4 -to DRAM_BA[1]
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||||
set_location_assignment PIN_U2 -to DRAM_DQM[0]
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||||
set_location_assignment PIN_W4 -to DRAM_DQM[1]
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||||
set_location_assignment PIN_K8 -to DRAM_DQM[2]
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||||
set_location_assignment PIN_N8 -to DRAM_DQM[3]
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||||
set_location_assignment PIN_U6 -to DRAM_RAS_N
|
||||
set_location_assignment PIN_V7 -to DRAM_CAS_N
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||||
set_location_assignment PIN_AA6 -to DRAM_CKE
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||||
set_location_assignment PIN_AE5 -to DRAM_CLK
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||||
set_location_assignment PIN_V6 -to DRAM_WE_N
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||||
set_location_assignment PIN_T4 -to DRAM_CS_N
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||||
set_location_assignment PIN_W3 -to DRAM_DQ[0]
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||||
set_location_assignment PIN_W2 -to DRAM_DQ[1]
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||||
set_location_assignment PIN_V4 -to DRAM_DQ[2]
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||||
set_location_assignment PIN_W1 -to DRAM_DQ[3]
|
||||
set_location_assignment PIN_V3 -to DRAM_DQ[4]
|
||||
set_location_assignment PIN_V2 -to DRAM_DQ[5]
|
||||
set_location_assignment PIN_V1 -to DRAM_DQ[6]
|
||||
set_location_assignment PIN_U3 -to DRAM_DQ[7]
|
||||
set_location_assignment PIN_Y3 -to DRAM_DQ[8]
|
||||
set_location_assignment PIN_Y4 -to DRAM_DQ[9]
|
||||
set_location_assignment PIN_AB1 -to DRAM_DQ[10]
|
||||
set_location_assignment PIN_AA3 -to DRAM_DQ[11]
|
||||
set_location_assignment PIN_AB2 -to DRAM_DQ[12]
|
||||
set_location_assignment PIN_AC1 -to DRAM_DQ[13]
|
||||
set_location_assignment PIN_AB3 -to DRAM_DQ[14]
|
||||
set_location_assignment PIN_AC2 -to DRAM_DQ[15]
|
||||
set_location_assignment PIN_M8 -to DRAM_DQ[16]
|
||||
set_location_assignment PIN_L8 -to DRAM_DQ[17]
|
||||
set_location_assignment PIN_P2 -to DRAM_DQ[18]
|
||||
set_location_assignment PIN_N3 -to DRAM_DQ[19]
|
||||
set_location_assignment PIN_N4 -to DRAM_DQ[20]
|
||||
set_location_assignment PIN_M4 -to DRAM_DQ[21]
|
||||
set_location_assignment PIN_M7 -to DRAM_DQ[22]
|
||||
set_location_assignment PIN_L7 -to DRAM_DQ[23]
|
||||
set_location_assignment PIN_U5 -to DRAM_DQ[24]
|
||||
set_location_assignment PIN_R7 -to DRAM_DQ[25]
|
||||
set_location_assignment PIN_R1 -to DRAM_DQ[26]
|
||||
set_location_assignment PIN_R2 -to DRAM_DQ[27]
|
||||
set_location_assignment PIN_R3 -to DRAM_DQ[28]
|
||||
set_location_assignment PIN_T3 -to DRAM_DQ[29]
|
||||
set_location_assignment PIN_U4 -to DRAM_DQ[30]
|
||||
set_location_assignment PIN_U1 -to DRAM_DQ[31]
|
||||
set_location_assignment PIN_R6 -to DRAM_ADDR[0]
|
||||
set_location_assignment PIN_V8 -to DRAM_ADDR[1]
|
||||
set_location_assignment PIN_U8 -to DRAM_ADDR[2]
|
||||
set_location_assignment PIN_P1 -to DRAM_ADDR[3]
|
||||
set_location_assignment PIN_V5 -to DRAM_ADDR[4]
|
||||
set_location_assignment PIN_W8 -to DRAM_ADDR[5]
|
||||
set_location_assignment PIN_W7 -to DRAM_ADDR[6]
|
||||
set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
|
||||
set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
|
||||
set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
|
||||
set_location_assignment PIN_R5 -to DRAM_ADDR[10]
|
||||
set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
|
||||
set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
|
||||
set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
|
||||
set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
|
||||
set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
|
||||
set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
|
||||
set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
|
||||
set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
|
||||
set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
|
||||
set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
|
||||
set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
|
||||
set_location_assignment PIN_T7 -to SRAM_ADDR[9]
|
||||
set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
|
||||
set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
|
||||
set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
|
||||
set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
|
||||
set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
|
||||
set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
|
||||
set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
|
||||
set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
|
||||
set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
|
||||
set_location_assignment PIN_T8 -to SRAM_ADDR[19]
|
||||
set_location_assignment PIN_AH3 -to SRAM_DQ[0]
|
||||
set_location_assignment PIN_AF4 -to SRAM_DQ[1]
|
||||
set_location_assignment PIN_AG4 -to SRAM_DQ[2]
|
||||
set_location_assignment PIN_AH4 -to SRAM_DQ[3]
|
||||
set_location_assignment PIN_AF6 -to SRAM_DQ[4]
|
||||
set_location_assignment PIN_AG6 -to SRAM_DQ[5]
|
||||
set_location_assignment PIN_AH6 -to SRAM_DQ[6]
|
||||
set_location_assignment PIN_AF7 -to SRAM_DQ[7]
|
||||
set_location_assignment PIN_AD1 -to SRAM_DQ[8]
|
||||
set_location_assignment PIN_AD2 -to SRAM_DQ[9]
|
||||
set_location_assignment PIN_AE2 -to SRAM_DQ[10]
|
||||
set_location_assignment PIN_AE1 -to SRAM_DQ[11]
|
||||
set_location_assignment PIN_AE3 -to SRAM_DQ[12]
|
||||
set_location_assignment PIN_AE4 -to SRAM_DQ[13]
|
||||
set_location_assignment PIN_AF3 -to SRAM_DQ[14]
|
||||
set_location_assignment PIN_AG3 -to SRAM_DQ[15]
|
||||
set_location_assignment PIN_AC4 -to SRAM_UB_N
|
||||
set_location_assignment PIN_AD4 -to SRAM_LB_N
|
||||
set_location_assignment PIN_AF8 -to SRAM_CE_N
|
||||
set_location_assignment PIN_AD5 -to SRAM_OE_N
|
||||
set_location_assignment PIN_AE8 -to SRAM_WE_N
|
||||
set_location_assignment PIN_AG12 -to FL_ADDR[0]
|
||||
set_location_assignment PIN_AH7 -to FL_ADDR[1]
|
||||
set_location_assignment PIN_Y13 -to FL_ADDR[2]
|
||||
set_location_assignment PIN_Y14 -to FL_ADDR[3]
|
||||
set_location_assignment PIN_Y12 -to FL_ADDR[4]
|
||||
set_location_assignment PIN_AA13 -to FL_ADDR[5]
|
||||
set_location_assignment PIN_AA12 -to FL_ADDR[6]
|
||||
set_location_assignment PIN_AB13 -to FL_ADDR[7]
|
||||
set_location_assignment PIN_AB12 -to FL_ADDR[8]
|
||||
set_location_assignment PIN_AB10 -to FL_ADDR[9]
|
||||
set_location_assignment PIN_AE9 -to FL_ADDR[10]
|
||||
set_location_assignment PIN_AF9 -to FL_ADDR[11]
|
||||
set_location_assignment PIN_AA10 -to FL_ADDR[12]
|
||||
set_location_assignment PIN_AD8 -to FL_ADDR[13]
|
||||
set_location_assignment PIN_AC8 -to FL_ADDR[14]
|
||||
set_location_assignment PIN_Y10 -to FL_ADDR[15]
|
||||
set_location_assignment PIN_AA8 -to FL_ADDR[16]
|
||||
set_location_assignment PIN_AH12 -to FL_ADDR[17]
|
||||
set_location_assignment PIN_AC12 -to FL_ADDR[18]
|
||||
set_location_assignment PIN_AD12 -to FL_ADDR[19]
|
||||
set_location_assignment PIN_AE10 -to FL_ADDR[20]
|
||||
set_location_assignment PIN_AD10 -to FL_ADDR[21]
|
||||
set_location_assignment PIN_AD11 -to FL_ADDR[22]
|
||||
set_location_assignment PIN_AH8 -to FL_DQ[0]
|
||||
set_location_assignment PIN_AF10 -to FL_DQ[1]
|
||||
set_location_assignment PIN_AG10 -to FL_DQ[2]
|
||||
set_location_assignment PIN_AH10 -to FL_DQ[3]
|
||||
set_location_assignment PIN_AF11 -to FL_DQ[4]
|
||||
set_location_assignment PIN_AG11 -to FL_DQ[5]
|
||||
set_location_assignment PIN_AH11 -to FL_DQ[6]
|
||||
set_location_assignment PIN_AF12 -to FL_DQ[7]
|
||||
set_location_assignment PIN_AG7 -to FL_CE_N
|
||||
set_location_assignment PIN_AG8 -to FL_OE_N
|
||||
set_location_assignment PIN_AE11 -to FL_RST_N
|
||||
set_location_assignment PIN_Y1 -to FL_RY
|
||||
set_location_assignment PIN_AC10 -to FL_WE_N
|
||||
set_location_assignment PIN_AE12 -to FL_WP_N
|
||||
set_location_assignment PIN_AB22 -to GPIO[0]
|
||||
set_location_assignment PIN_AC15 -to GPIO[1]
|
||||
set_location_assignment PIN_AB21 -to GPIO[2]
|
||||
set_location_assignment PIN_Y17 -to GPIO[3]
|
||||
set_location_assignment PIN_AC21 -to GPIO[4]
|
||||
set_location_assignment PIN_Y16 -to GPIO[5]
|
||||
set_location_assignment PIN_AD21 -to GPIO[6]
|
||||
set_location_assignment PIN_AE16 -to GPIO[7]
|
||||
set_location_assignment PIN_AD15 -to GPIO[8]
|
||||
set_location_assignment PIN_AE15 -to GPIO[9]
|
||||
set_location_assignment PIN_AC19 -to GPIO[10]
|
||||
set_location_assignment PIN_AF16 -to GPIO[11]
|
||||
set_location_assignment PIN_AD19 -to GPIO[12]
|
||||
set_location_assignment PIN_AF15 -to GPIO[13]
|
||||
set_location_assignment PIN_AF24 -to GPIO[14]
|
||||
set_location_assignment PIN_AE21 -to GPIO[15]
|
||||
set_location_assignment PIN_AF25 -to GPIO[16]
|
||||
set_location_assignment PIN_AC22 -to GPIO[17]
|
||||
set_location_assignment PIN_AE22 -to GPIO[18]
|
||||
set_location_assignment PIN_AF21 -to GPIO[19]
|
||||
set_location_assignment PIN_AF22 -to GPIO[20]
|
||||
set_location_assignment PIN_AD22 -to GPIO[21]
|
||||
set_location_assignment PIN_AG25 -to GPIO[22]
|
||||
set_location_assignment PIN_AD25 -to GPIO[23]
|
||||
set_location_assignment PIN_AH25 -to GPIO[24]
|
||||
set_location_assignment PIN_AE25 -to GPIO[25]
|
||||
set_location_assignment PIN_AG22 -to GPIO[26]
|
||||
set_location_assignment PIN_AE24 -to GPIO[27]
|
||||
set_location_assignment PIN_AH22 -to GPIO[28]
|
||||
set_location_assignment PIN_AF26 -to GPIO[29]
|
||||
set_location_assignment PIN_AE20 -to GPIO[30]
|
||||
set_location_assignment PIN_AG23 -to GPIO[31]
|
||||
set_location_assignment PIN_AF20 -to GPIO[32]
|
||||
set_location_assignment PIN_AH26 -to GPIO[33]
|
||||
set_location_assignment PIN_AH23 -to GPIO[34]
|
||||
set_location_assignment PIN_AG26 -to GPIO[35]
|
||||
set_location_assignment PIN_AH15 -to HSMC_CLKIN0
|
||||
set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
|
||||
set_location_assignment PIN_AE26 -to HSMC_D[0]
|
||||
set_location_assignment PIN_AE28 -to HSMC_D[1]
|
||||
set_location_assignment PIN_AE27 -to HSMC_D[2]
|
||||
set_location_assignment PIN_AF27 -to HSMC_D[3]
|
||||
set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
|
||||
set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
|
||||
set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
|
||||
set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
|
||||
set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
|
||||
set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
|
||||
set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
|
||||
set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
|
||||
set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
|
||||
set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
|
||||
set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
|
||||
set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
|
||||
set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
|
||||
set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
|
||||
set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
|
||||
set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
|
||||
set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
|
||||
set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
|
||||
set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
|
||||
set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
|
||||
set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
|
||||
set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
|
||||
set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
|
||||
set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
|
||||
set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
|
||||
set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
|
||||
set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
|
||||
set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
|
||||
set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
|
||||
set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
|
||||
set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
|
||||
set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
|
||||
set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
|
||||
set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
|
||||
set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
|
||||
set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
|
||||
set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
|
||||
set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
|
||||
set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
|
||||
set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
|
||||
set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
|
||||
set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
|
||||
set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
|
||||
set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
|
||||
set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
|
||||
set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
|
||||
set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
|
||||
set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
|
||||
set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
|
||||
set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
|
||||
set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
|
||||
set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
|
||||
set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
|
||||
set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
|
||||
set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
|
||||
set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
|
||||
set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
|
||||
set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
|
||||
set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
|
||||
set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
|
||||
set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
|
||||
set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
|
||||
set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
|
||||
set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
|
||||
set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
|
||||
set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
|
||||
set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
|
||||
set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
|
||||
set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
|
||||
set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
|
||||
set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
|
||||
set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
|
||||
set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
|
||||
set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
|
||||
set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
|
||||
set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
|
||||
set_location_assignment PIN_J10 -to EX_IO[0]
|
||||
set_location_assignment PIN_J14 -to EX_IO[1]
|
||||
set_location_assignment PIN_H13 -to EX_IO[2]
|
||||
set_location_assignment PIN_H14 -to EX_IO[3]
|
||||
set_location_assignment PIN_F14 -to EX_IO[4]
|
||||
set_location_assignment PIN_E10 -to EX_IO[5]
|
||||
set_location_assignment PIN_D9 -to EX_IO[6]
|
||||
set_global_assignment -name BDF_FILE NAND2Block.bdf
|
||||
set_global_assignment -name VHDL_FILE AND2Gate.vhd
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE AND2Gate.vwf
|
||||
set_global_assignment -name VHDL_FILE GateDemo.vhd
|
||||
set_global_assignment -name VHDL_FILE NOTGate.vhd
|
||||
set_global_assignment -name VHDL_FILE NAND2Gate.vhd
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Binary file not shown.
|
|
@ -1,7 +1,7 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221061486 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221061487 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:31:01 2023 " "Processing started: Tue Mar 7 20:31:01 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221061487 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678221061487 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678221061487 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678221061690 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678221063922 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678221064018 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221064279 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:31:04 2023 " "Processing ended: Tue Mar 7 20:31:04 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221064279 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221064279 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221064279 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678221064279 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678230237613 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678230237614 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 23:03:57 2023 " "Processing started: Tue Mar 7 23:03:57 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678230237614 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678230237614 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678230237614 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678230237753 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678230239241 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678230239304 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678230239490 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 23:03:59 2023 " "Processing ended: Tue Mar 7 23:03:59 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678230239490 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678230239490 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678230239490 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678230239490 ""}
|
||||
|
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Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Version_Index = 520278016
|
||||
Creation_Time = Tue Mar 7 20:19:31 2023
|
||||
Creation_Time = Tue Mar 7 23:03:12 2023
|
||||
|
|
|
|||
|
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@ -1,6 +1,6 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221066801 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221066801 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:31:06 2023 " "Processing started: Tue Mar 7 20:31:06 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221066801 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221066801 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221066801 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678221067030 ""}
|
||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "AND2Gate.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/ simulation " "Generated file AND2Gate.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678221067067 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221067087 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:31:07 2023 " "Processing ended: Tue Mar 7 20:31:07 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221067087 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221067087 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221067087 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678221067087 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678230241841 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678230241842 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 23:04:01 2023 " "Processing started: Tue Mar 7 23:04:01 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678230241842 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678230241842 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678230241842 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678230241997 ""}
|
||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "AND2Gate.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/ simulation " "Generated file AND2Gate.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678230242022 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "612 " "Peak virtual memory: 612 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678230242037 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 23:04:02 2023 " "Processing ended: Tue Mar 7 23:04:02 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678230242037 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678230242037 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678230242037 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678230242037 ""}
|
||||
|
|
|
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|
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221044023 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221044024 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:30:43 2023 " "Processing started: Tue Mar 7 20:30:43 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221044024 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221044024 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221044024 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678221044176 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678221044176 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Block.bdf 1 1 " "Found 1 design units, including 1 entities, in source file NAND2Block.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 NAND2Block " "Found entity 1: NAND2Block" { } { { "NAND2Block.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049524 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049524 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AND2Gate-Behavioral " "Found design unit 1: AND2Gate-Behavioral" { } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049760 ""} { "Info" "ISGN_ENTITY_NAME" "1 AND2Gate " "Found entity 1: AND2Gate" { } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049760 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049760 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file GateDemo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 GateDemo-Shell " "Found design unit 1: GateDemo-Shell" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""} { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049761 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NOTGate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NOTGate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NOTGate-Behavioral " "Found design unit 1: NOTGate-Behavioral" { } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""} { "Info" "ISGN_ENTITY_NAME" "1 NOTGate " "Found entity 1: NOTGate" { } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049761 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NAND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NAND2Gate-Structural " "Found design unit 1: NAND2Gate-Structural" { } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""} { "Info" "ISGN_ENTITY_NAME" "1 NAND2Gate " "Found entity 1: NAND2Gate" { } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678221049761 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049761 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GateDemo " "Elaborating entity \"GateDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678221049794 ""}
|
||||
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[1\] GateDemo.vhd(7) " "Using initial value X (don't care) for net \"LEDR\[1\]\" at GateDemo.vhd(7)" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 7 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221049795 "|GateDemo"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "NAND2Gate NAND2Gate:system_core A:structural " "Elaborating entity \"NAND2Gate\" using architecture \"A:structural\" for hierarchy \"NAND2Gate:system_core\"" { } { { "GateDemo.vhd" "system_core" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 13 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678221049796 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AND2Gate NAND2Gate:system_core\|AND2Gate:and_gate A:behavioral " "Elaborating entity \"AND2Gate\" using architecture \"A:behavioral\" for hierarchy \"NAND2Gate:system_core\|AND2Gate:and_gate\"" { } { { "NAND2Gate.vhd" "and_gate" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 15 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678221049796 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "NOTGate NAND2Gate:system_core\|NOTGate:not_gate A:behavioral " "Elaborating entity \"NOTGate\" using architecture \"A:behavioral\" for hierarchy \"NAND2Gate:system_core\|NOTGate:not_gate\"" { } { { "NAND2Gate.vhd" "not_gate" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 22 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678221049798 ""}
|
||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678221050110 "|GateDemo|LEDR[1]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1678221050110 ""}
|
||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678221050172 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678221050531 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678221050531 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "5 " "Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678221050551 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678221050551 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678221050551 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678221050551 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "432 " "Peak virtual memory: 432 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221050557 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:30:50 2023 " "Processing ended: Tue Mar 7 20:30:50 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221050557 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221050557 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221050557 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678221050557 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678230224767 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678230224767 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 23:03:44 2023 " "Processing started: Tue Mar 7 23:03:44 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678230224767 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230224767 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate " "Command: quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230224767 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678230224894 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678230224894 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Block.bdf 1 1 " "Found 1 design units, including 1 entities, in source file NAND2Block.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 NAND2Block " "Found entity 1: NAND2Block" { } { { "NAND2Block.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Block.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229573 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229573 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file AND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AND2Gate-Behavioral " "Found design unit 1: AND2Gate-Behavioral" { } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd" 15 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229787 ""} { "Info" "ISGN_ENTITY_NAME" "1 AND2Gate " "Found entity 1: AND2Gate" { } { { "AND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/AND2Gate.vhd" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229787 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229787 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "GateDemo.vhd 2 1 " "Found 2 design units, including 1 entities, in source file GateDemo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 GateDemo-Shell " "Found design unit 1: GateDemo-Shell" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} { "Info" "ISGN_ENTITY_NAME" "1 GateDemo " "Found entity 1: GateDemo" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229788 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NOTGate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NOTGate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NOTGate-Behavioral " "Found design unit 1: NOTGate-Behavioral" { } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd" 11 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} { "Info" "ISGN_ENTITY_NAME" "1 NOTGate " "Found entity 1: NOTGate" { } { { "NOTGate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NOTGate.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229788 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "NAND2Gate.vhd 2 1 " "Found 2 design units, including 1 entities, in source file NAND2Gate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NAND2Gate-Structural " "Found design unit 1: NAND2Gate-Structural" { } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 12 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} { "Info" "ISGN_ENTITY_NAME" "1 NAND2Gate " "Found entity 1: NAND2Gate" { } { { "NAND2Gate.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678230229788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229788 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "GateDemo " "Elaborating entity \"GateDemo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678230229819 ""}
|
||||
{ "Warning" "WVRFX_VDB_USING_X_INITIAL_VALUE" "LEDR\[1\] GateDemo.vhd(7) " "Using initial value X (don't care) for net \"LEDR\[1\]\" at GateDemo.vhd(7)" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 7 0 0 } } } 0 10873 "Using initial value X (don't care) for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230229820 "|GateDemo"}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "NAND2Gate NAND2Gate:system_core A:structural " "Elaborating entity \"NAND2Gate\" using architecture \"A:structural\" for hierarchy \"NAND2Gate:system_core\"" { } { { "GateDemo.vhd" "system_core" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 13 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678230229821 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "AND2Gate NAND2Gate:system_core\|AND2Gate:and_gate A:behavioral " "Elaborating entity \"AND2Gate\" using architecture \"A:behavioral\" for hierarchy \"NAND2Gate:system_core\|AND2Gate:and_gate\"" { } { { "NAND2Gate.vhd" "and_gate" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 15 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678230229821 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY_WITH_ARCHITECTURE" "NOTGate NAND2Gate:system_core\|NOTGate:not_gate A:behavioral " "Elaborating entity \"NOTGate\" using architecture \"A:behavioral\" for hierarchy \"NAND2Gate:system_core\|NOTGate:not_gate\"" { } { { "NAND2Gate.vhd" "not_gate" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/NAND2Gate.vhd" 22 0 0 } } } 0 12129 "Elaborating entity \"%1!s!\" using architecture \"%3!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678230229822 ""}
|
||||
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" { } { { "GateDemo.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/GateDemo.vhd" 7 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1678230230102 "|GateDemo|LEDR[1]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1678230230102 ""}
|
||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678230230161 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678230230471 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678230230471 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "5 " "Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Implemented 2 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678230230485 ""} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Implemented 2 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678230230485 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678230230485 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678230230485 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "433 " "Peak virtual memory: 433 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678230230488 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 23:03:50 2023 " "Processing ended: Tue Mar 7 23:03:50 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678230230488 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678230230488 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:13 " "Total CPU time (on all processors): 00:00:13" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678230230488 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678230230488 ""}
|
||||
|
|
|
|||
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|
|
@ -1,49 +1,49 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678221064953 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678221064953 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 20:31:04 2023 " "Processing started: Tue Mar 7 20:31:04 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678221064953 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678221064953 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta VHDLDemo -c AND2Gate " "Command: quartus_sta VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678221064953 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678221064981 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678221065060 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678221065060 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678221065120 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678221065120 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AND2Gate.sdc " "Synopsys Design Constraints File file not found: 'AND2Gate.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678221065549 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678221065550 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678221065550 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678221065551 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678221065551 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678221065551 ""}
|
||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678221065552 ""}
|
||||
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678221065557 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678221065558 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065559 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065561 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065561 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065561 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065562 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065562 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678221065565 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678221065584 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678221065793 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678221065809 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678221065809 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678221065809 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678221065809 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065809 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065810 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065810 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065811 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065811 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065812 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678221065814 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678221065864 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678221065864 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678221065864 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678221065864 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065865 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065865 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065866 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065866 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678221065866 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678221066143 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678221066143 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678221066155 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 20:31:06 2023 " "Processing ended: Tue Mar 7 20:31:06 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678221066155 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678221066155 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678221066155 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678221066155 ""}
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678230239960 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678230239960 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 23:03:59 2023 " "Processing started: Tue Mar 7 23:03:59 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678230239960 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1678230239960 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta VHDLDemo -c AND2Gate " "Command: quartus_sta VHDLDemo -c AND2Gate" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1678230239960 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1678230239981 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1678230240041 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1678230240041 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678230240091 ""}
|
||||
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1678230240091 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "AND2Gate.sdc " "Synopsys Design Constraints File file not found: 'AND2Gate.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1678230240398 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678230240398 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678230240398 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678230240398 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1678230240398 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678230240399 ""}
|
||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1678230240399 ""}
|
||||
{ "Info" "ISTA_NO_CLOCKS_TO_REPORT" "" "No clocks to report" { } { } 0 332159 "No clocks to report" 0 0 "Timing Analyzer" 0 -1 1678230240402 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1678230240402 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240402 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240404 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240405 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240405 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240405 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240405 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678230240407 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1678230240421 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1678230240582 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678230240596 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678230240596 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678230240596 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678230240596 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "fmax " "No fmax paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240597 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240597 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240598 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240598 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240598 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240598 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1678230240600 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1678230240638 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_FOUND_NO_CLOCKS" "" "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." { } { } 0 332096 "The command derive_clocks did not find any clocks to derive. No clocks were created or changed." 0 0 "Timing Analyzer" 0 -1 1678230240639 ""}
|
||||
{ "Warning" "WSTA_NO_CLOCKS_DEFINED" "" "No clocks defined in design." { } { } 0 332068 "No clocks defined in design." 0 0 "Timing Analyzer" 0 -1 1678230240639 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Timing Analyzer" 0 -1 1678230240639 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Setup " "No Setup paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240639 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Hold " "No Hold paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240640 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240640 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240640 ""}
|
||||
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Minimum Pulse Width " "No Minimum Pulse Width paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Timing Analyzer" 0 -1 1678230240641 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678230240845 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1678230240845 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "533 " "Peak virtual memory: 533 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678230240853 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 23:04:00 2023 " "Processing ended: Tue Mar 7 23:04:00 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678230240853 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678230240853 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678230240853 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1678230240853 ""}
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,7 +1,7 @@
|
|||
start_full_compilation:s:00:00:24
|
||||
start_analysis_synthesis:s:00:00:07-start_full_compilation
|
||||
start_full_compilation:s:00:00:18
|
||||
start_analysis_synthesis:s:00:00:06-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:10-start_full_compilation
|
||||
start_assembler:s:00:00:04-start_full_compilation
|
||||
start_fitter:s:00:00:07-start_full_compilation
|
||||
start_assembler:s:00:00:02-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:02-start_full_compilation
|
||||
start_eda_netlist_writer:s:00:00:01-start_full_compilation
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,5 +1,5 @@
|
|||
Assembler report for AND2Gate
|
||||
Tue Mar 7 20:31:04 2023
|
||||
Tue Mar 7 23:03:59 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Tue Mar 7 20:31:04 2023 ;
|
||||
; Assembler Status ; Successful - Tue Mar 7 23:03:59 2023 ;
|
||||
; Revision Name ; AND2Gate ;
|
||||
; Top-level Entity Name ; GateDemo ;
|
||||
; Family ; Cyclone IV E ;
|
||||
|
|
@ -78,15 +78,15 @@ https://fpgasoftware.intel.com/eula.
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Info: Processing started: Tue Mar 7 20:31:01 2023
|
||||
Info: Processing started: Tue Mar 7 23:03:57 2023
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 367 megabytes
|
||||
Info: Processing ended: Tue Mar 7 20:31:04 2023
|
||||
Info: Elapsed time: 00:00:03
|
||||
Info: Total CPU time (on all processors): 00:00:03
|
||||
Info: Processing ended: Tue Mar 7 23:03:59 2023
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Tue Mar 7 20:31:07 2023
|
||||
Tue Mar 7 23:04:02 2023
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
EDA Netlist Writer report for AND2Gate
|
||||
Tue Mar 7 20:31:07 2023
|
||||
Tue Mar 7 23:04:02 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -37,7 +37,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------------------------------------------------------+
|
||||
; EDA Netlist Writer Summary ;
|
||||
+---------------------------+---------------------------------------+
|
||||
; EDA Netlist Writer Status ; Successful - Tue Mar 7 20:31:07 2023 ;
|
||||
; EDA Netlist Writer Status ; Successful - Tue Mar 7 23:04:02 2023 ;
|
||||
; Revision Name ; AND2Gate ;
|
||||
; Top-level Entity Name ; GateDemo ;
|
||||
; Family ; Cyclone IV E ;
|
||||
|
|
@ -81,13 +81,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime EDA Netlist Writer
|
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Info: Processing started: Tue Mar 7 20:31:06 2023
|
||||
Info: Processing started: Tue Mar 7 23:04:01 2023
|
||||
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off VHDLDemo -c AND2Gate
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (204019): Generated file AND2Gate.vho in folder "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/simulation/modelsim/" for EDA simulation tool
|
||||
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 612 megabytes
|
||||
Info: Processing ended: Tue Mar 7 20:31:07 2023
|
||||
Info: Processing ended: Tue Mar 7 23:04:02 2023
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:00
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Fitter report for AND2Gate
|
||||
Tue Mar 7 20:31:00 2023
|
||||
Tue Mar 7 23:03:56 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -64,7 +64,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
; Fitter Status ; Successful - Tue Mar 7 20:31:00 2023 ;
|
||||
; Fitter Status ; Successful - Tue Mar 7 23:03:56 2023 ;
|
||||
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
|
||||
; Revision Name ; AND2Gate ;
|
||||
; Top-level Entity Name ; GateDemo ;
|
||||
|
|
@ -2468,7 +2468,7 @@ Warning (15705): Ignored locations or region assignments to the following nodes
|
|||
Warning (15706): Node "VGA_R[7]" is assigned to location or region, but does not exist in design
|
||||
Warning (15706): Node "VGA_SYNC_N" is assigned to location or region, but does not exist in design
|
||||
Warning (15706): Node "VGA_VS" is assigned to location or region, but does not exist in design
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
|
|
@ -2482,19 +2482,19 @@ Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were
|
|||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170200): Optimizations that may affect the design's timing were skipped
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.01 seconds.
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (334003): Started post-fitting delay annotation
|
||||
Info (334004): Delay annotation completed successfully
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
||||
Info (144001): Generated suppressed messages file /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica01/part2/output_files/AND2Gate.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 522 warnings
|
||||
Info: Peak virtual memory: 1142 megabytes
|
||||
Info: Processing ended: Tue Mar 7 20:31:00 2023
|
||||
Info: Elapsed time: 00:00:10
|
||||
Info: Total CPU time (on all processors): 00:00:16
|
||||
Info: Peak virtual memory: 1149 megabytes
|
||||
Info: Processing ended: Tue Mar 7 23:03:57 2023
|
||||
Info: Elapsed time: 00:00:07
|
||||
Info: Total CPU time (on all processors): 00:00:10
|
||||
|
||||
|
||||
+----------------------------+
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Fitter Status : Successful - Tue Mar 7 20:31:00 2023
|
||||
Fitter Status : Successful - Tue Mar 7 23:03:56 2023
|
||||
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Revision Name : AND2Gate
|
||||
Top-level Entity Name : GateDemo
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Flow report for AND2Gate
|
||||
Tue Mar 7 20:31:07 2023
|
||||
Tue Mar 7 23:04:02 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Mar 7 20:31:07 2023 ;
|
||||
; Flow Status ; Successful - Tue Mar 7 23:04:02 2023 ;
|
||||
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
|
||||
; Revision Name ; AND2Gate ;
|
||||
; Top-level Entity Name ; GateDemo ;
|
||||
|
|
@ -65,7 +65,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 03/07/2023 20:30:44 ;
|
||||
; Start date & time ; 03/07/2023 23:03:44 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; AND2Gate ;
|
||||
+-------------------+---------------------+
|
||||
|
|
@ -76,7 +76,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
|
||||
; COMPILER_SIGNATURE_ID ; 2690080394329.167822104406633 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 2690080394329.167823022420872 ; -- ; -- ; -- ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
|
||||
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
|
||||
|
|
@ -102,12 +102,12 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 432 MB ; 00:00:16 ;
|
||||
; Fitter ; 00:00:10 ; 1.0 ; 1142 MB ; 00:00:15 ;
|
||||
; Assembler ; 00:00:03 ; 1.0 ; 367 MB ; 00:00:03 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 533 MB ; 00:00:01 ;
|
||||
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 433 MB ; 00:00:13 ;
|
||||
; Fitter ; 00:00:06 ; 1.0 ; 1149 MB ; 00:00:09 ;
|
||||
; Assembler ; 00:00:02 ; 1.0 ; 367 MB ; 00:00:02 ;
|
||||
; Timing Analyzer ; 00:00:01 ; 1.0 ; 533 MB ; 00:00:01 ;
|
||||
; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 612 MB ; 00:00:00 ;
|
||||
; Total ; 00:00:23 ; -- ; -- ; 00:00:35 ;
|
||||
; Total ; 00:00:16 ; -- ; -- ; 00:00:25 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Analysis & Synthesis report for AND2Gate
|
||||
Tue Mar 7 20:30:50 2023
|
||||
Tue Mar 7 23:03:50 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -43,7 +43,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+------------------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Tue Mar 7 20:30:50 2023 ;
|
||||
; Analysis & Synthesis Status ; Successful - Tue Mar 7 23:03:50 2023 ;
|
||||
; Quartus Prime Version ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
|
||||
; Revision Name ; AND2Gate ;
|
||||
; Top-level Entity Name ; GateDemo ;
|
||||
|
|
@ -265,7 +265,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Info: Processing started: Tue Mar 7 20:30:43 2023
|
||||
Info: Processing started: Tue Mar 7 23:03:44 2023
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VHDLDemo -c AND2Gate
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||||
|
|
@ -298,9 +298,9 @@ Info (21057): Implemented 5 device resources after synthesis - the final resourc
|
|||
Info (21059): Implemented 2 output pins
|
||||
Info (21061): Implemented 1 logic cells
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 4 warnings
|
||||
Info: Peak virtual memory: 432 megabytes
|
||||
Info: Processing ended: Tue Mar 7 20:30:50 2023
|
||||
Info: Elapsed time: 00:00:07
|
||||
Info: Total CPU time (on all processors): 00:00:16
|
||||
Info: Peak virtual memory: 433 megabytes
|
||||
Info: Processing ended: Tue Mar 7 23:03:50 2023
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Total CPU time (on all processors): 00:00:13
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Analysis & Synthesis Status : Successful - Tue Mar 7 20:30:50 2023
|
||||
Analysis & Synthesis Status : Successful - Tue Mar 7 23:03:50 2023
|
||||
Quartus Prime Version : 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Revision Name : AND2Gate
|
||||
Top-level Entity Name : GateDemo
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,5 +1,5 @@
|
|||
Timing Analyzer report for AND2Gate
|
||||
Tue Mar 7 20:31:06 2023
|
||||
Tue Mar 7 23:04:00 2023
|
||||
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -379,7 +379,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Info: Processing started: Tue Mar 7 20:31:04 2023
|
||||
Info: Processing started: Tue Mar 7 23:03:59 2023
|
||||
Info: Command: quartus_sta VHDLDemo -c AND2Gate
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||||
|
|
@ -428,8 +428,8 @@ Info (332102): Design is not fully constrained for setup requirements
|
|||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
||||
Info: Peak virtual memory: 533 megabytes
|
||||
Info: Processing ended: Tue Mar 7 20:31:06 2023
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Processing ended: Tue Mar 7 23:04:00 2023
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
-- PROGRAM "Quartus Prime"
|
||||
-- VERSION "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition"
|
||||
|
||||
-- DATE "03/07/2023 20:31:07"
|
||||
-- DATE "03/07/2023 23:04:02"
|
||||
|
||||
--
|
||||
-- Device: Altera EP4CE115F29C7 Package FBGA780
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1181,4 +1181,5 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
|
|||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name VHDL_FILE EqCmp8.vhd
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE EqCmp8.vwf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE EqCmp4.vwf
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 16 16 176 128)
|
||||
(text "Mux2_1" (rect 5 0 36 12)(font "Arial" ))
|
||||
(text "inst" (rect 8 96 20 108)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "dataIn0" (rect 0 0 28 12)(font "Arial" ))
|
||||
(text "dataIn0" (rect 21 27 49 39)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "dataIn1" (rect 0 0 27 12)(font "Arial" ))
|
||||
(text "dataIn1" (rect 21 43 48 55)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "sel" (rect 0 0 10 12)(font "Arial" ))
|
||||
(text "sel" (rect 21 59 31 71)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64)(line_width 1))
|
||||
)
|
||||
(port
|
||||
(pt 160 32)
|
||||
(output)
|
||||
(text "dataOut" (rect 0 0 30 12)(font "Arial" ))
|
||||
(text "dataOut" (rect 109 27 139 39)(font "Arial" ))
|
||||
(line (pt 160 32)(pt 144 32)(line_width 1))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 144 96)(line_width 1))
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
|
||||
entity Mux2_1 is
|
||||
port
|
||||
(
|
||||
dataIn0 : in std_logic;
|
||||
dataIn1 : in std_logic;
|
||||
sel : in std_logic;
|
||||
dataOut : out std_logic
|
||||
);
|
||||
end Mux2_1;
|
||||
|
||||
architecture Behavioral of Mux2_1 is
|
||||
begin
|
||||
process(dataIn0, dataIn1, sel)
|
||||
begin
|
||||
if (sel = '0') then
|
||||
dataOut <= dataIn0;
|
||||
else
|
||||
dataOut <= dataIn1;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
|
||||
entity Mux2_1 is
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
/*<simulation_settings>
|
||||
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht"</ftestbench_cmd>
|
||||
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off Mux2_1Demo -c Mux2_1Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/Mux2_1.vwf.vht"</ttestbench_cmd>
|
||||
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/" Mux2_1Demo -c Mux2_1Demo</fnetlist_cmd>
|
||||
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/" Mux2_1Demo -c Mux2_1Demo</tnetlist_cmd>
|
||||
<modelsim_script>onerror {exit -code 1}
|
||||
vlib work
|
||||
vcom -work work Mux2_1Demo.vho
|
||||
vcom -work work Mux2_1.vwf.vht
|
||||
vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux2_1Demo_vhd_vec_tst
|
||||
vcd file -direction Mux2_1Demo.msim.vcd
|
||||
vcd add -internal Mux2_1Demo_vhd_vec_tst/*
|
||||
vcd add -internal Mux2_1Demo_vhd_vec_tst/i1/*
|
||||
proc simTimestamp {} {
|
||||
echo "Simulation time: $::now ps"
|
||||
if { [string equal running [runStatus]] } {
|
||||
after 2500 simTimestamp
|
||||
}
|
||||
}
|
||||
after 2500 simTimestamp
|
||||
run -all
|
||||
quit -f
|
||||
</modelsim_script>
|
||||
<modelsim_script_timing>onerror {exit -code 1}
|
||||
vlib work
|
||||
vcom -work work Mux2_1Demo.vho
|
||||
vcom -work work Mux2_1.vwf.vht
|
||||
vsim -novopt -c -t 1ps -sdfmax Mux2_1Demo_vhd_vec_tst/i1=Mux2_1Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.Mux2_1Demo_vhd_vec_tst
|
||||
vcd file -direction Mux2_1Demo.msim.vcd
|
||||
vcd add -internal Mux2_1Demo_vhd_vec_tst/*
|
||||
vcd add -internal Mux2_1Demo_vhd_vec_tst/i1/*
|
||||
proc simTimestamp {} {
|
||||
echo "Simulation time: $::now ps"
|
||||
if { [string equal running [runStatus]] } {
|
||||
after 2500 simTimestamp
|
||||
}
|
||||
}
|
||||
after 2500 simTimestamp
|
||||
run -all
|
||||
quit -f
|
||||
</modelsim_script_timing>
|
||||
<hdl_lang>vhdl</hdl_lang>
|
||||
</simulation_settings>*/
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
|
||||
HEADER
|
||||
{
|
||||
VERSION = 1;
|
||||
TIME_UNIT = ns;
|
||||
DATA_OFFSET = 0.0;
|
||||
DATA_DURATION = 1000.0;
|
||||
SIMULATION_TIME = 0.0;
|
||||
GRID_PHASE = 0.0;
|
||||
GRID_PERIOD = 10.0;
|
||||
GRID_DUTY_CYCLE = 50;
|
||||
}
|
||||
|
||||
SIGNAL("dataIn0")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("dataIn1")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("dataOut")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("sel")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataIn0")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 2;
|
||||
LEVEL 0 FOR 200.0;
|
||||
LEVEL 1 FOR 200.0;
|
||||
}
|
||||
LEVEL 0 FOR 200.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataIn1")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 5;
|
||||
LEVEL 0 FOR 100.0;
|
||||
LEVEL 1 FOR 100.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataOut")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("sel")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 400.0;
|
||||
LEVEL 1 FOR 400.0;
|
||||
}
|
||||
LEVEL 0 FOR 200.0;
|
||||
}
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn0";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 0;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn1";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 1;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "sel";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 2;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataOut";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 3;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
TIME_BAR
|
||||
{
|
||||
TIME = 0;
|
||||
MASTER = TRUE;
|
||||
}
|
||||
;
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 304 248 472 264)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "KEY[0]" (rect 5 0 40 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 304 216 472 232)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[0]" (rect 5 0 39 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 304 232 472 248)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[1]" (rect 5 0 39 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 648 216 824 232)
|
||||
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
|
||||
(text "LEDG[0]" (rect 90 0 132 11)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(rect 480 192 640 304)
|
||||
(text "Mux2_1" (rect 5 0 46 11)(font "Arial" ))
|
||||
(text "inst" (rect 8 96 26 107)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "dataIn0" (rect 0 0 38 11)(font "Arial" ))
|
||||
(text "dataIn0" (rect 21 27 59 38)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "dataIn1" (rect 0 0 38 11)(font "Arial" ))
|
||||
(text "dataIn1" (rect 21 43 59 54)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "sel" (rect 0 0 15 11)(font "Arial" ))
|
||||
(text "sel" (rect 21 59 36 70)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 160 32)
|
||||
(output)
|
||||
(text "dataOut" (rect 0 0 41 11)(font "Arial" ))
|
||||
(text "dataOut" (rect 105 27 146 38)(font "Arial" ))
|
||||
(line (pt 160 32)(pt 144 32))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 144 96))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 480 224)
|
||||
(pt 472 224)
|
||||
)
|
||||
(connector
|
||||
(pt 480 240)
|
||||
(pt 472 240)
|
||||
)
|
||||
(connector
|
||||
(pt 480 256)
|
||||
(pt 472 256)
|
||||
)
|
||||
(connector
|
||||
(pt 648 224)
|
||||
(pt 640 224)
|
||||
)
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
# Date created = 21:28:47 March 07, 2023
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "20.1"
|
||||
DATE = "21:28:47 March 07, 2023"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Mux2_1Demo"
|
||||
|
|
@ -0,0 +1,583 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
# Date created = 21:28:47 March 07, 2023
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Mux2_1Demo_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE115F29C7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Mux2_1Demo
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:28:47 MARCH 07, 2023"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
|
||||
set_global_assignment -name VHDL_FILE Mux2_1.vhd
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Mux2_1.vwf
|
||||
set_global_assignment -name BDF_FILE Mux2_1Demo.bdf
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_location_assignment PIN_Y2 -to CLOCK_50
|
||||
set_location_assignment PIN_AG14 -to CLOCK2_50
|
||||
set_location_assignment PIN_AG15 -to CLOCK3_50
|
||||
set_location_assignment PIN_AH14 -to SMA_CLKIN
|
||||
set_location_assignment PIN_AE23 -to SMA_CLKOUT
|
||||
set_location_assignment PIN_M23 -to KEY[0]
|
||||
set_location_assignment PIN_M21 -to KEY[1]
|
||||
set_location_assignment PIN_N21 -to KEY[2]
|
||||
set_location_assignment PIN_R24 -to KEY[3]
|
||||
set_location_assignment PIN_AB28 -to SW[0]
|
||||
set_location_assignment PIN_AC28 -to SW[1]
|
||||
set_location_assignment PIN_AC27 -to SW[2]
|
||||
set_location_assignment PIN_AD27 -to SW[3]
|
||||
set_location_assignment PIN_AB27 -to SW[4]
|
||||
set_location_assignment PIN_AC26 -to SW[5]
|
||||
set_location_assignment PIN_AD26 -to SW[6]
|
||||
set_location_assignment PIN_AB26 -to SW[7]
|
||||
set_location_assignment PIN_AC25 -to SW[8]
|
||||
set_location_assignment PIN_AB25 -to SW[9]
|
||||
set_location_assignment PIN_AC24 -to SW[10]
|
||||
set_location_assignment PIN_AB24 -to SW[11]
|
||||
set_location_assignment PIN_AB23 -to SW[12]
|
||||
set_location_assignment PIN_AA24 -to SW[13]
|
||||
set_location_assignment PIN_AA23 -to SW[14]
|
||||
set_location_assignment PIN_AA22 -to SW[15]
|
||||
set_location_assignment PIN_Y24 -to SW[16]
|
||||
set_location_assignment PIN_Y23 -to SW[17]
|
||||
set_location_assignment PIN_G19 -to LEDR[0]
|
||||
set_location_assignment PIN_F19 -to LEDR[1]
|
||||
set_location_assignment PIN_E19 -to LEDR[2]
|
||||
set_location_assignment PIN_F21 -to LEDR[3]
|
||||
set_location_assignment PIN_F18 -to LEDR[4]
|
||||
set_location_assignment PIN_E18 -to LEDR[5]
|
||||
set_location_assignment PIN_J19 -to LEDR[6]
|
||||
set_location_assignment PIN_H19 -to LEDR[7]
|
||||
set_location_assignment PIN_J17 -to LEDR[8]
|
||||
set_location_assignment PIN_G17 -to LEDR[9]
|
||||
set_location_assignment PIN_J15 -to LEDR[10]
|
||||
set_location_assignment PIN_H16 -to LEDR[11]
|
||||
set_location_assignment PIN_J16 -to LEDR[12]
|
||||
set_location_assignment PIN_H17 -to LEDR[13]
|
||||
set_location_assignment PIN_F15 -to LEDR[14]
|
||||
set_location_assignment PIN_G15 -to LEDR[15]
|
||||
set_location_assignment PIN_G16 -to LEDR[16]
|
||||
set_location_assignment PIN_H15 -to LEDR[17]
|
||||
set_location_assignment PIN_E21 -to LEDG[0]
|
||||
set_location_assignment PIN_E22 -to LEDG[1]
|
||||
set_location_assignment PIN_E25 -to LEDG[2]
|
||||
set_location_assignment PIN_E24 -to LEDG[3]
|
||||
set_location_assignment PIN_H21 -to LEDG[4]
|
||||
set_location_assignment PIN_G20 -to LEDG[5]
|
||||
set_location_assignment PIN_G22 -to LEDG[6]
|
||||
set_location_assignment PIN_G21 -to LEDG[7]
|
||||
set_location_assignment PIN_F17 -to LEDG[8]
|
||||
set_location_assignment PIN_G18 -to HEX0[0]
|
||||
set_location_assignment PIN_F22 -to HEX0[1]
|
||||
set_location_assignment PIN_E17 -to HEX0[2]
|
||||
set_location_assignment PIN_L26 -to HEX0[3]
|
||||
set_location_assignment PIN_L25 -to HEX0[4]
|
||||
set_location_assignment PIN_J22 -to HEX0[5]
|
||||
set_location_assignment PIN_H22 -to HEX0[6]
|
||||
set_location_assignment PIN_M24 -to HEX1[0]
|
||||
set_location_assignment PIN_Y22 -to HEX1[1]
|
||||
set_location_assignment PIN_W21 -to HEX1[2]
|
||||
set_location_assignment PIN_W22 -to HEX1[3]
|
||||
set_location_assignment PIN_W25 -to HEX1[4]
|
||||
set_location_assignment PIN_U23 -to HEX1[5]
|
||||
set_location_assignment PIN_U24 -to HEX1[6]
|
||||
set_location_assignment PIN_AA25 -to HEX2[0]
|
||||
set_location_assignment PIN_AA26 -to HEX2[1]
|
||||
set_location_assignment PIN_Y25 -to HEX2[2]
|
||||
set_location_assignment PIN_W26 -to HEX2[3]
|
||||
set_location_assignment PIN_Y26 -to HEX2[4]
|
||||
set_location_assignment PIN_W27 -to HEX2[5]
|
||||
set_location_assignment PIN_W28 -to HEX2[6]
|
||||
set_location_assignment PIN_V21 -to HEX3[0]
|
||||
set_location_assignment PIN_U21 -to HEX3[1]
|
||||
set_location_assignment PIN_AB20 -to HEX3[2]
|
||||
set_location_assignment PIN_AA21 -to HEX3[3]
|
||||
set_location_assignment PIN_AD24 -to HEX3[4]
|
||||
set_location_assignment PIN_AF23 -to HEX3[5]
|
||||
set_location_assignment PIN_Y19 -to HEX3[6]
|
||||
set_location_assignment PIN_AB19 -to HEX4[0]
|
||||
set_location_assignment PIN_AA19 -to HEX4[1]
|
||||
set_location_assignment PIN_AG21 -to HEX4[2]
|
||||
set_location_assignment PIN_AH21 -to HEX4[3]
|
||||
set_location_assignment PIN_AE19 -to HEX4[4]
|
||||
set_location_assignment PIN_AF19 -to HEX4[5]
|
||||
set_location_assignment PIN_AE18 -to HEX4[6]
|
||||
set_location_assignment PIN_AD18 -to HEX5[0]
|
||||
set_location_assignment PIN_AC18 -to HEX5[1]
|
||||
set_location_assignment PIN_AB18 -to HEX5[2]
|
||||
set_location_assignment PIN_AH19 -to HEX5[3]
|
||||
set_location_assignment PIN_AG19 -to HEX5[4]
|
||||
set_location_assignment PIN_AF18 -to HEX5[5]
|
||||
set_location_assignment PIN_AH18 -to HEX5[6]
|
||||
set_location_assignment PIN_AA17 -to HEX6[0]
|
||||
set_location_assignment PIN_AB16 -to HEX6[1]
|
||||
set_location_assignment PIN_AA16 -to HEX6[2]
|
||||
set_location_assignment PIN_AB17 -to HEX6[3]
|
||||
set_location_assignment PIN_AB15 -to HEX6[4]
|
||||
set_location_assignment PIN_AA15 -to HEX6[5]
|
||||
set_location_assignment PIN_AC17 -to HEX6[6]
|
||||
set_location_assignment PIN_AD17 -to HEX7[0]
|
||||
set_location_assignment PIN_AE17 -to HEX7[1]
|
||||
set_location_assignment PIN_AG17 -to HEX7[2]
|
||||
set_location_assignment PIN_AH17 -to HEX7[3]
|
||||
set_location_assignment PIN_AF17 -to HEX7[4]
|
||||
set_location_assignment PIN_AG18 -to HEX7[5]
|
||||
set_location_assignment PIN_AA14 -to HEX7[6]
|
||||
set_location_assignment PIN_L3 -to LCD_DATA[0]
|
||||
set_location_assignment PIN_L1 -to LCD_DATA[1]
|
||||
set_location_assignment PIN_L2 -to LCD_DATA[2]
|
||||
set_location_assignment PIN_K7 -to LCD_DATA[3]
|
||||
set_location_assignment PIN_K1 -to LCD_DATA[4]
|
||||
set_location_assignment PIN_K2 -to LCD_DATA[5]
|
||||
set_location_assignment PIN_M3 -to LCD_DATA[6]
|
||||
set_location_assignment PIN_M5 -to LCD_DATA[7]
|
||||
set_location_assignment PIN_L6 -to LCD_BLON
|
||||
set_location_assignment PIN_M1 -to LCD_RW
|
||||
set_location_assignment PIN_L4 -to LCD_EN
|
||||
set_location_assignment PIN_M2 -to LCD_RS
|
||||
set_location_assignment PIN_L5 -to LCD_ON
|
||||
set_location_assignment PIN_G9 -to UART_TXD
|
||||
set_location_assignment PIN_G12 -to UART_RXD
|
||||
set_location_assignment PIN_G14 -to UART_CTS
|
||||
set_location_assignment PIN_J13 -to UART_RTS
|
||||
set_location_assignment PIN_G6 -to PS2_CLK
|
||||
set_location_assignment PIN_H5 -to PS2_DAT
|
||||
set_location_assignment PIN_G5 -to PS2_CLK2
|
||||
set_location_assignment PIN_F5 -to PS2_DAT2
|
||||
set_location_assignment PIN_AE13 -to SD_CLK
|
||||
set_location_assignment PIN_AD14 -to SD_CMD
|
||||
set_location_assignment PIN_AF14 -to SD_WP_N
|
||||
set_location_assignment PIN_AE14 -to SD_DAT[0]
|
||||
set_location_assignment PIN_AF13 -to SD_DAT[1]
|
||||
set_location_assignment PIN_AB14 -to SD_DAT[2]
|
||||
set_location_assignment PIN_AC14 -to SD_DAT[3]
|
||||
set_location_assignment PIN_G13 -to VGA_HS
|
||||
set_location_assignment PIN_C13 -to VGA_VS
|
||||
set_location_assignment PIN_C10 -to VGA_SYNC_N
|
||||
set_location_assignment PIN_A12 -to VGA_CLK
|
||||
set_location_assignment PIN_F11 -to VGA_BLANK_N
|
||||
set_location_assignment PIN_E12 -to VGA_R[0]
|
||||
set_location_assignment PIN_E11 -to VGA_R[1]
|
||||
set_location_assignment PIN_D10 -to VGA_R[2]
|
||||
set_location_assignment PIN_F12 -to VGA_R[3]
|
||||
set_location_assignment PIN_G10 -to VGA_R[4]
|
||||
set_location_assignment PIN_J12 -to VGA_R[5]
|
||||
set_location_assignment PIN_H8 -to VGA_R[6]
|
||||
set_location_assignment PIN_H10 -to VGA_R[7]
|
||||
set_location_assignment PIN_G8 -to VGA_G[0]
|
||||
set_location_assignment PIN_G11 -to VGA_G[1]
|
||||
set_location_assignment PIN_F8 -to VGA_G[2]
|
||||
set_location_assignment PIN_H12 -to VGA_G[3]
|
||||
set_location_assignment PIN_C8 -to VGA_G[4]
|
||||
set_location_assignment PIN_B8 -to VGA_G[5]
|
||||
set_location_assignment PIN_F10 -to VGA_G[6]
|
||||
set_location_assignment PIN_C9 -to VGA_G[7]
|
||||
set_location_assignment PIN_B10 -to VGA_B[0]
|
||||
set_location_assignment PIN_A10 -to VGA_B[1]
|
||||
set_location_assignment PIN_C11 -to VGA_B[2]
|
||||
set_location_assignment PIN_B11 -to VGA_B[3]
|
||||
set_location_assignment PIN_A11 -to VGA_B[4]
|
||||
set_location_assignment PIN_C12 -to VGA_B[5]
|
||||
set_location_assignment PIN_D11 -to VGA_B[6]
|
||||
set_location_assignment PIN_D12 -to VGA_B[7]
|
||||
set_location_assignment PIN_C2 -to AUD_ADCLRCK
|
||||
set_location_assignment PIN_D2 -to AUD_ADCDAT
|
||||
set_location_assignment PIN_E3 -to AUD_DACLRCK
|
||||
set_location_assignment PIN_D1 -to AUD_DACDAT
|
||||
set_location_assignment PIN_E1 -to AUD_XCK
|
||||
set_location_assignment PIN_F2 -to AUD_BCLK
|
||||
set_location_assignment PIN_D14 -to EEP_I2C_SCLK
|
||||
set_location_assignment PIN_E14 -to EEP_I2C_SDAT
|
||||
set_location_assignment PIN_B7 -to I2C_SCLK
|
||||
set_location_assignment PIN_A8 -to I2C_SDAT
|
||||
set_location_assignment PIN_A14 -to ENETCLK_25
|
||||
set_location_assignment PIN_C14 -to ENET0_LINK100
|
||||
set_location_assignment PIN_A17 -to ENET0_GTX_CLK
|
||||
set_location_assignment PIN_C19 -to ENET0_RST_N
|
||||
set_location_assignment PIN_C20 -to ENET0_MDC
|
||||
set_location_assignment PIN_B21 -to ENET0_MDIO
|
||||
set_location_assignment PIN_A21 -to ENET0_INT_N
|
||||
set_location_assignment PIN_C18 -to ENET0_TX_DATA[0]
|
||||
set_location_assignment PIN_D19 -to ENET0_TX_DATA[1]
|
||||
set_location_assignment PIN_A19 -to ENET0_TX_DATA[2]
|
||||
set_location_assignment PIN_B19 -to ENET0_TX_DATA[3]
|
||||
set_location_assignment PIN_B17 -to ENET0_TX_CLK
|
||||
set_location_assignment PIN_A18 -to ENET0_TX_EN
|
||||
set_location_assignment PIN_B18 -to ENET0_TX_ER
|
||||
set_location_assignment PIN_C16 -to ENET0_RX_DATA[0]
|
||||
set_location_assignment PIN_D16 -to ENET0_RX_DATA[1]
|
||||
set_location_assignment PIN_D17 -to ENET0_RX_DATA[2]
|
||||
set_location_assignment PIN_C15 -to ENET0_RX_DATA[3]
|
||||
set_location_assignment PIN_A15 -to ENET0_RX_CLK
|
||||
set_location_assignment PIN_C17 -to ENET0_RX_DV
|
||||
set_location_assignment PIN_D18 -to ENET0_RX_ER
|
||||
set_location_assignment PIN_D15 -to ENET0_RX_CRS
|
||||
set_location_assignment PIN_E15 -to ENET0_RX_COL
|
||||
set_location_assignment PIN_D13 -to ENET1_LINK100
|
||||
set_location_assignment PIN_C23 -to ENET1_GTX_CLK
|
||||
set_location_assignment PIN_D22 -to ENET1_RST_N
|
||||
set_location_assignment PIN_D23 -to ENET1_MDC
|
||||
set_location_assignment PIN_D25 -to ENET1_MDIO
|
||||
set_location_assignment PIN_D24 -to ENET1_INT_N
|
||||
set_location_assignment PIN_C25 -to ENET1_TX_DATA[0]
|
||||
set_location_assignment PIN_A26 -to ENET1_TX_DATA[1]
|
||||
set_location_assignment PIN_B26 -to ENET1_TX_DATA[2]
|
||||
set_location_assignment PIN_C26 -to ENET1_TX_DATA[3]
|
||||
set_location_assignment PIN_C22 -to ENET1_TX_CLK
|
||||
set_location_assignment PIN_B25 -to ENET1_TX_EN
|
||||
set_location_assignment PIN_A25 -to ENET1_TX_ER
|
||||
set_location_assignment PIN_B23 -to ENET1_RX_DATA[0]
|
||||
set_location_assignment PIN_C21 -to ENET1_RX_DATA[1]
|
||||
set_location_assignment PIN_A23 -to ENET1_RX_DATA[2]
|
||||
set_location_assignment PIN_D21 -to ENET1_RX_DATA[3]
|
||||
set_location_assignment PIN_B15 -to ENET1_RX_CLK
|
||||
set_location_assignment PIN_A22 -to ENET1_RX_DV
|
||||
set_location_assignment PIN_C24 -to ENET1_RX_ER
|
||||
set_location_assignment PIN_D20 -to ENET1_RX_CRS
|
||||
set_location_assignment PIN_B22 -to ENET1_RX_COL
|
||||
set_location_assignment PIN_E5 -to TD_HS
|
||||
set_location_assignment PIN_E4 -to TD_VS
|
||||
set_location_assignment PIN_B14 -to TD_CLK27
|
||||
set_location_assignment PIN_G7 -to TD_RESET_N
|
||||
set_location_assignment PIN_E8 -to TD_DATA[0]
|
||||
set_location_assignment PIN_A7 -to TD_DATA[1]
|
||||
set_location_assignment PIN_D8 -to TD_DATA[2]
|
||||
set_location_assignment PIN_C7 -to TD_DATA[3]
|
||||
set_location_assignment PIN_D7 -to TD_DATA[4]
|
||||
set_location_assignment PIN_D6 -to TD_DATA[5]
|
||||
set_location_assignment PIN_E7 -to TD_DATA[6]
|
||||
set_location_assignment PIN_F7 -to TD_DATA[7]
|
||||
set_location_assignment PIN_J6 -to OTG_DATA[0]
|
||||
set_location_assignment PIN_K4 -to OTG_DATA[1]
|
||||
set_location_assignment PIN_J5 -to OTG_DATA[2]
|
||||
set_location_assignment PIN_K3 -to OTG_DATA[3]
|
||||
set_location_assignment PIN_J4 -to OTG_DATA[4]
|
||||
set_location_assignment PIN_J3 -to OTG_DATA[5]
|
||||
set_location_assignment PIN_J7 -to OTG_DATA[6]
|
||||
set_location_assignment PIN_H6 -to OTG_DATA[7]
|
||||
set_location_assignment PIN_H3 -to OTG_DATA[8]
|
||||
set_location_assignment PIN_H4 -to OTG_DATA[9]
|
||||
set_location_assignment PIN_G1 -to OTG_DATA[10]
|
||||
set_location_assignment PIN_G2 -to OTG_DATA[11]
|
||||
set_location_assignment PIN_G3 -to OTG_DATA[12]
|
||||
set_location_assignment PIN_F1 -to OTG_DATA[13]
|
||||
set_location_assignment PIN_F3 -to OTG_DATA[14]
|
||||
set_location_assignment PIN_G4 -to OTG_DATA[15]
|
||||
set_location_assignment PIN_H7 -to OTG_ADDR[0]
|
||||
set_location_assignment PIN_C3 -to OTG_ADDR[1]
|
||||
set_location_assignment PIN_J1 -to OTG_DREQ[0]
|
||||
set_location_assignment PIN_A3 -to OTG_CS_N
|
||||
set_location_assignment PIN_A4 -to OTG_WR_N
|
||||
set_location_assignment PIN_B3 -to OTG_RD_N
|
||||
set_location_assignment PIN_D5 -to OTG_INT
|
||||
set_location_assignment PIN_C5 -to OTG_RST_N
|
||||
set_location_assignment PIN_Y15 -to IRDA_RXD
|
||||
set_location_assignment PIN_U7 -to DRAM_BA[0]
|
||||
set_location_assignment PIN_R4 -to DRAM_BA[1]
|
||||
set_location_assignment PIN_U2 -to DRAM_DQM[0]
|
||||
set_location_assignment PIN_W4 -to DRAM_DQM[1]
|
||||
set_location_assignment PIN_K8 -to DRAM_DQM[2]
|
||||
set_location_assignment PIN_N8 -to DRAM_DQM[3]
|
||||
set_location_assignment PIN_U6 -to DRAM_RAS_N
|
||||
set_location_assignment PIN_V7 -to DRAM_CAS_N
|
||||
set_location_assignment PIN_AA6 -to DRAM_CKE
|
||||
set_location_assignment PIN_AE5 -to DRAM_CLK
|
||||
set_location_assignment PIN_V6 -to DRAM_WE_N
|
||||
set_location_assignment PIN_T4 -to DRAM_CS_N
|
||||
set_location_assignment PIN_W3 -to DRAM_DQ[0]
|
||||
set_location_assignment PIN_W2 -to DRAM_DQ[1]
|
||||
set_location_assignment PIN_V4 -to DRAM_DQ[2]
|
||||
set_location_assignment PIN_W1 -to DRAM_DQ[3]
|
||||
set_location_assignment PIN_V3 -to DRAM_DQ[4]
|
||||
set_location_assignment PIN_V2 -to DRAM_DQ[5]
|
||||
set_location_assignment PIN_V1 -to DRAM_DQ[6]
|
||||
set_location_assignment PIN_U3 -to DRAM_DQ[7]
|
||||
set_location_assignment PIN_Y3 -to DRAM_DQ[8]
|
||||
set_location_assignment PIN_Y4 -to DRAM_DQ[9]
|
||||
set_location_assignment PIN_AB1 -to DRAM_DQ[10]
|
||||
set_location_assignment PIN_AA3 -to DRAM_DQ[11]
|
||||
set_location_assignment PIN_AB2 -to DRAM_DQ[12]
|
||||
set_location_assignment PIN_AC1 -to DRAM_DQ[13]
|
||||
set_location_assignment PIN_AB3 -to DRAM_DQ[14]
|
||||
set_location_assignment PIN_AC2 -to DRAM_DQ[15]
|
||||
set_location_assignment PIN_M8 -to DRAM_DQ[16]
|
||||
set_location_assignment PIN_L8 -to DRAM_DQ[17]
|
||||
set_location_assignment PIN_P2 -to DRAM_DQ[18]
|
||||
set_location_assignment PIN_N3 -to DRAM_DQ[19]
|
||||
set_location_assignment PIN_N4 -to DRAM_DQ[20]
|
||||
set_location_assignment PIN_M4 -to DRAM_DQ[21]
|
||||
set_location_assignment PIN_M7 -to DRAM_DQ[22]
|
||||
set_location_assignment PIN_L7 -to DRAM_DQ[23]
|
||||
set_location_assignment PIN_U5 -to DRAM_DQ[24]
|
||||
set_location_assignment PIN_R7 -to DRAM_DQ[25]
|
||||
set_location_assignment PIN_R1 -to DRAM_DQ[26]
|
||||
set_location_assignment PIN_R2 -to DRAM_DQ[27]
|
||||
set_location_assignment PIN_R3 -to DRAM_DQ[28]
|
||||
set_location_assignment PIN_T3 -to DRAM_DQ[29]
|
||||
set_location_assignment PIN_U4 -to DRAM_DQ[30]
|
||||
set_location_assignment PIN_U1 -to DRAM_DQ[31]
|
||||
set_location_assignment PIN_R6 -to DRAM_ADDR[0]
|
||||
set_location_assignment PIN_V8 -to DRAM_ADDR[1]
|
||||
set_location_assignment PIN_U8 -to DRAM_ADDR[2]
|
||||
set_location_assignment PIN_P1 -to DRAM_ADDR[3]
|
||||
set_location_assignment PIN_V5 -to DRAM_ADDR[4]
|
||||
set_location_assignment PIN_W8 -to DRAM_ADDR[5]
|
||||
set_location_assignment PIN_W7 -to DRAM_ADDR[6]
|
||||
set_location_assignment PIN_AA7 -to DRAM_ADDR[7]
|
||||
set_location_assignment PIN_Y5 -to DRAM_ADDR[8]
|
||||
set_location_assignment PIN_Y6 -to DRAM_ADDR[9]
|
||||
set_location_assignment PIN_R5 -to DRAM_ADDR[10]
|
||||
set_location_assignment PIN_AA5 -to DRAM_ADDR[11]
|
||||
set_location_assignment PIN_Y7 -to DRAM_ADDR[12]
|
||||
set_location_assignment PIN_AB7 -to SRAM_ADDR[0]
|
||||
set_location_assignment PIN_AD7 -to SRAM_ADDR[1]
|
||||
set_location_assignment PIN_AE7 -to SRAM_ADDR[2]
|
||||
set_location_assignment PIN_AC7 -to SRAM_ADDR[3]
|
||||
set_location_assignment PIN_AB6 -to SRAM_ADDR[4]
|
||||
set_location_assignment PIN_AE6 -to SRAM_ADDR[5]
|
||||
set_location_assignment PIN_AB5 -to SRAM_ADDR[6]
|
||||
set_location_assignment PIN_AC5 -to SRAM_ADDR[7]
|
||||
set_location_assignment PIN_AF5 -to SRAM_ADDR[8]
|
||||
set_location_assignment PIN_T7 -to SRAM_ADDR[9]
|
||||
set_location_assignment PIN_AF2 -to SRAM_ADDR[10]
|
||||
set_location_assignment PIN_AD3 -to SRAM_ADDR[11]
|
||||
set_location_assignment PIN_AB4 -to SRAM_ADDR[12]
|
||||
set_location_assignment PIN_AC3 -to SRAM_ADDR[13]
|
||||
set_location_assignment PIN_AA4 -to SRAM_ADDR[14]
|
||||
set_location_assignment PIN_AB11 -to SRAM_ADDR[15]
|
||||
set_location_assignment PIN_AC11 -to SRAM_ADDR[16]
|
||||
set_location_assignment PIN_AB9 -to SRAM_ADDR[17]
|
||||
set_location_assignment PIN_AB8 -to SRAM_ADDR[18]
|
||||
set_location_assignment PIN_T8 -to SRAM_ADDR[19]
|
||||
set_location_assignment PIN_AH3 -to SRAM_DQ[0]
|
||||
set_location_assignment PIN_AF4 -to SRAM_DQ[1]
|
||||
set_location_assignment PIN_AG4 -to SRAM_DQ[2]
|
||||
set_location_assignment PIN_AH4 -to SRAM_DQ[3]
|
||||
set_location_assignment PIN_AF6 -to SRAM_DQ[4]
|
||||
set_location_assignment PIN_AG6 -to SRAM_DQ[5]
|
||||
set_location_assignment PIN_AH6 -to SRAM_DQ[6]
|
||||
set_location_assignment PIN_AF7 -to SRAM_DQ[7]
|
||||
set_location_assignment PIN_AD1 -to SRAM_DQ[8]
|
||||
set_location_assignment PIN_AD2 -to SRAM_DQ[9]
|
||||
set_location_assignment PIN_AE2 -to SRAM_DQ[10]
|
||||
set_location_assignment PIN_AE1 -to SRAM_DQ[11]
|
||||
set_location_assignment PIN_AE3 -to SRAM_DQ[12]
|
||||
set_location_assignment PIN_AE4 -to SRAM_DQ[13]
|
||||
set_location_assignment PIN_AF3 -to SRAM_DQ[14]
|
||||
set_location_assignment PIN_AG3 -to SRAM_DQ[15]
|
||||
set_location_assignment PIN_AC4 -to SRAM_UB_N
|
||||
set_location_assignment PIN_AD4 -to SRAM_LB_N
|
||||
set_location_assignment PIN_AF8 -to SRAM_CE_N
|
||||
set_location_assignment PIN_AD5 -to SRAM_OE_N
|
||||
set_location_assignment PIN_AE8 -to SRAM_WE_N
|
||||
set_location_assignment PIN_AG12 -to FL_ADDR[0]
|
||||
set_location_assignment PIN_AH7 -to FL_ADDR[1]
|
||||
set_location_assignment PIN_Y13 -to FL_ADDR[2]
|
||||
set_location_assignment PIN_Y14 -to FL_ADDR[3]
|
||||
set_location_assignment PIN_Y12 -to FL_ADDR[4]
|
||||
set_location_assignment PIN_AA13 -to FL_ADDR[5]
|
||||
set_location_assignment PIN_AA12 -to FL_ADDR[6]
|
||||
set_location_assignment PIN_AB13 -to FL_ADDR[7]
|
||||
set_location_assignment PIN_AB12 -to FL_ADDR[8]
|
||||
set_location_assignment PIN_AB10 -to FL_ADDR[9]
|
||||
set_location_assignment PIN_AE9 -to FL_ADDR[10]
|
||||
set_location_assignment PIN_AF9 -to FL_ADDR[11]
|
||||
set_location_assignment PIN_AA10 -to FL_ADDR[12]
|
||||
set_location_assignment PIN_AD8 -to FL_ADDR[13]
|
||||
set_location_assignment PIN_AC8 -to FL_ADDR[14]
|
||||
set_location_assignment PIN_Y10 -to FL_ADDR[15]
|
||||
set_location_assignment PIN_AA8 -to FL_ADDR[16]
|
||||
set_location_assignment PIN_AH12 -to FL_ADDR[17]
|
||||
set_location_assignment PIN_AC12 -to FL_ADDR[18]
|
||||
set_location_assignment PIN_AD12 -to FL_ADDR[19]
|
||||
set_location_assignment PIN_AE10 -to FL_ADDR[20]
|
||||
set_location_assignment PIN_AD10 -to FL_ADDR[21]
|
||||
set_location_assignment PIN_AD11 -to FL_ADDR[22]
|
||||
set_location_assignment PIN_AH8 -to FL_DQ[0]
|
||||
set_location_assignment PIN_AF10 -to FL_DQ[1]
|
||||
set_location_assignment PIN_AG10 -to FL_DQ[2]
|
||||
set_location_assignment PIN_AH10 -to FL_DQ[3]
|
||||
set_location_assignment PIN_AF11 -to FL_DQ[4]
|
||||
set_location_assignment PIN_AG11 -to FL_DQ[5]
|
||||
set_location_assignment PIN_AH11 -to FL_DQ[6]
|
||||
set_location_assignment PIN_AF12 -to FL_DQ[7]
|
||||
set_location_assignment PIN_AG7 -to FL_CE_N
|
||||
set_location_assignment PIN_AG8 -to FL_OE_N
|
||||
set_location_assignment PIN_AE11 -to FL_RST_N
|
||||
set_location_assignment PIN_Y1 -to FL_RY
|
||||
set_location_assignment PIN_AC10 -to FL_WE_N
|
||||
set_location_assignment PIN_AE12 -to FL_WP_N
|
||||
set_location_assignment PIN_AB22 -to GPIO[0]
|
||||
set_location_assignment PIN_AC15 -to GPIO[1]
|
||||
set_location_assignment PIN_AB21 -to GPIO[2]
|
||||
set_location_assignment PIN_Y17 -to GPIO[3]
|
||||
set_location_assignment PIN_AC21 -to GPIO[4]
|
||||
set_location_assignment PIN_Y16 -to GPIO[5]
|
||||
set_location_assignment PIN_AD21 -to GPIO[6]
|
||||
set_location_assignment PIN_AE16 -to GPIO[7]
|
||||
set_location_assignment PIN_AD15 -to GPIO[8]
|
||||
set_location_assignment PIN_AE15 -to GPIO[9]
|
||||
set_location_assignment PIN_AC19 -to GPIO[10]
|
||||
set_location_assignment PIN_AF16 -to GPIO[11]
|
||||
set_location_assignment PIN_AD19 -to GPIO[12]
|
||||
set_location_assignment PIN_AF15 -to GPIO[13]
|
||||
set_location_assignment PIN_AF24 -to GPIO[14]
|
||||
set_location_assignment PIN_AE21 -to GPIO[15]
|
||||
set_location_assignment PIN_AF25 -to GPIO[16]
|
||||
set_location_assignment PIN_AC22 -to GPIO[17]
|
||||
set_location_assignment PIN_AE22 -to GPIO[18]
|
||||
set_location_assignment PIN_AF21 -to GPIO[19]
|
||||
set_location_assignment PIN_AF22 -to GPIO[20]
|
||||
set_location_assignment PIN_AD22 -to GPIO[21]
|
||||
set_location_assignment PIN_AG25 -to GPIO[22]
|
||||
set_location_assignment PIN_AD25 -to GPIO[23]
|
||||
set_location_assignment PIN_AH25 -to GPIO[24]
|
||||
set_location_assignment PIN_AE25 -to GPIO[25]
|
||||
set_location_assignment PIN_AG22 -to GPIO[26]
|
||||
set_location_assignment PIN_AE24 -to GPIO[27]
|
||||
set_location_assignment PIN_AH22 -to GPIO[28]
|
||||
set_location_assignment PIN_AF26 -to GPIO[29]
|
||||
set_location_assignment PIN_AE20 -to GPIO[30]
|
||||
set_location_assignment PIN_AG23 -to GPIO[31]
|
||||
set_location_assignment PIN_AF20 -to GPIO[32]
|
||||
set_location_assignment PIN_AH26 -to GPIO[33]
|
||||
set_location_assignment PIN_AH23 -to GPIO[34]
|
||||
set_location_assignment PIN_AG26 -to GPIO[35]
|
||||
set_location_assignment PIN_AH15 -to HSMC_CLKIN0
|
||||
set_location_assignment PIN_AD28 -to HSMC_CLKOUT0
|
||||
set_location_assignment PIN_AE26 -to HSMC_D[0]
|
||||
set_location_assignment PIN_AE28 -to HSMC_D[1]
|
||||
set_location_assignment PIN_AE27 -to HSMC_D[2]
|
||||
set_location_assignment PIN_AF27 -to HSMC_D[3]
|
||||
set_location_assignment PIN_J27 -to HSMC_CLKIN_P1
|
||||
set_location_assignment PIN_J28 -to HSMC_CLKIN_N1
|
||||
set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1
|
||||
set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1
|
||||
set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2
|
||||
set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2
|
||||
set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2
|
||||
set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2
|
||||
set_location_assignment PIN_D27 -to HSMC_TX_D_P[0]
|
||||
set_location_assignment PIN_D28 -to HSMC_TX_D_N[0]
|
||||
set_location_assignment PIN_E27 -to HSMC_TX_D_P[1]
|
||||
set_location_assignment PIN_E28 -to HSMC_TX_D_N[1]
|
||||
set_location_assignment PIN_F27 -to HSMC_TX_D_P[2]
|
||||
set_location_assignment PIN_F28 -to HSMC_TX_D_N[2]
|
||||
set_location_assignment PIN_G27 -to HSMC_TX_D_P[3]
|
||||
set_location_assignment PIN_G28 -to HSMC_TX_D_N[3]
|
||||
set_location_assignment PIN_K27 -to HSMC_TX_D_P[4]
|
||||
set_location_assignment PIN_K28 -to HSMC_TX_D_N[4]
|
||||
set_location_assignment PIN_M27 -to HSMC_TX_D_P[5]
|
||||
set_location_assignment PIN_M28 -to HSMC_TX_D_N[5]
|
||||
set_location_assignment PIN_K21 -to HSMC_TX_D_P[6]
|
||||
set_location_assignment PIN_K22 -to HSMC_TX_D_N[6]
|
||||
set_location_assignment PIN_H23 -to HSMC_TX_D_P[7]
|
||||
set_location_assignment PIN_H24 -to HSMC_TX_D_N[7]
|
||||
set_location_assignment PIN_J23 -to HSMC_TX_D_P[8]
|
||||
set_location_assignment PIN_J24 -to HSMC_TX_D_N[8]
|
||||
set_location_assignment PIN_P27 -to HSMC_TX_D_P[9]
|
||||
set_location_assignment PIN_P28 -to HSMC_TX_D_N[9]
|
||||
set_location_assignment PIN_J25 -to HSMC_TX_D_P[10]
|
||||
set_location_assignment PIN_J26 -to HSMC_TX_D_N[10]
|
||||
set_location_assignment PIN_L27 -to HSMC_TX_D_P[11]
|
||||
set_location_assignment PIN_L28 -to HSMC_TX_D_N[11]
|
||||
set_location_assignment PIN_V25 -to HSMC_TX_D_P[12]
|
||||
set_location_assignment PIN_V26 -to HSMC_TX_D_N[12]
|
||||
set_location_assignment PIN_R27 -to HSMC_TX_D_P[13]
|
||||
set_location_assignment PIN_R28 -to HSMC_TX_D_N[13]
|
||||
set_location_assignment PIN_U27 -to HSMC_TX_D_P[14]
|
||||
set_location_assignment PIN_U28 -to HSMC_TX_D_N[14]
|
||||
set_location_assignment PIN_V27 -to HSMC_TX_D_P[15]
|
||||
set_location_assignment PIN_V28 -to HSMC_TX_D_N[15]
|
||||
set_location_assignment PIN_U22 -to HSMC_TX_D_P[16]
|
||||
set_location_assignment PIN_V22 -to HSMC_TX_D_N[16]
|
||||
set_location_assignment PIN_F24 -to HSMC_RX_D_P[0]
|
||||
set_location_assignment PIN_F25 -to HSMC_RX_D_N[0]
|
||||
set_location_assignment PIN_D26 -to HSMC_RX_D_P[1]
|
||||
set_location_assignment PIN_C27 -to HSMC_RX_D_N[1]
|
||||
set_location_assignment PIN_F26 -to HSMC_RX_D_P[2]
|
||||
set_location_assignment PIN_E26 -to HSMC_RX_D_N[2]
|
||||
set_location_assignment PIN_G25 -to HSMC_RX_D_P[3]
|
||||
set_location_assignment PIN_G26 -to HSMC_RX_D_N[3]
|
||||
set_location_assignment PIN_H25 -to HSMC_RX_D_P[4]
|
||||
set_location_assignment PIN_H26 -to HSMC_RX_D_N[4]
|
||||
set_location_assignment PIN_K25 -to HSMC_RX_D_P[5]
|
||||
set_location_assignment PIN_K26 -to HSMC_RX_D_N[5]
|
||||
set_location_assignment PIN_L23 -to HSMC_RX_D_P[6]
|
||||
set_location_assignment PIN_L24 -to HSMC_RX_D_N[6]
|
||||
set_location_assignment PIN_M25 -to HSMC_RX_D_P[7]
|
||||
set_location_assignment PIN_M26 -to HSMC_RX_D_N[7]
|
||||
set_location_assignment PIN_R25 -to HSMC_RX_D_P[8]
|
||||
set_location_assignment PIN_R26 -to HSMC_RX_D_N[8]
|
||||
set_location_assignment PIN_T25 -to HSMC_RX_D_P[9]
|
||||
set_location_assignment PIN_T26 -to HSMC_RX_D_N[9]
|
||||
set_location_assignment PIN_U25 -to HSMC_RX_D_P[10]
|
||||
set_location_assignment PIN_U26 -to HSMC_RX_D_N[10]
|
||||
set_location_assignment PIN_L21 -to HSMC_RX_D_P[11]
|
||||
set_location_assignment PIN_L22 -to HSMC_RX_D_N[11]
|
||||
set_location_assignment PIN_N25 -to HSMC_RX_D_P[12]
|
||||
set_location_assignment PIN_N26 -to HSMC_RX_D_N[12]
|
||||
set_location_assignment PIN_P25 -to HSMC_RX_D_P[13]
|
||||
set_location_assignment PIN_P26 -to HSMC_RX_D_N[13]
|
||||
set_location_assignment PIN_P21 -to HSMC_RX_D_P[14]
|
||||
set_location_assignment PIN_R21 -to HSMC_RX_D_N[14]
|
||||
set_location_assignment PIN_R22 -to HSMC_RX_D_P[15]
|
||||
set_location_assignment PIN_R23 -to HSMC_RX_D_N[15]
|
||||
set_location_assignment PIN_T21 -to HSMC_RX_D_P[16]
|
||||
set_location_assignment PIN_T22 -to HSMC_RX_D_N[16]
|
||||
set_location_assignment PIN_J10 -to EX_IO[0]
|
||||
set_location_assignment PIN_J14 -to EX_IO[1]
|
||||
set_location_assignment PIN_H13 -to EX_IO[2]
|
||||
set_location_assignment PIN_H14 -to EX_IO[3]
|
||||
set_location_assignment PIN_F14 -to EX_IO[4]
|
||||
set_location_assignment PIN_E10 -to EX_IO[5]
|
||||
set_location_assignment PIN_D9 -to EX_IO[6]
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
# Date created = 21:28:47 March 07, 2023
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Mux2_1Demo_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE115F29C7
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Mux2_1Demo
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:28:47 MARCH 07, 2023"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
|
||||
set_global_assignment -name VHDL_FILE Mux2_1.vhd
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Mux2_1.vwf
|
||||
set_global_assignment -name BDF_FILE Mux2_1Demo.bdf
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,7 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678227226957 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227226957 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:13:46 2023 " "Processing started: Tue Mar 7 22:13:46 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678227226957 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1678227226957 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Mux2_1Demo -c Mux2_1Demo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Mux2_1Demo -c Mux2_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1678227226957 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1678227227081 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1678227228548 ""}
|
||||
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1678227228621 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "365 " "Peak virtual memory: 365 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678227228804 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:13:48 2023 " "Processing ended: Tue Mar 7 22:13:48 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678227228804 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678227228804 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678227228804 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1678227228804 ""}
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,5 @@
|
|||
<?xml version="1.0" ?>
|
||||
<LOG_ROOT>
|
||||
<PROJECT NAME="Mux2_1Demo">
|
||||
</PROJECT>
|
||||
</LOG_ROOT>
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,46 @@
|
|||
v1
|
||||
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
|
||||
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
|
||||
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
|
||||
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
|
||||
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042,
|
||||
IO_RULES_MATRIX,Total Pass,0;4;4;0;0;4;4;0;0;0;0;0;0;1;0;0;0;3;1;0;3;0;0;1;0;4;4;4;0;0,
|
||||
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,Total Inapplicable,4;0;0;4;4;0;0;4;4;4;4;4;4;3;4;4;4;1;3;4;1;4;4;3;4;0;0;0;4;4,
|
||||
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,LEDG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_SUMMARY,Total I/O Rules,30,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Passed,12,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18,
|
||||
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|
|
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|
|||
Quartus_Version = Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
Version_Index = 520278016
|
||||
Creation_Time = Tue Mar 7 22:20:46 2023
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678227272079 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2020 Intel Corporation. All rights reserved. " "Copyright (C) 2020 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and any partner logic " "and other software and tools, and any partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors. Please " "Intel and sold by Intel or its authorized distributors. Please" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details, at " "refer to the applicable agreement for further details, at" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "https://fpgasoftware.intel.com/eula. " "https://fpgasoftware.intel.com/eula." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:14:31 2023 " "Processing started: Tue Mar 7 22:14:31 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678227272079 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678227272079 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/ Mux2_1Demo -c Mux2_1Demo " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim/ Mux2_1Demo -c Mux2_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1678227272079 ""}
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||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1678227272211 ""}
|
||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "Mux2_1Demo.vho /home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim// simulation " "Generated file Mux2_1Demo.vho in folder \"/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1678227272233 ""}
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||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "611 " "Peak virtual memory: 611 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678227272243 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:14:32 2023 " "Processing ended: Tue Mar 7 22:14:32 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678227272243 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678227272243 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678227272243 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1678227272243 ""}
|
||||
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|
|
@ -0,0 +1,14 @@
|
|||
|Mux2_1Demo
|
||||
LEDG[0] <= Mux2_1:inst.dataOut
|
||||
SW[0] => Mux2_1:inst.dataIn0
|
||||
SW[1] => Mux2_1:inst.dataIn1
|
||||
KEY[0] => Mux2_1:inst.sel
|
||||
|
||||
|
||||
|Mux2_1Demo|Mux2_1:inst
|
||||
dataIn0 => dataOut.DATAB
|
||||
dataIn1 => dataOut.DATAA
|
||||
sel => dataOut.OUTPUTSELECT
|
||||
dataOut <= dataOut.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
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|
|
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|
|||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >1</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
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|
|
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|
|||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; inst ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
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|
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|
|||
v1
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1678227215091 ""}
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||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1678227215092 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 7 22:13:35 2023 " "Processing started: Tue Mar 7 22:13:35 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1678227215092 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678227215092 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Mux2_1Demo -c Mux2_1Demo " "Command: quartus_map --read_settings_files=on --write_settings_files=off Mux2_1Demo -c Mux2_1Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678227215092 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1678227215218 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1678227215218 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux2_1.vhd 2 1 " "Found 2 design units, including 1 entities, in source file Mux2_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Mux2_1-Behavioral " "Found design unit 1: Mux2_1-Behavioral" { } { { "Mux2_1.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vhd" 14 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678227219814 ""} { "Info" "ISGN_ENTITY_NAME" "1 Mux2_1 " "Found entity 1: Mux2_1" { } { { "Mux2_1.vhd" "" { Text "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1.vhd" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678227219814 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678227219814 ""}
|
||||
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Mux2_1Demo.bdf 1 1 " "Found 1 design units, including 1 entities, in source file Mux2_1Demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Mux2_1Demo " "Found entity 1: Mux2_1Demo" { } { { "Mux2_1Demo.bdf" "" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1Demo.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1678227219814 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1678227219814 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_TOP" "Mux2_1Demo " "Elaborating entity \"Mux2_1Demo\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1678227219839 ""}
|
||||
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Mux2_1 Mux2_1:inst " "Elaborating entity \"Mux2_1\" for hierarchy \"Mux2_1:inst\"" { } { { "Mux2_1Demo.bdf" "inst" { Schematic "/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica02/Mux2_1/Mux2_1Demo.bdf" { { 192 480 640 304 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678227219840 ""}
|
||||
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1678227220171 ""}
|
||||
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1678227220468 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1678227220468 ""}
|
||||
{ "Info" "ICUT_CUT_TM_SUMMARY" "5 " "Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1678227220482 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1678227220482 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1678227220482 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1678227220482 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "431 " "Peak virtual memory: 431 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1678227220485 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 7 22:13:40 2023 " "Processing ended: Tue Mar 7 22:13:40 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1678227220485 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1678227220485 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1678227220485 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1678227220485 ""}
|
||||
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|
|||
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|
||||
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Reference in New Issue