[LSD] SeqShiftUnit_Demo added (pratica06 - part2)
This commit is contained in:
TiagoRG
parent
91e718e620
commit
7188967342
GPG Key ID:
DFCD48E3F420DB42
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@ -0,0 +1,50 @@
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
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/*
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Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 160 96)
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(text "FreqDivider" (rect 5 0 52 12)(font "Arial" ))
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(text "inst" (rect 8 64 20 76)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clkIn" (rect 0 0 17 12)(font "Arial" ))
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(text "clkIn" (rect 21 27 38 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 144 32)
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(output)
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(text "clkOut" (rect 0 0 24 12)(font "Arial" ))
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(text "clkOut" (rect 99 27 123 39)(font "Arial" ))
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(line (pt 144 32)(pt 128 32)(line_width 1))
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)
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(parameter
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"divFactor"
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"10"
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""
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(type "PARAMETER_SIGNED_DEC") )
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(drawing
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(rectangle (rect 16 16 128 64)(line_width 1))
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)
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(annotation_block (parameter)(rect 160 -64 260 16))
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)
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@ -0,0 +1,33 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity FreqDivider is
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generic(divFactor : positive := 10);
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port
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(
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clkIn : in std_logic;
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clkOut : out std_logic
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);
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end FreqDivider;
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architecture Behavioral of FreqDivider is
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subtype TCounter is natural range 0 to divFactor - 1;
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signal s_divCounter : TCounter := 0;
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begin
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assert(divFactor >= 2);
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process(clkIn)
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begin
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if (rising_edge(clkIn)) then
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if (s_divCounter >= (divFactor - 1)) then
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clkOut <= '0';
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s_divCounter <= 0;
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else
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if (s_divCounter = (divFactor / 2 - 1)) then
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clkOut <= '1';
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end if;
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s_divCounter <= s_divCounter + 1;
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end if;
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end if;
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end process;
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end Behavioral;
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@ -0,0 +1,93 @@
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
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||||
/*
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Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 208 192)
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(text "SeqShiftUnit" (rect 5 0 53 12)(font "Arial" ))
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(text "inst" (rect 8 160 20 172)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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(text "clk" (rect 0 0 10 12)(font "Arial" ))
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(text "clk" (rect 21 27 31 39)(font "Arial" ))
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(line (pt 0 32)(pt 16 32)(line_width 1))
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)
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(port
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(pt 0 48)
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(input)
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(text "dataIn[7..0]" (rect 0 0 43 12)(font "Arial" ))
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(text "dataIn[7..0]" (rect 21 43 64 55)(font "Arial" ))
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(line (pt 0 48)(pt 16 48)(line_width 3))
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)
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(port
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(pt 0 64)
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(input)
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(text "siLeft" (rect 0 0 22 12)(font "Arial" ))
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(text "siLeft" (rect 21 59 43 71)(font "Arial" ))
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(line (pt 0 64)(pt 16 64)(line_width 1))
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)
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(port
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(pt 0 80)
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(input)
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(text "siRight" (rect 0 0 27 12)(font "Arial" ))
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(text "siRight" (rect 21 75 48 87)(font "Arial" ))
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(line (pt 0 80)(pt 16 80)(line_width 1))
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)
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(port
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(pt 0 96)
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(input)
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(text "loadEn" (rect 0 0 27 12)(font "Arial" ))
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(text "loadEn" (rect 21 91 48 103)(font "Arial" ))
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(line (pt 0 96)(pt 16 96)(line_width 1))
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)
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(port
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(pt 0 112)
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(input)
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(text "rotate" (rect 0 0 22 12)(font "Arial" ))
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(text "rotate" (rect 21 107 43 119)(font "Arial" ))
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(line (pt 0 112)(pt 16 112)(line_width 1))
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)
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(port
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(pt 0 128)
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(input)
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(text "dirLeft" (rect 0 0 25 12)(font "Arial" ))
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(text "dirLeft" (rect 21 123 46 135)(font "Arial" ))
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(line (pt 0 128)(pt 16 128)(line_width 1))
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)
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(port
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(pt 0 144)
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(input)
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(text "shArith" (rect 0 0 29 12)(font "Arial" ))
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(text "shArith" (rect 21 139 50 151)(font "Arial" ))
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(line (pt 0 144)(pt 16 144)(line_width 1))
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)
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(port
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(pt 192 32)
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(output)
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(text "dataOut[7..0]" (rect 0 0 50 12)(font "Arial" ))
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(text "dataOut[7..0]" (rect 121 27 171 39)(font "Arial" ))
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(line (pt 192 32)(pt 176 32)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 176 160)(line_width 1))
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)
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)
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity SeqShiftUnit is
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port
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(
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clk : in std_logic;
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dataIn : in std_logic_vector(7 downto 0);
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siLeft : in std_logic;
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siRight : in std_logic;
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loadEn : in std_logic;
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rotate : in std_logic;
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dirLeft : in std_logic;
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shArith : in std_logic;
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dataOut : out std_logic_vector(7 downto 0)
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);
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end SeqShiftUnit;
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architecture Behavioral of SeqShiftUnit is
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signal s_shiftReg : std_logic_vector(7 downto 0);
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begin
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process (clk)
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begin
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if (falling_edge(clk)) then
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if (loadEn = '1') then
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s_shiftReg <= dataIn;
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elsif (rotate = '1') then
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if (dirLeft = '1') then
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s_shiftReg <= s_shiftReg(6 downto 0) & s_shiftReg(7);
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else
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s_shiftReg <= s_shiftReg(0) & s_shiftReg(7 downto 1);
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end if;
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elsif (shArith = '1') then
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if (dirLeft = '1') then
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s_shiftReg <= s_shiftReg(6 downto 0) & '0';
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else
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s_shiftReg <= s_shiftReg(7) & s_shiftReg(7 downto 1);
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end if;
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else
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if (dirLeft = '1') then
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s_shiftReg <= s_shiftReg(6 downto 0) & siLeft;
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else
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s_shiftReg <= siRight & s_shiftReg(7 downto 1);
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end if;
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end if;
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end if;
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end process;
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dataOut <= s_ShiftReg;
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end Behavioral;
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@ -0,0 +1,872 @@
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/*<simulation_settings>
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<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off SeqShiftUnit_Demo -c SeqShiftUnit_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/SeqShiftUnit.vwf.vht"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off SeqShiftUnit_Demo -c SeqShiftUnit_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/SeqShiftUnit.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/SeqShiftUnit.vwf.vht"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/" SeqShiftUnit_Demo -c SeqShiftUnit_Demo</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica06/SeqShiftUnit_Demo/simulation/qsim/" SeqShiftUnit_Demo -c SeqShiftUnit_Demo</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vcom -work work SeqShiftUnit_Demo.vho
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vcom -work work SeqShiftUnit.vwf.vht
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vsim -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.SeqShiftUnit_vhd_vec_tst
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vcd file -direction SeqShiftUnit_Demo.msim.vcd
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vcd add -internal SeqShiftUnit_vhd_vec_tst/*
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vcd add -internal SeqShiftUnit_vhd_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vcom -work work SeqShiftUnit_Demo.vho
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vcom -work work SeqShiftUnit.vwf.vht
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vsim -novopt -c -t 1ps -sdfmax SeqShiftUnit_vhd_vec_tst/i1=SeqShiftUnit_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.SeqShiftUnit_vhd_vec_tst
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vcd file -direction SeqShiftUnit_Demo.msim.vcd
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vcd add -internal SeqShiftUnit_vhd_vec_tst/*
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vcd add -internal SeqShiftUnit_vhd_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>vhdl</hdl_lang>
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</simulation_settings>*/
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/*
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||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("clk")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("dataIn")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 8;
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LSB_INDEX = 0;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("dataIn[7]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "dataIn";
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}
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SIGNAL("dataIn[6]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "dataIn";
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}
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SIGNAL("dataIn[5]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "dataIn";
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}
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SIGNAL("dataIn[4]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "dataIn";
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}
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SIGNAL("dataIn[3]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "dataIn";
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}
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SIGNAL("dataIn[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
|
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "dataIn";
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}
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SIGNAL("dataIn[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
|
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "dataIn";
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}
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SIGNAL("dataIn[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "dataIn";
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}
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SIGNAL("dirLeft")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
|
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WIDTH = 1;
|
||||
LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("loadEn")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
|
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WIDTH = 1;
|
||||
LSB_INDEX = -1;
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DIRECTION = INPUT;
|
||||
PARENT = "";
|
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}
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|
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SIGNAL("rotate")
|
||||
{
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VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
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SIGNAL("shArith")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
|
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SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
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||||
PARENT = "";
|
||||
}
|
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|
||||
SIGNAL("siLeft")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("siRight")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = INPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("dataOut")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = BUS;
|
||||
WIDTH = 8;
|
||||
LSB_INDEX = 0;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "";
|
||||
}
|
||||
|
||||
SIGNAL("dataOut[7]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "dataOut";
|
||||
}
|
||||
|
||||
SIGNAL("dataOut[6]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "dataOut";
|
||||
}
|
||||
|
||||
SIGNAL("dataOut[5]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "dataOut";
|
||||
}
|
||||
|
||||
SIGNAL("dataOut[4]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "dataOut";
|
||||
}
|
||||
|
||||
SIGNAL("dataOut[3]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "dataOut";
|
||||
}
|
||||
|
||||
SIGNAL("dataOut[2]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "dataOut";
|
||||
}
|
||||
|
||||
SIGNAL("dataOut[1]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "dataOut";
|
||||
}
|
||||
|
||||
SIGNAL("dataOut[0]")
|
||||
{
|
||||
VALUE_TYPE = NINE_LEVEL_BIT;
|
||||
SIGNAL_TYPE = SINGLE_BIT;
|
||||
WIDTH = 1;
|
||||
LSB_INDEX = -1;
|
||||
DIRECTION = OUTPUT;
|
||||
PARENT = "dataOut";
|
||||
}
|
||||
|
||||
TRANSITION_LIST("clk")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 100;
|
||||
LEVEL 0 FOR 5.0;
|
||||
LEVEL 1 FOR 5.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataIn[7]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataIn[6]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataIn[5]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataIn[4]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataIn[3]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataIn[2]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataIn[1]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataIn[0]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dirLeft")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 25;
|
||||
LEVEL 0 FOR 20.0;
|
||||
LEVEL 1 FOR 20.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("loadEn")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 50;
|
||||
LEVEL 0 FOR 10.0;
|
||||
LEVEL 1 FOR 10.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("rotate")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 12;
|
||||
LEVEL 0 FOR 40.0;
|
||||
LEVEL 1 FOR 40.0;
|
||||
}
|
||||
LEVEL 0 FOR 40.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("shArith")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 6;
|
||||
LEVEL 0 FOR 80.0;
|
||||
LEVEL 1 FOR 80.0;
|
||||
}
|
||||
LEVEL 0 FOR 40.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("siLeft")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 60.0;
|
||||
LEVEL 0 FOR 45.0;
|
||||
LEVEL 1 FOR 45.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 30.0;
|
||||
LEVEL 0 FOR 60.0;
|
||||
LEVEL 1 FOR 30.0;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 45.0;
|
||||
LEVEL 0 FOR 45.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 60.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 30.0;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 30.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 30.0;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 30.0;
|
||||
LEVEL 0 FOR 60.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 25.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("siRight")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 60.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 30.0;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 60.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 30.0;
|
||||
LEVEL 0 FOR 30.0;
|
||||
LEVEL 1 FOR 30.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 90.0;
|
||||
LEVEL 0 FOR 45.0;
|
||||
LEVEL 1 FOR 135.0;
|
||||
LEVEL 0 FOR 45.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 195.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 15.0;
|
||||
LEVEL 0 FOR 15.0;
|
||||
LEVEL 1 FOR 25.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataOut[7]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataOut[6]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataOut[5]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataOut[4]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataOut[3]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataOut[2]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataOut[1]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("dataOut[0]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "clk";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 0;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 1;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 2, 3, 4, 5, 6, 7, 8, 9;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn[7]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 2;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 1;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn[6]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 3;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 1;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn[5]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 4;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 1;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn[4]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 5;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 1;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn[3]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 6;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 1;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 7;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 1;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 8;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 1;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataIn[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 9;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 1;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "loadEn";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 10;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dirLeft";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 11;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "rotate";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 12;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "shArith";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 13;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "siLeft";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 14;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "siRight";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 15;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataOut";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 16;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 17, 18, 19, 20, 21, 22, 23, 24;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataOut[7]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 17;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 16;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataOut[6]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 18;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 16;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataOut[5]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 19;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 16;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataOut[4]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 20;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 16;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataOut[3]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 21;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 16;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataOut[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 22;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 16;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataOut[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 23;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 16;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "dataOut[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 24;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 16;
|
||||
}
|
||||
|
||||
TIME_BAR
|
||||
{
|
||||
TIME = 0;
|
||||
MASTER = TRUE;
|
||||
}
|
||||
;
|
||||
|
|
@ -0,0 +1,350 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
Your use of Intel Corporation's design tools, logic functions
|
||||
and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
|
||||
*/
|
||||
(header "graphic" (version "1.4"))
|
||||
(pin
|
||||
(input)
|
||||
(rect 96 208 264 224)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "CLOCK_50" (rect 5 0 63 11)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
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|
||||
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|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
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|
||||
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|
||||
)
|
||||
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|
||||
(input)
|
||||
(rect 96 224 264 240)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[7..0]" (rect 5 0 48 11)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 32 240 96 256))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 96 304 264 320)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[14]" (rect 5 0 43 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 32 320 96 336))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 96 256 264 272)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[15]" (rect 5 0 43 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 32 272 96 288))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 96 240 264 256)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[16]" (rect 5 0 42 11)(font "Arial" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 32 256 96 272))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 96 272 264 288)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[17]" (rect 5 0 44 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 24 288 96 304))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 96 288 264 304)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[11]" (rect 5 0 44 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 32 304 96 320))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 96 320 264 336)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[10]" (rect 5 0 44 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 24 336 96 352))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 96 336 264 352)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[13..12]" (rect 5 0 62 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 32 352 96 368))
|
||||
)
|
||||
(pin
|
||||
(input)
|
||||
(rect 96 352 264 368)
|
||||
(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
|
||||
(text "SW[9..8]" (rect 5 0 49 13)(font "Intel Clear" ))
|
||||
(pt 168 8)
|
||||
(drawing
|
||||
(line (pt 84 12)(pt 109 12))
|
||||
(line (pt 84 4)(pt 109 4))
|
||||
(line (pt 113 8)(pt 168 8))
|
||||
(line (pt 84 12)(pt 84 4))
|
||||
(line (pt 109 4)(pt 113 8))
|
||||
(line (pt 109 12)(pt 113 8))
|
||||
)
|
||||
(text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6)))
|
||||
(annotation_block (location)(rect 48 400 112 416))
|
||||
)
|
||||
(pin
|
||||
(output)
|
||||
(rect 624 208 800 224)
|
||||
(text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6)))
|
||||
(text "LEDR[7..0]" (rect 90 0 144 11)(font "Arial" ))
|
||||
(pt 0 8)
|
||||
(drawing
|
||||
(line (pt 0 8)(pt 52 8))
|
||||
(line (pt 52 4)(pt 78 4))
|
||||
(line (pt 52 12)(pt 78 12))
|
||||
(line (pt 52 12)(pt 52 4))
|
||||
(line (pt 78 4)(pt 82 8))
|
||||
(line (pt 82 8)(pt 78 12))
|
||||
(line (pt 78 12)(pt 82 8))
|
||||
)
|
||||
(annotation_block (location)(rect 800 224 864 240))
|
||||
)
|
||||
(symbol
|
||||
(rect 272 184 416 264)
|
||||
(text "FreqDivider" (rect 5 0 64 11)(font "Arial" ))
|
||||
(text "inst" (rect 8 64 26 75)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "clkIn" (rect 0 0 24 11)(font "Arial" ))
|
||||
(text "clkIn" (rect 21 27 45 38)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 144 32)
|
||||
(output)
|
||||
(text "clkOut" (rect 0 0 33 11)(font "Arial" ))
|
||||
(text "clkOut" (rect 96 27 129 38)(font "Arial" ))
|
||||
(line (pt 144 32)(pt 128 32))
|
||||
)
|
||||
(parameter
|
||||
"divFactor"
|
||||
"12500000"
|
||||
""
|
||||
(type "PARAMETER_SIGNED_DEC") )
|
||||
(drawing
|
||||
(rectangle (rect 16 16 128 64))
|
||||
)
|
||||
(annotation_block (parameter)(rect 416 152 610 182))
|
||||
)
|
||||
(symbol
|
||||
(rect 424 184 616 360)
|
||||
(text "SeqShiftUnit" (rect 5 0 67 11)(font "Arial" ))
|
||||
(text "inst1" (rect 8 160 32 171)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "clk" (rect 0 0 15 11)(font "Arial" ))
|
||||
(text "clk" (rect 21 27 36 38)(font "Arial" ))
|
||||
(line (pt 0 32)(pt 16 32))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "dataIn[7..0]" (rect 0 0 55 11)(font "Arial" ))
|
||||
(text "dataIn[7..0]" (rect 21 43 76 54)(font "Arial" ))
|
||||
(line (pt 0 48)(pt 16 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "siLeft" (rect 0 0 28 11)(font "Arial" ))
|
||||
(text "siLeft" (rect 21 59 49 70)(font "Arial" ))
|
||||
(line (pt 0 64)(pt 16 64))
|
||||
)
|
||||
(port
|
||||
(pt 0 80)
|
||||
(input)
|
||||
(text "siRight" (rect 0 0 35 11)(font "Arial" ))
|
||||
(text "siRight" (rect 21 75 56 86)(font "Arial" ))
|
||||
(line (pt 0 80)(pt 16 80))
|
||||
)
|
||||
(port
|
||||
(pt 0 96)
|
||||
(input)
|
||||
(text "loadEn" (rect 0 0 36 11)(font "Arial" ))
|
||||
(text "loadEn" (rect 21 91 57 102)(font "Arial" ))
|
||||
(line (pt 0 96)(pt 16 96))
|
||||
)
|
||||
(port
|
||||
(pt 0 112)
|
||||
(input)
|
||||
(text "rotate" (rect 0 0 29 11)(font "Arial" ))
|
||||
(text "rotate" (rect 21 107 50 118)(font "Arial" ))
|
||||
(line (pt 0 112)(pt 16 112))
|
||||
)
|
||||
(port
|
||||
(pt 0 128)
|
||||
(input)
|
||||
(text "dirLeft" (rect 0 0 31 11)(font "Arial" ))
|
||||
(text "dirLeft" (rect 21 123 52 134)(font "Arial" ))
|
||||
(line (pt 0 128)(pt 16 128))
|
||||
)
|
||||
(port
|
||||
(pt 0 144)
|
||||
(input)
|
||||
(text "shArith" (rect 0 0 35 11)(font "Arial" ))
|
||||
(text "shArith" (rect 21 139 56 150)(font "Arial" ))
|
||||
(line (pt 0 144)(pt 16 144))
|
||||
)
|
||||
(port
|
||||
(pt 192 32)
|
||||
(output)
|
||||
(text "dataOut[7..0]" (rect 0 0 63 11)(font "Arial" ))
|
||||
(text "dataOut[7..0]" (rect 118 27 181 38)(font "Arial" ))
|
||||
(line (pt 192 32)(pt 176 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(rectangle (rect 16 16 176 160))
|
||||
)
|
||||
)
|
||||
(connector
|
||||
(pt 424 216)
|
||||
(pt 416 216)
|
||||
)
|
||||
(connector
|
||||
(pt 272 216)
|
||||
(pt 264 216)
|
||||
)
|
||||
(connector
|
||||
(pt 424 232)
|
||||
(pt 264 232)
|
||||
(bus)
|
||||
)
|
||||
(connector
|
||||
(pt 424 248)
|
||||
(pt 264 248)
|
||||
)
|
||||
(connector
|
||||
(pt 424 264)
|
||||
(pt 264 264)
|
||||
)
|
||||
(connector
|
||||
(pt 424 280)
|
||||
(pt 264 280)
|
||||
)
|
||||
(connector
|
||||
(pt 424 296)
|
||||
(pt 264 296)
|
||||
)
|
||||
(connector
|
||||
(pt 424 312)
|
||||
(pt 264 312)
|
||||
)
|
||||
(connector
|
||||
(pt 424 328)
|
||||
(pt 264 328)
|
||||
)
|
||||
(connector
|
||||
(pt 616 216)
|
||||
(pt 624 216)
|
||||
(bus)
|
||||
)
|
||||
Binary file not shown.
Loading…
Reference in New Issue