From 715510bcb383376085983faafddfcb2cf9dc3167 Mon Sep 17 00:00:00 2001 From: TiagoRG <35657250+TiagoRG@users.noreply.github.com> Date: Tue, 21 Mar 2023 22:41:33 +0000 Subject: [PATCH] [LSD] pratica05 part1 added --- .../lsd/pratica05/CmpN_Demo/Cmp8.vwf | 733 +++++ .../lsd/pratica05/CmpN_Demo/CmpN.bsf | 78 + .../lsd/pratica05/CmpN_Demo/CmpN.vhd | 24 + .../lsd/pratica05/CmpN_Demo/CmpN.vhd.bak | 21 + .../lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf | 390 +++ .../lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf | 31 + .../lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf | 585 ++++ .../lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak | 585 ++++ .../lsd/pratica05/CmpN_Demo/CmpN_Demo.qws | Bin 0 -> 2491 bytes .../CmpN_Demo/db/CmpN_Demo.(0).cnf.cdb | Bin 0 -> 1298 bytes .../CmpN_Demo/db/CmpN_Demo.(0).cnf.hdb | Bin 0 -> 859 bytes .../CmpN_Demo/db/CmpN_Demo.(1).cnf.cdb | Bin 0 -> 1333 bytes .../CmpN_Demo/db/CmpN_Demo.(1).cnf.hdb | Bin 0 -> 765 bytes .../CmpN_Demo/db/CmpN_Demo.(2).cnf.cdb | Bin 0 -> 1328 bytes .../CmpN_Demo/db/CmpN_Demo.(2).cnf.hdb | Bin 0 -> 868 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.asm.qmsg | 7 + .../pratica05/CmpN_Demo/db/CmpN_Demo.asm.rdb | Bin 0 -> 824 bytes .../CmpN_Demo/db/CmpN_Demo.asm_labs.ddb | Bin 0 -> 89331 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml | 5 + .../pratica05/CmpN_Demo/db/CmpN_Demo.cmp.bpm | Bin 0 -> 836 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.cmp.cdb | Bin 0 -> 8229 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.cmp.hdb | Bin 0 -> 27249 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.cmp.idb | Bin 0 -> 1325 bytes .../CmpN_Demo/db/CmpN_Demo.cmp.logdb | 68 + .../pratica05/CmpN_Demo/db/CmpN_Demo.cmp.rdb | Bin 0 -> 32374 bytes .../CmpN_Demo/db/CmpN_Demo.cmp_merge.kpt | Bin 0 -> 208 bytes ...ve_io_sim_cache.45um_ff_1200mv_0c_fast.hsd | Bin 0 -> 746429 bytes ...ve_io_sim_cache.45um_ii_1200mv_0c_slow.hsd | Bin 0 -> 749613 bytes ...e_io_sim_cache.45um_ii_1200mv_85c_slow.hsd | Bin 0 -> 749512 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.db_info | 3 + .../pratica05/CmpN_Demo/db/CmpN_Demo.eda.qmsg | 6 + .../pratica05/CmpN_Demo/db/CmpN_Demo.fit.qmsg | 48 + .../CmpN_Demo/db/CmpN_Demo.hier_info | 97 + .../lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hif | Bin 0 -> 509 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.lpc.html | 50 + .../pratica05/CmpN_Demo/db/CmpN_Demo.lpc.rdb | Bin 0 -> 466 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.lpc.txt | 8 + .../CmpN_Demo/db/CmpN_Demo.map.ammdb | Bin 0 -> 129 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.map.bpm | Bin 0 -> 811 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.map.cdb | Bin 0 -> 3970 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.map.hdb | Bin 0 -> 26344 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.map.kpt | Bin 0 -> 207 bytes .../CmpN_Demo/db/CmpN_Demo.map.logdb | 1 + .../pratica05/CmpN_Demo/db/CmpN_Demo.map.qmsg | 14 + .../pratica05/CmpN_Demo/db/CmpN_Demo.map.rdb | Bin 0 -> 1336 bytes .../CmpN_Demo/db/CmpN_Demo.map_bb.cdb | Bin 0 -> 2178 bytes .../CmpN_Demo/db/CmpN_Demo.map_bb.hdb | Bin 0 -> 24948 bytes .../CmpN_Demo/db/CmpN_Demo.map_bb.logdb | 1 + .../CmpN_Demo/db/CmpN_Demo.pre_map.hdb | Bin 0 -> 25909 bytes .../CmpN_Demo.root_partition.map.reg_db.cdb | Bin 0 -> 223 bytes .../CmpN_Demo/db/CmpN_Demo.routing.rdb | Bin 0 -> 31584 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.rtlv.hdb | Bin 0 -> 25766 bytes .../CmpN_Demo/db/CmpN_Demo.rtlv_sg.cdb | Bin 0 -> 2359 bytes .../CmpN_Demo/db/CmpN_Demo.rtlv_sg_swap.cdb | Bin 0 -> 835 bytes .../db/CmpN_Demo.sld_design_entry.sci | Bin 0 -> 225 bytes .../db/CmpN_Demo.sld_design_entry_dsc.sci | Bin 0 -> 225 bytes .../CmpN_Demo/db/CmpN_Demo.smart_action.txt | 1 + .../pratica05/CmpN_Demo/db/CmpN_Demo.sta.qmsg | 49 + .../pratica05/CmpN_Demo/db/CmpN_Demo.sta.rdb | Bin 0 -> 6693 bytes .../CmpN_Demo.sta_cmp.7_slow_1200mv_85c.tdb | Bin 0 -> 6914 bytes .../CmpN_Demo/db/CmpN_Demo.tis_db_list.ddb | Bin 0 -> 294 bytes .../db/CmpN_Demo.tiscmp.fast_1200mv_0c.ddb | Bin 0 -> 120861 bytes .../db/CmpN_Demo.tiscmp.slow_1200mv_0c.ddb | Bin 0 -> 121280 bytes .../db/CmpN_Demo.tiscmp.slow_1200mv_85c.ddb | Bin 0 -> 120936 bytes .../pratica05/CmpN_Demo/db/CmpN_Demo.tmw_info | 7 + .../CmpN_Demo/db/CmpN_Demo.vpr.ammdb | Bin 0 -> 313 bytes .../db/CmpN_Demo_partition_pins.json | 113 + .../CmpN_Demo/db/prev_cmp_CmpN_Demo.qmsg | 140 + .../pratica05/CmpN_Demo/incremental_db/README | 11 + .../compiled_partitions/CmpN_Demo.db_info | 3 + .../CmpN_Demo.root_partition.cmp.ammdb | Bin 0 -> 275 bytes .../CmpN_Demo.root_partition.cmp.cdb | Bin 0 -> 5106 bytes .../CmpN_Demo.root_partition.cmp.dfp | Bin 0 -> 33 bytes .../CmpN_Demo.root_partition.cmp.hdb | Bin 0 -> 25906 bytes .../CmpN_Demo.root_partition.cmp.logdb | 1 + .../CmpN_Demo.root_partition.cmp.rcfdb | Bin 0 -> 3950 bytes .../CmpN_Demo.root_partition.map.cdb | Bin 0 -> 3551 bytes .../CmpN_Demo.root_partition.map.dpi | Bin 0 -> 865 bytes .../CmpN_Demo.root_partition.map.hbdb.cdb | Bin 0 -> 1597 bytes .../CmpN_Demo.root_partition.map.hbdb.hb_info | Bin 0 -> 46 bytes .../CmpN_Demo.root_partition.map.hbdb.hdb | Bin 0 -> 25197 bytes .../CmpN_Demo.root_partition.map.hbdb.sig | 1 + .../CmpN_Demo.root_partition.map.hdb | Bin 0 -> 24883 bytes .../CmpN_Demo.root_partition.map.kpt | Bin 0 -> 209 bytes .../compiled_partitions/CmpN_Demo.rrp.hdb | Bin 0 -> 27183 bytes .../CmpN_Demo/output_files/CmpN_Demo.asm.rpt | 92 + .../CmpN_Demo/output_files/CmpN_Demo.cdf | 13 + .../CmpN_Demo/output_files/CmpN_Demo.done | 1 + .../CmpN_Demo/output_files/CmpN_Demo.eda.rpt | 94 + .../CmpN_Demo/output_files/CmpN_Demo.fit.rpt | 2622 +++++++++++++++++ .../CmpN_Demo/output_files/CmpN_Demo.fit.smsg | 8 + .../output_files/CmpN_Demo.fit.summary | 16 + .../CmpN_Demo/output_files/CmpN_Demo.flow.rpt | 136 + .../CmpN_Demo/output_files/CmpN_Demo.jdi | 8 + .../CmpN_Demo/output_files/CmpN_Demo.map.rpt | 314 ++ .../output_files/CmpN_Demo.map.summary | 14 + .../CmpN_Demo/output_files/CmpN_Demo.pin | 851 ++++++ .../CmpN_Demo/output_files/CmpN_Demo.sld | 1 + .../CmpN_Demo/output_files/CmpN_Demo.sof | Bin 0 -> 3541729 bytes .../CmpN_Demo/output_files/CmpN_Demo.sta.rpt | 521 ++++ .../output_files/CmpN_Demo.sta.summary | 5 + .../simulation/modelsim/CmpN_Demo.sft | 1 + .../simulation/modelsim/CmpN_Demo.vho | 773 +++++ .../modelsim/CmpN_Demo_modelsim.xrf | 53 + .../CmpN_Demo/simulation/qsim/Cmp8.vwf.vht | 226 ++ .../CmpN_Demo/simulation/qsim/CmpN_Demo.do | 17 + .../CmpN_Demo/simulation/qsim/CmpN_Demo.sft | 1 + .../CmpN_Demo/simulation/qsim/CmpN_Demo.vho | 663 +++++ .../simulation/qsim/CmpN_Demo_modelsim.xrf | 50 + .../CmpN_Demo/simulation/qsim/transcript | 23 + .../CmpN_Demo/simulation/qsim/work/_info | 60 + .../CmpN_Demo/simulation/qsim/work/_lib.qdb | Bin 0 -> 49152 bytes .../simulation/qsim/work/_lib1_0.qdb | Bin 0 -> 32768 bytes .../simulation/qsim/work/_lib1_0.qpg | Bin 0 -> 237568 bytes .../simulation/qsim/work/_lib1_0.qtl | Bin 0 -> 8549 bytes .../CmpN_Demo/simulation/qsim/work/_vmake | 4 + 116 files changed, 9648 insertions(+) create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.bsf create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd.bak create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qws create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(0).cnf.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(0).cnf.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(1).cnf.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(1).cnf.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(2).cnf.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(2).cnf.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.qmsg create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.rdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm_labs.ddb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.bpm create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.idb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.logdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.rdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp_merge.kpt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.db_info create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.eda.qmsg create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.fit.qmsg create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hier_info create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.hif create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.html create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.rdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.lpc.txt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.ammdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.bpm create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.kpt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.logdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.qmsg create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map.rdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map_bb.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map_bb.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.map_bb.logdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.pre_map.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.root_partition.map.reg_db.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.routing.rdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.rtlv.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.rtlv_sg.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.rtlv_sg_swap.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sld_design_entry.sci create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sld_design_entry_dsc.sci create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.smart_action.txt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta.qmsg create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta.rdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.sta_cmp.7_slow_1200mv_85c.tdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tis_db_list.ddb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.fast_1200mv_0c.ddb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.slow_1200mv_0c.ddb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tiscmp.slow_1200mv_85c.ddb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.tmw_info create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.vpr.ammdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo_partition_pins.json create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/db/prev_cmp_CmpN_Demo.qmsg create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/README create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.db_info create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.ammdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.dfp create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.logdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.cmp.rcfdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.dpi create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.cdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.hb_info create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hbdb.sig create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.root_partition.map.kpt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/incremental_db/compiled_partitions/CmpN_Demo.rrp.hdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.asm.rpt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.cdf create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.done create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.eda.rpt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.rpt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.smsg create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.fit.summary create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.flow.rpt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.jdi create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.map.rpt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.map.summary create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.pin create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sld create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sof create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sta.rpt create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/output_files/CmpN_Demo.sta.summary create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.sft create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo.vho create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/modelsim/CmpN_Demo_modelsim.xrf create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.do create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.sft create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo.vho create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/CmpN_Demo_modelsim.xrf create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/transcript create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_info create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_lib.qdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_lib1_0.qdb create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_lib1_0.qpg create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_lib1_0.qtl create mode 100644 1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/work/_vmake diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf new file mode 100644 index 0000000..4cf750b --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf @@ -0,0 +1,733 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CmpN_Demo -c CmpN_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht" +quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off CmpN_Demo -c CmpN_Demo --vector_source="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/Cmp8.vwf" --testbench_file="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/Cmp8.vwf.vht" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/" CmpN_Demo -c CmpN_Demo +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/tiagorg/repos/uaveiro-leci/1ano/2semestre/lsd/pratica05/CmpN_Demo/simulation/qsim/" CmpN_Demo -c CmpN_Demo +onerror {exit -code 1} +vlib work +vcom -work work CmpN_Demo.vho +vcom work Cmp8.vwf.vht +vsim -novopt -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CmpN_vhd_vec_tst +vcd file -direction CmpN_Demo.msim.vcd +vcd add -internal CmpN_vhd_vec_tst/* +vcd add -internal CmpN_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vcom -work work CmpN_Demo.vho +vcom -work work Cmp8.vwf.vht +vsim -novopt -c -t 1ps -sdfmax CmpN_vhd_vec_tst/i1=CmpN_Demo_vhd.sdo -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.CmpN_vhd_vec_tst +vcd file -direction CmpN_Demo.msim.vcd +vcd add -internal CmpN_vhd_vec_tst/* +vcd add -internal CmpN_vhd_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +vhdl +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("equal") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("input0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("input0[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input0[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input0"; +} + +SIGNAL("input1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("input1[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("input1[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "input1"; +} + +SIGNAL("ltSigned") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("ltUnsigned") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("notEqual") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("equal") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("input0[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 840.0; + } +} + +TRANSITION_LIST("input0[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input0[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input1[7]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 760.0; + } +} + +TRANSITION_LIST("input1[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("input1[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 920.0; + } +} + +TRANSITION_LIST("ltSigned") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("ltUnsigned") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("notEqual") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "input0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input0[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "input1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; + CHILDREN = 10, 11, 12, 13, 14, 15, 16, 17; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "input1[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "equal"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "notEqual"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ltSigned"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "ltUnsigned"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.bsf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.bsf new file mode 100644 index 0000000..d3a6149 --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.bsf @@ -0,0 +1,78 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 208 128) + (text "CmpN" (rect 5 0 32 12)(font "Arial" )) + (text "inst" (rect 8 96 20 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "input0[n-1..0]" (rect 0 0 48 12)(font "Arial" )) + (text "input0[n-1..0]" (rect 21 27 69 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "input1[n-1..0]" (rect 0 0 47 12)(font "Arial" )) + (text "input1[n-1..0]" (rect 21 43 68 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 192 32) + (output) + (text "equal" (rect 0 0 20 12)(font "Arial" )) + (text "equal" (rect 151 27 171 39)(font "Arial" )) + (line (pt 192 32)(pt 176 32)(line_width 1)) + ) + (port + (pt 192 48) + (output) + (text "notEqual" (rect 0 0 34 12)(font "Arial" )) + (text "notEqual" (rect 137 43 171 55)(font "Arial" )) + (line (pt 192 48)(pt 176 48)(line_width 1)) + ) + (port + (pt 192 64) + (output) + (text "ltSigned" (rect 0 0 29 12)(font "Arial" )) + (text "ltSigned" (rect 142 59 171 71)(font "Arial" )) + (line (pt 192 64)(pt 176 64)(line_width 1)) + ) + (port + (pt 192 80) + (output) + (text "ltUnsigned" (rect 0 0 40 12)(font "Arial" )) + (text "ltUnsigned" (rect 131 75 171 87)(font "Arial" )) + (line (pt 192 80)(pt 176 80)(line_width 1)) + ) + (parameter + "N" + "4" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 176 96)(line_width 1)) + ) + (annotation_block (parameter)(rect 208 -64 308 16)) +) diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd new file mode 100644 index 0000000..deed67d --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd @@ -0,0 +1,24 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity CmpN is + generic (N : positive := 4); + port + ( + input0 : in std_logic_vector((N-1) downto 0); + input1 : in std_logic_vector((N-1) downto 0); + equal : out std_logic; + notEqual : out std_logic; + ltSigned : out std_logic; + ltUnsigned : out std_logic + ); +end CmpN; + +architecture Behavioral of CmpN is +begin + equal <= '1' when (input0 = input1) else '0'; + notEqual <= '1' when (input0 /= input1) else '0'; + ltSigned <= '1' when (signed(input0) < signed(input1)) else '0'; + ltUnsigned <= '1' when (unsigned(input0) < unsigned(input1)) else '0'; +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd.bak b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd.bak new file mode 100644 index 0000000..1193ba4 --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN.vhd.bak @@ -0,0 +1,21 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.NUMERIC_STD.all; + +entity Cmp4 is + port( + input0 : in std_logic_vector(3 downto 0); + input1 : in std_logic_vector(3 downto 0); + equal : out std_logic; + notEqual : out std_logic; + ltSigned : out std_logic; + ltUnsigned : out std_logic); +end Cmp4; + +architecture Behavioral of Cmp4 is +begin + equal <= '1' when (input0 = input1) else '0'; + notEqual <= '1' when (input0 /= input1) else '0'; + ltSigned <= '1' when (signed(input0) < signed(input1)) else '0'; + ltUnsigned <= '1' when (unsigned(input0) < unsigned(input1)) else '0'; +end Behavioral; \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf new file mode 100644 index 0000000..7ef32f1 --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.bdf @@ -0,0 +1,390 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2020 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 424 240 592 256) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[7..4]" (rect 5 0 47 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 360 256 424 272)) +) +(pin + (input) + (rect 424 256 592 272) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[3..0]" (rect 5 0 48 13)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 360 272 424 288)) +) +(pin + (input) + (rect 424 408 592 424) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[17..13]" (rect 5 0 62 13)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 232 472 296 488)) +) +(pin + (input) + (rect 424 424 592 440) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "SW[12..8]" (rect 5 0 56 13)(font "Intel Clear" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 232 488 296 504)) +) +(pin + (output) + (rect 800 240 976 256) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDG[0]" (rect 90 0 132 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 984 256 1048 272)) +) +(pin + (output) + (rect 800 256 976 272) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDG[1]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 976 272 1032 288)) +) +(pin + (output) + (rect 800 272 976 288) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDG[2]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 976 288 1032 304)) +) +(pin + (output) + (rect 800 288 976 304) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDG[3]" (rect 90 0 132 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 976 304 1032 320)) +) +(pin + (output) + (rect 800 408 976 424) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDR[0]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 856 472 920 488)) +) +(pin + (output) + (rect 800 424 976 440) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDR[1]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 848 488 904 504)) +) +(pin + (output) + (rect 800 440 976 456) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDR[2]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 848 504 904 520)) +) +(pin + (output) + (rect 800 456 976 472) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "LEDR[3]" (rect 90 0 132 13)(font "Intel Clear" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 848 520 904 536)) +) +(symbol + (rect 600 216 792 328) + (text "CmpN" (rect 5 0 36 11)(font "Arial" )) + (text "inst" (rect 8 96 26 107)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "input0[n-1..0]" (rect 0 0 64 11)(font "Arial" )) + (text "input0[n-1..0]" (rect 21 27 85 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "input1[n-1..0]" (rect 0 0 64 11)(font "Arial" )) + (text "input1[n-1..0]" (rect 21 43 85 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 192 32) + (output) + (text "equal" (rect 0 0 28 11)(font "Arial" )) + (text "equal" (rect 148 27 176 38)(font "Arial" )) + (line (pt 192 32)(pt 176 32)) + ) + (port + (pt 192 48) + (output) + (text "notEqual" (rect 0 0 44 11)(font "Arial" )) + (text "notEqual" (rect 134 43 178 54)(font "Arial" )) + (line (pt 192 48)(pt 176 48)) + ) + (port + (pt 192 64) + (output) + (text "ltSigned" (rect 0 0 41 11)(font "Arial" )) + (text "ltSigned" (rect 137 59 178 70)(font "Arial" )) + (line (pt 192 64)(pt 176 64)) + ) + (port + (pt 192 80) + (output) + (text "ltUnsigned" (rect 0 0 54 11)(font "Arial" )) + (text "ltUnsigned" (rect 126 75 180 86)(font "Arial" )) + (line (pt 192 80)(pt 176 80)) + ) + (parameter + "N" + "4" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 176 96)) + ) + (annotation_block (parameter)(rect 792 184 963 214)) +) +(symbol + (rect 600 384 792 496) + (text "CmpN" (rect 5 0 36 11)(font "Arial" )) + (text "inst3" (rect 8 96 32 109)(font "Intel Clear" )) + (port + (pt 0 32) + (input) + (text "input0[n-1..0]" (rect 0 0 64 11)(font "Arial" )) + (text "input0[n-1..0]" (rect 21 27 85 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "input1[n-1..0]" (rect 0 0 64 11)(font "Arial" )) + (text "input1[n-1..0]" (rect 21 43 85 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 192 32) + (output) + (text "equal" (rect 0 0 28 11)(font "Arial" )) + (text "equal" (rect 148 27 176 38)(font "Arial" )) + (line (pt 192 32)(pt 176 32)) + ) + (port + (pt 192 48) + (output) + (text "notEqual" (rect 0 0 44 11)(font "Arial" )) + (text "notEqual" (rect 134 43 178 54)(font "Arial" )) + (line (pt 192 48)(pt 176 48)) + ) + (port + (pt 192 64) + (output) + (text "ltSigned" (rect 0 0 41 11)(font "Arial" )) + (text "ltSigned" (rect 137 59 178 70)(font "Arial" )) + (line (pt 192 64)(pt 176 64)) + ) + (port + (pt 192 80) + (output) + (text "ltUnsigned" (rect 0 0 54 11)(font "Arial" )) + (text "ltUnsigned" (rect 126 75 180 86)(font "Arial" )) + (line (pt 192 80)(pt 176 80)) + ) + (parameter + "N" + "5" + "" + (type "PARAMETER_SIGNED_DEC") ) + (drawing + (rectangle (rect 16 16 176 96)) + ) + (annotation_block (parameter)(rect 792 352 963 382)) +) +(connector + (pt 600 248) + (pt 592 248) + (bus) +) +(connector + (pt 600 264) + (pt 592 264) + (bus) +) +(connector + (pt 792 264) + (pt 800 264) +) +(connector + (pt 792 280) + (pt 800 280) +) +(connector + (pt 792 296) + (pt 800 296) +) +(connector + (pt 792 248) + (pt 800 248) +) +(connector + (pt 600 416) + (pt 592 416) + (bus) +) +(connector + (pt 600 432) + (pt 592 432) + (bus) +) +(connector + (pt 792 432) + (pt 800 432) +) +(connector + (pt 792 448) + (pt 800 448) +) +(connector + (pt 792 464) + (pt 800 464) +) +(connector + (pt 792 416) + (pt 800 416) +) diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf new file mode 100644 index 0000000..e3f2c0d --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 11:22:49 March 17, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "20.1" +DATE = "11:22:49 March 17, 2023" + +# Revisions + +PROJECT_REVISION = "CmpN_Demo" diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf new file mode 100644 index 0000000..646af9b --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf @@ -0,0 +1,585 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 11:22:49 March 17, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# CmpN_Demo_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name TOP_LEVEL_ENTITY CmpN_Demo +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:22:49 MARCH 17, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name VECTOR_WAVEFORM_FILE Cmp8.vwf +set_global_assignment -name VHDL_FILE CmpN.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name BDF_FILE CmpN_Demo.bdf +set_location_assignment PIN_Y2 -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_location_assignment PIN_M23 -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_location_assignment PIN_AB28 -to SW[0] +set_location_assignment PIN_AC28 -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_location_assignment PIN_AB26 -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_location_assignment PIN_G19 -to LEDR[0] +set_location_assignment PIN_F19 -to LEDR[1] +set_location_assignment PIN_E19 -to LEDR[2] +set_location_assignment PIN_F21 -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_location_assignment PIN_E21 -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_location_assignment PIN_G18 -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_location_assignment PIN_E17 -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_location_assignment PIN_M24 -to HEX1[0] +set_location_assignment PIN_Y22 -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_location_assignment PIN_AA25 -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_location_assignment PIN_W27 -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_location_assignment PIN_V21 -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_location_assignment PIN_AB19 -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_location_assignment PIN_AG17 -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_location_assignment PIN_L6 -to LCD_BLON +set_location_assignment PIN_M1 -to LCD_RW +set_location_assignment PIN_L4 -to LCD_EN +set_location_assignment PIN_M2 -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_location_assignment PIN_G9 -to UART_TXD +set_location_assignment PIN_G12 -to UART_RXD +set_location_assignment PIN_G14 -to UART_CTS +set_location_assignment PIN_J13 -to UART_RTS +set_location_assignment PIN_G6 -to PS2_CLK +set_location_assignment PIN_H5 -to PS2_DAT +set_location_assignment PIN_G5 -to PS2_CLK2 +set_location_assignment PIN_F5 -to PS2_DAT2 +set_location_assignment PIN_AE13 -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_location_assignment PIN_AF14 -to SD_WP_N +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_location_assignment PIN_G13 -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_A12 -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_location_assignment PIN_E12 -to VGA_R[0] +set_location_assignment PIN_E11 -to VGA_R[1] +set_location_assignment PIN_D10 -to VGA_R[2] +set_location_assignment PIN_F12 -to VGA_R[3] +set_location_assignment PIN_G10 -to VGA_R[4] +set_location_assignment PIN_J12 -to VGA_R[5] +set_location_assignment PIN_H8 -to VGA_R[6] +set_location_assignment PIN_H10 -to VGA_R[7] +set_location_assignment PIN_G8 -to VGA_G[0] +set_location_assignment PIN_G11 -to VGA_G[1] +set_location_assignment PIN_F8 -to VGA_G[2] +set_location_assignment PIN_H12 -to VGA_G[3] +set_location_assignment PIN_C8 -to VGA_G[4] +set_location_assignment PIN_B8 -to VGA_G[5] +set_location_assignment PIN_F10 -to VGA_G[6] +set_location_assignment PIN_C9 -to VGA_G[7] +set_location_assignment PIN_B10 -to VGA_B[0] +set_location_assignment PIN_A10 -to VGA_B[1] +set_location_assignment PIN_C11 -to VGA_B[2] +set_location_assignment PIN_B11 -to VGA_B[3] +set_location_assignment PIN_A11 -to VGA_B[4] +set_location_assignment PIN_C12 -to VGA_B[5] +set_location_assignment PIN_D11 -to VGA_B[6] +set_location_assignment PIN_D12 -to VGA_B[7] +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_location_assignment PIN_D1 -to AUD_DACDAT +set_location_assignment PIN_E1 -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_location_assignment PIN_B7 -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_location_assignment PIN_A14 -to ENETCLK_25 +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_location_assignment PIN_C19 -to ENET0_RST_N +set_location_assignment PIN_C20 -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_location_assignment PIN_A21 -to ENET0_INT_N +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_location_assignment PIN_D22 -to ENET1_RST_N +set_location_assignment PIN_D23 -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_location_assignment PIN_D24 -to ENET1_INT_N +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_location_assignment PIN_E5 -to TD_HS +set_location_assignment PIN_E4 -to TD_VS +set_location_assignment PIN_B14 -to TD_CLK27 +set_location_assignment PIN_G7 -to TD_RESET_N +set_location_assignment PIN_E8 -to TD_DATA[0] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_location_assignment PIN_F7 -to TD_DATA[7] +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_location_assignment PIN_A3 -to OTG_CS_N +set_location_assignment PIN_A4 -to OTG_WR_N +set_location_assignment PIN_B3 -to OTG_RD_N +set_location_assignment PIN_D5 -to OTG_INT +set_location_assignment PIN_C5 -to OTG_RST_N +set_location_assignment PIN_Y15 -to IRDA_RXD +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_location_assignment PIN_AE5 -to DRAM_CLK +set_location_assignment PIN_V6 -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_location_assignment PIN_AG7 -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_location_assignment PIN_Y1 -to FL_RY +set_location_assignment PIN_AC10 -to FL_WE_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_location_assignment PIN_AB22 -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_location_assignment PIN_AD15 -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_location_assignment PIN_AC19 -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_location_assignment PIN_AH23 -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_location_assignment PIN_J10 -to EX_IO[0] +set_location_assignment PIN_J14 -to EX_IO[1] +set_location_assignment PIN_H13 -to EX_IO[2] +set_location_assignment PIN_H14 -to EX_IO[3] +set_location_assignment PIN_F14 -to EX_IO[4] +set_location_assignment PIN_E10 -to EX_IO[5] +set_location_assignment PIN_D9 -to EX_IO[6] +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak new file mode 100644 index 0000000..646af9b --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qsf.bak @@ -0,0 +1,585 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 11:22:49 March 17, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# CmpN_Demo_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name TOP_LEVEL_ENTITY CmpN_Demo +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:22:49 MARCH 17, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name VECTOR_WAVEFORM_FILE Cmp8.vwf +set_global_assignment -name VHDL_FILE CmpN.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name BDF_FILE CmpN_Demo.bdf +set_location_assignment PIN_Y2 -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_location_assignment PIN_M23 -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_location_assignment PIN_AB28 -to SW[0] +set_location_assignment PIN_AC28 -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_location_assignment PIN_AB26 -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_location_assignment PIN_G19 -to LEDR[0] +set_location_assignment PIN_F19 -to LEDR[1] +set_location_assignment PIN_E19 -to LEDR[2] +set_location_assignment PIN_F21 -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_location_assignment PIN_E21 -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_location_assignment PIN_G18 -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_location_assignment PIN_E17 -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_location_assignment PIN_M24 -to HEX1[0] +set_location_assignment PIN_Y22 -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_location_assignment PIN_AA25 -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_location_assignment PIN_W27 -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_location_assignment PIN_V21 -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_location_assignment PIN_AB19 -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_location_assignment PIN_AG17 -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_location_assignment PIN_L6 -to LCD_BLON +set_location_assignment PIN_M1 -to LCD_RW +set_location_assignment PIN_L4 -to LCD_EN +set_location_assignment PIN_M2 -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_location_assignment PIN_G9 -to UART_TXD +set_location_assignment PIN_G12 -to UART_RXD +set_location_assignment PIN_G14 -to UART_CTS +set_location_assignment PIN_J13 -to UART_RTS +set_location_assignment PIN_G6 -to PS2_CLK +set_location_assignment PIN_H5 -to PS2_DAT +set_location_assignment PIN_G5 -to PS2_CLK2 +set_location_assignment PIN_F5 -to PS2_DAT2 +set_location_assignment PIN_AE13 -to SD_CLK +set_location_assignment PIN_AD14 -to SD_CMD +set_location_assignment PIN_AF14 -to SD_WP_N +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_location_assignment PIN_G13 -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_A12 -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_location_assignment PIN_E12 -to VGA_R[0] +set_location_assignment PIN_E11 -to VGA_R[1] +set_location_assignment PIN_D10 -to VGA_R[2] +set_location_assignment PIN_F12 -to VGA_R[3] +set_location_assignment PIN_G10 -to VGA_R[4] +set_location_assignment PIN_J12 -to VGA_R[5] +set_location_assignment PIN_H8 -to VGA_R[6] +set_location_assignment PIN_H10 -to VGA_R[7] +set_location_assignment PIN_G8 -to VGA_G[0] +set_location_assignment PIN_G11 -to VGA_G[1] +set_location_assignment PIN_F8 -to VGA_G[2] +set_location_assignment PIN_H12 -to VGA_G[3] +set_location_assignment PIN_C8 -to VGA_G[4] +set_location_assignment PIN_B8 -to VGA_G[5] +set_location_assignment PIN_F10 -to VGA_G[6] +set_location_assignment PIN_C9 -to VGA_G[7] +set_location_assignment PIN_B10 -to VGA_B[0] +set_location_assignment PIN_A10 -to VGA_B[1] +set_location_assignment PIN_C11 -to VGA_B[2] +set_location_assignment PIN_B11 -to VGA_B[3] +set_location_assignment PIN_A11 -to VGA_B[4] +set_location_assignment PIN_C12 -to VGA_B[5] +set_location_assignment PIN_D11 -to VGA_B[6] +set_location_assignment PIN_D12 -to VGA_B[7] +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_location_assignment PIN_D1 -to AUD_DACDAT +set_location_assignment PIN_E1 -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_location_assignment PIN_B7 -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_location_assignment PIN_A14 -to ENETCLK_25 +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_location_assignment PIN_C19 -to ENET0_RST_N +set_location_assignment PIN_C20 -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_location_assignment PIN_A21 -to ENET0_INT_N +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_location_assignment PIN_D22 -to ENET1_RST_N +set_location_assignment PIN_D23 -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_location_assignment PIN_D24 -to ENET1_INT_N +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_location_assignment PIN_E5 -to TD_HS +set_location_assignment PIN_E4 -to TD_VS +set_location_assignment PIN_B14 -to TD_CLK27 +set_location_assignment PIN_G7 -to TD_RESET_N +set_location_assignment PIN_E8 -to TD_DATA[0] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_location_assignment PIN_F7 -to TD_DATA[7] +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_location_assignment PIN_J1 -to OTG_DREQ[0] +set_location_assignment PIN_A3 -to OTG_CS_N +set_location_assignment PIN_A4 -to OTG_WR_N +set_location_assignment PIN_B3 -to OTG_RD_N +set_location_assignment PIN_D5 -to OTG_INT +set_location_assignment PIN_C5 -to OTG_RST_N +set_location_assignment PIN_Y15 -to IRDA_RXD +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_location_assignment PIN_AE5 -to DRAM_CLK +set_location_assignment PIN_V6 -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_location_assignment PIN_AG7 -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_location_assignment PIN_Y1 -to FL_RY +set_location_assignment PIN_AC10 -to FL_WE_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_location_assignment PIN_AB22 -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_location_assignment PIN_AD15 -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_location_assignment PIN_AC19 -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_location_assignment PIN_AH23 -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] +set_location_assignment PIN_AH15 -to HSMC_CLKIN0 +set_location_assignment PIN_AD28 -to HSMC_CLKOUT0 +set_location_assignment PIN_AE26 -to HSMC_D[0] +set_location_assignment PIN_AE28 -to HSMC_D[1] +set_location_assignment PIN_AE27 -to HSMC_D[2] +set_location_assignment PIN_AF27 -to HSMC_D[3] +set_location_assignment PIN_J27 -to HSMC_CLKIN_P1 +set_location_assignment PIN_J28 -to HSMC_CLKIN_N1 +set_location_assignment PIN_G23 -to HSMC_CLKOUT_P1 +set_location_assignment PIN_G24 -to HSMC_CLKOUT_N1 +set_location_assignment PIN_Y27 -to HSMC_CLKIN_P2 +set_location_assignment PIN_Y28 -to HSMC_CLKIN_N2 +set_location_assignment PIN_V23 -to HSMC_CLKOUT_P2 +set_location_assignment PIN_V24 -to HSMC_CLKOUT_N2 +set_location_assignment PIN_D27 -to HSMC_TX_D_P[0] +set_location_assignment PIN_D28 -to HSMC_TX_D_N[0] +set_location_assignment PIN_E27 -to HSMC_TX_D_P[1] +set_location_assignment PIN_E28 -to HSMC_TX_D_N[1] +set_location_assignment PIN_F27 -to HSMC_TX_D_P[2] +set_location_assignment PIN_F28 -to HSMC_TX_D_N[2] +set_location_assignment PIN_G27 -to HSMC_TX_D_P[3] +set_location_assignment PIN_G28 -to HSMC_TX_D_N[3] +set_location_assignment PIN_K27 -to HSMC_TX_D_P[4] +set_location_assignment PIN_K28 -to HSMC_TX_D_N[4] +set_location_assignment PIN_M27 -to HSMC_TX_D_P[5] +set_location_assignment PIN_M28 -to HSMC_TX_D_N[5] +set_location_assignment PIN_K21 -to HSMC_TX_D_P[6] +set_location_assignment PIN_K22 -to HSMC_TX_D_N[6] +set_location_assignment PIN_H23 -to HSMC_TX_D_P[7] +set_location_assignment PIN_H24 -to HSMC_TX_D_N[7] +set_location_assignment PIN_J23 -to HSMC_TX_D_P[8] +set_location_assignment PIN_J24 -to HSMC_TX_D_N[8] +set_location_assignment PIN_P27 -to HSMC_TX_D_P[9] +set_location_assignment PIN_P28 -to HSMC_TX_D_N[9] +set_location_assignment PIN_J25 -to HSMC_TX_D_P[10] +set_location_assignment PIN_J26 -to HSMC_TX_D_N[10] +set_location_assignment PIN_L27 -to HSMC_TX_D_P[11] +set_location_assignment PIN_L28 -to HSMC_TX_D_N[11] +set_location_assignment PIN_V25 -to HSMC_TX_D_P[12] +set_location_assignment PIN_V26 -to HSMC_TX_D_N[12] +set_location_assignment PIN_R27 -to HSMC_TX_D_P[13] +set_location_assignment PIN_R28 -to HSMC_TX_D_N[13] +set_location_assignment PIN_U27 -to HSMC_TX_D_P[14] +set_location_assignment PIN_U28 -to HSMC_TX_D_N[14] +set_location_assignment PIN_V27 -to HSMC_TX_D_P[15] +set_location_assignment PIN_V28 -to HSMC_TX_D_N[15] +set_location_assignment PIN_U22 -to HSMC_TX_D_P[16] +set_location_assignment PIN_V22 -to HSMC_TX_D_N[16] +set_location_assignment PIN_F24 -to HSMC_RX_D_P[0] +set_location_assignment PIN_F25 -to HSMC_RX_D_N[0] +set_location_assignment PIN_D26 -to HSMC_RX_D_P[1] +set_location_assignment PIN_C27 -to HSMC_RX_D_N[1] +set_location_assignment PIN_F26 -to HSMC_RX_D_P[2] +set_location_assignment PIN_E26 -to HSMC_RX_D_N[2] +set_location_assignment PIN_G25 -to HSMC_RX_D_P[3] +set_location_assignment PIN_G26 -to HSMC_RX_D_N[3] +set_location_assignment PIN_H25 -to HSMC_RX_D_P[4] +set_location_assignment PIN_H26 -to HSMC_RX_D_N[4] +set_location_assignment PIN_K25 -to HSMC_RX_D_P[5] +set_location_assignment PIN_K26 -to HSMC_RX_D_N[5] +set_location_assignment PIN_L23 -to HSMC_RX_D_P[6] +set_location_assignment PIN_L24 -to HSMC_RX_D_N[6] +set_location_assignment PIN_M25 -to HSMC_RX_D_P[7] +set_location_assignment PIN_M26 -to HSMC_RX_D_N[7] +set_location_assignment PIN_R25 -to HSMC_RX_D_P[8] +set_location_assignment PIN_R26 -to HSMC_RX_D_N[8] +set_location_assignment PIN_T25 -to HSMC_RX_D_P[9] +set_location_assignment PIN_T26 -to HSMC_RX_D_N[9] +set_location_assignment PIN_U25 -to HSMC_RX_D_P[10] +set_location_assignment PIN_U26 -to HSMC_RX_D_N[10] +set_location_assignment PIN_L21 -to HSMC_RX_D_P[11] +set_location_assignment PIN_L22 -to HSMC_RX_D_N[11] +set_location_assignment PIN_N25 -to HSMC_RX_D_P[12] +set_location_assignment PIN_N26 -to HSMC_RX_D_N[12] +set_location_assignment PIN_P25 -to HSMC_RX_D_P[13] +set_location_assignment PIN_P26 -to HSMC_RX_D_N[13] +set_location_assignment PIN_P21 -to HSMC_RX_D_P[14] +set_location_assignment PIN_R21 -to HSMC_RX_D_N[14] +set_location_assignment PIN_R22 -to HSMC_RX_D_P[15] +set_location_assignment PIN_R23 -to HSMC_RX_D_N[15] +set_location_assignment PIN_T21 -to HSMC_RX_D_P[16] +set_location_assignment PIN_T22 -to HSMC_RX_D_N[16] +set_location_assignment PIN_J10 -to EX_IO[0] +set_location_assignment PIN_J14 -to EX_IO[1] +set_location_assignment PIN_H13 -to EX_IO[2] +set_location_assignment PIN_H14 -to EX_IO[3] +set_location_assignment PIN_F14 -to EX_IO[4] +set_location_assignment PIN_E10 -to EX_IO[5] +set_location_assignment PIN_D9 -to EX_IO[6] +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qws b/1ano/2semestre/lsd/pratica05/CmpN_Demo/CmpN_Demo.qws new file mode 100644 index 0000000000000000000000000000000000000000..4c432a4df447e6831f993cdcb012142f326a9c31 GIT binary patch literal 2491 zcmds(J#Q015QgWD$g-$XA&4ka0J4y5@Nt$CiYVf%K!^g-P+9i*9IV9HIEF+*5tPvK z8)&Hb6Ygke5lHzL2nj=Y-u0d3*ij;^(0Hx=nAw@x*_n6eyq>ePU9>H$+P3wqVmsEh zu5Chf;6)ZAbcP>weS%%@-B1~K0EY}szPi1modGpNVRZ6a60^R7hgfTlTV zi*^sym@7ymvdyD}@XXY6_J}-e5Z4(_l3^LS! z1&0dB8$1Cq*;IhA`u&NDd-`zVUan;>aNLuW;@CgxqFqr}8B_5JlOm=sW}dPX0+^%V zq=GgHrx58PP~1x|<$c2Z2sG~bfFyWcf8Z*<%2JMRe1~uSbH3TC+7WX-38wx7G@&-| lp_l6SQHt~qvD1|;==lJlZa6at{~vVx*F?{{^+(nk@hT literal 0 HcmV?d00001 diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(0).cnf.cdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(0).cnf.cdb new file mode 100644 index 0000000000000000000000000000000000000000..cc6e36bc09664e21fa86ec1526e680ce11b43698 GIT binary patch literal 1298 zcmV+t1?~D2000233jqKC0001M0BZm=00011WpZ4R5H!?6F zF)=SOF)uPOGB6-hN+3*WbY&n#WNCD1Z*EBs00000004Od000000052x0000000000 z000sN00000004La?3T@IQ$Y~GUo>j{0!2{|A|4c^c*s*w(Nm;7L~I*s0!ok&HE1BD zO46%;j{kuFgn01a!DEl!y@>c#=eP6b?Y{RC+aw+ooHE^=@7bBzmn}z8bR@x(vQC4d zp29xamE>EX)U z9=%vhi_K0y)tsi22gPczF@^QUY&*ZJt57EFe>wwjsU6DrAZHTnm4R^97={Q+TL z%=h1ry?(=$J}xNrsJSb=RBcq-wbcogaBbtX_EWhid;KtIN0D6<{FzpZ2r?uBp`Bx- zKeR>JitChWU6AE{;!i(CzPiYu)>Sp3lpr1mNXL6;`)ZC5#-_F;Xp3YJidh}6j zU#0fmC;mbV`(XVs`QIe_BxeD>Y=3jZy&&h<68dX^H-#6{+>ld(z-3*c1G2goK_xnt zu-vV`7`mJSLb;dJ@JM7n2`bz+yt*?GA^HXPrST58(vLvRX)65fMI7af^lK z>J#4ZT#n|r$S@igy0UX2YGL@^&V2Lhn=rVb3;+}BGdnKC zF0=tOGpz}Y@tkUM!8C4^y1<9-tDD^<7g5w zibj>3Dk^72z6Z9^**yPvr4~f!BPvi{vqa)ys=mG)wtjxWrd$b>8D{M+Om{ z9(n;+;=0iX8T3obw@)MqO&s~d69wI9E9r*>hVO^p>IhatyX?0{LY7PxfJfZ?VD#mL z1h5a|v~Qm$2yqNYn(u3NIZ~v^b3$IylnhG=I%4ui9ts?rnvKU7`XPavJqMCeT99P; zol3{}H#KC@sUv;%g=*Ek%2suAW4uz`4_j;2+;bx~V+b@RNL-b3Oc*SUBQnGM I0ssL2|4vq24gdfE literal 0 HcmV?d00001 diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(0).cnf.hdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(0).cnf.hdb new file mode 100644 index 0000000000000000000000000000000000000000..4d6221d29ee50077882fc04baa4900af33c6f488 GIT binary patch literal 859 zcmV-h1El;E000233jqKC0001M0BZm=00011WpZ4R5H!?6F zF)=SOF)uPOGB6-hN+3*WbY&n#WNCD1Z*GDI00000007$o00000003G70000000000 z003J900000004La>{L5X!$1r^-p_%7fsF+z3!pPB3~UIAp<;oGs!@kZjcBD1ikk4_ zS-{^pm-wnfVj@Dql4E~<+?{>#ts9{o7TZ7IRgT%OnT0uKKIo7SdG8};&?fWAH*Cy` z1k8$gRoYX;GqF*bDKKxaD|@TPxkV5YYIjX4Udy;6FBh}tBAWymyPTDmRS|KSH7v>G z69jpPOF=}^Pn;Ntup&srP{fmno`^dUX9<=-k%Q)Ap%FgAh|R?r)5XqwBBuYHP4XM} z+;O)t6f%nG7slwCQ6owXD4LF) zZ(ip2=kL?W7XSbN|NnRaT#-9V13?hSHxKiUF}@9gX#~;IM$*XU+}xey9_(%)S8bzc znn27IT4`tLC-56s2^OjS3}PoXK0vUy5ob2ZC3x^>_GW(kXLqJVVx&z7dF=IWVi4n? zd5|z&)$|N1Z4VB%ka02xX|>aT&qB;iVGa|5noKcQ@*qK~P#Of=x9F4rErHO@0W&XNTfkU z(9p%JA2LH`$rfa+)30(0B3k4l0{i6j;F_!7_mCzyymC}GJQrR_ZCB>C%f7LDfpbHb zm58F8(?Ctw0e8vC( literal 0 HcmV?d00001 diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(1).cnf.cdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(1).cnf.cdb new file mode 100644 index 0000000000000000000000000000000000000000..74cb4287ec2a4ff7fc5441403225e7ddff9d5cf4 GIT binary patch literal 1333 zcmV-514R5H!?6F zF)=SOF)uPOGB6-hN+3*WbY&n#WNCD1Z*Bk?00000004*s00000006%N0000000000 z001=w00000004La>{#1w6EP6olyXNra2MhcBqVs~(v)(00h%HtNTW94qNs{0QBWXk z3r&T@$M6|^0H47J@PGu5h^LlwJhs=nNw!^Yl@civjpLn}W6zAoPP~&r5S##C1fLla zV;W17=#}s}q9rAKUr@3jxTIwV^fzsuROTKvr8`&@+Y5Hw&R>3!!fnLf`g7 zAC_7R^;Tn*=1IDNdsdr)dzPDld)AwQdlsC5dsdu*dzPGmJ2iKftLISG8KckGMRUrO zf~{N&Z}FZhZ}FZ>Z}HCBJE5ysc%G!`%3YI{xd*MM_g}OY8uePE-l{Du)?4+LwF-Y6 zp-PL>fq>qAB@IDP~$Cz;r#&sb3#%C|M+e&_d zciwX@M*91MS(%-{^yk6)RDE1c9IB^9lai`G!NC^~Srr0?8WlGAxp}zGN*Wa~kW|8wDNX8{{YDgLI=3Umiby@xTWC z1tWCzmg776TN%tZBCHRSE0eEl8~}6-{P6vH^-eq5=*m&a7dTgQGRzhDIy<0);7@BG z-|-JL4{Vn>b{W|JaB)u(dxvB;u7J}@x7Rj(M^s5T~AAQ?R z4qU&>h{MV1Jv=hJQ<}~5A1oi)JexQAFpKffD^fy^LgGk2A!ZR2Wi=ogdXgUNHRP_$ z*wWLlDf_pO{Z7eTY@YtJ)V$^&*gpUO0RR7Z0c=stD+F;Eep%n^n}d9Zd}Xx`%3+h= z%>LRP?anYW%2Iw3v8j!G zt)d*7C8CbG{^cBSE>I0PF;kh+O&E@=r0LqJTq;8O=wvkl@?=4<9uvyaMy2isXcF(e zq04KwVbpRzswpQXT&d!Qw1ut5Q+c$7#+#Tu22m4G0r*1GipqT2Lv3H2jn;$Ntn7!z zunK4dmD9xKb{{wdR06(>;YvGMNJ}VQ9lSiWf!qIxEEW|}9vU}?ksXltt$gsflS&qQ zuhXwDLEg&WU(&7Qm}O!+CDaYU#X`>t$87+Z{V*(4W0sv=WsvI7exG{WV&4G3BfsUs z7Rk@mm(mdW=M7J%ATLKvR{ynBr3put(Jex5Hs9}ZR`%vg`o7tFmQxtz`m5&|kZ0Ek z9(NN;n=tjbj4Hl*4i8t*5aQmIM!GmP@9p;}U+>@1N>7dn@8N)a(v8eo rdNH#w-S9!m=5g2S_2`gFvKL&46xQ3RH%9b%il(zE$00960#+HN} literal 0 HcmV?d00001 diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(1).cnf.hdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(1).cnf.hdb new file mode 100644 index 0000000000000000000000000000000000000000..1dec9c7be64d0e34063ae5c1de3094f372318fe3 GIT binary patch literal 765 zcmV4R5H!?6F zF)=SOF)uPOGB6-hN+3*WbY&n#WNCD1Z*Elt000000080v00000005o=0000000000 z008|000000004Laypual!$1&*7YJ{JC@3f>C@82_Uau1;v;>&~Q8+~+Sr!NZ5=8(B z3d)omfum4TavV;8`G4E9wo&Agk;e1w&OT;l#~oG3GR)c>UBcW}O@V43y7SMv%Zp24 zoad**D6y$Szd}=?mu_I~$@J;s`2OMfWfgE{6NET-Smcj=VDSfew>z37IUxs=i-T&j5&00xkY@Ny7M0q=vTrbV@@XurVm-NNl4Tjk6mkcai#Wz! z#qlTf3;F@Qg7QU?HwyyF`;(T!UUhEM?)KZ=Hg`)5M~Ln1C(C9~GP@D|6>1&KJ*Mtxa(gLl+^hL%G7&y59)p4A;M+cC0VC%r|N;M}$t|@qe#zyIae_ zACSA*Ed0kVhqu#5eSLHH3jhHB|9AmhPeDopF%-?T(^`w5Xax}qUF!jqx{A{@6L2O& z5}~uoMkw6~j-4`NN@F7YtTsxd{M))i&LCJVKKGhM5AnXBn$2u1n4&6*bDK$J ztVpM_>;0kd$F*z$WpzCsm(}g!X1?JQjov?8W}j#PPBi}wuA`VGwC6LOhx4I}?wk&4 vA!n2S;!Qs`D5|j8a=R9b2@;7ZHtl=E`_soIO5U)U{A0+hFf92300960Y4A<> literal 0 HcmV?d00001 diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(2).cnf.cdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.(2).cnf.cdb new file mode 100644 index 0000000000000000000000000000000000000000..453a96df384b48441c711e08cda508e454b8214a GIT binary patch literal 1328 zcmV-01<(2v000233jqKC0001M0BZm=00011WpZ4R5H!?6F zF)=SOF)uPOGB6-hN+3*WbY&n#WNCD1Z*Ff900000005T*000000052x0000000000 z001xr00000004La?3hby6hRPxC%V2LD2j@B@Sx(s!%hq;2tp(|te9lcT~HTUHX1Y# zHcB>Ee}V`9iZ_3NhzE}z{R@I8Q8d=qH8tJyNV2=*#bAY+?t0f$SIy3(7Ddrv!J~pF z$3!tpp)R`#`P(1ua=Zz-o^iY=I_Ef1v^!Z3%DUWtu|BAG>W>p1wpkd`Lu?+1pM@bk zOjh=AwX%n)iXLKL$ua8?cdAx0?o_R0+^Jg0xKmomnrn=$`eCnVEWKRst)!ZxbkhN` z>aPxFQwMk%)xpZ({_?Z_(o>hgs16Q^!OEcBU(33{O<~+N1h`-369kyei#M%8Gq<~Q z(+|1}?N+nh>NXedwYsf`%~>84BFeL|_Yj2h9hDEK>iG&~a`nwLhOzIXF^qi+jcgpw z;TXmh3KmY^7?CR!ES$MvBl~uVB5XqVCGA<9o=~G`qtaqOg;x1Ef6JzKou9nZg2~u4 z<}*`sLM1t_M*rmQRrh+;pHKG1e0R3&?FSx0#|5R14foKQnQl#Y8}pk~&>c5bvKNd= z+3TZBI|11(!QW|>i6G4-5ZXCL`g&57&AAg+tqZbzO#JD?)1L}5s6|yxC?$vo0(m?5 z*qK}@G&OhQ|F`qC=1l*Ey3i9}B-htzzWyG_Kg96dtshLj6J%ed2Eg}?pKb_wRroCQ zj~w0+exAofpArPF=o0Od)xC4oqhkrnP4Q(R42fqS9;U;~60<}P<>PD?n_K~l4SjcM zZLRgZ*N^41CxM!*7TQ)sq>-q&#ZtH?6lsKbsf5Svql0l-3ia(%&<@fkqq)MJLbfZ7 z%ZjAO2GfZ>a(OR_aQ`6+>7RX=IL&ukXs+TfJsJqIqJU49`*Kx)|0vlPGhwR2EZ75R zF51RrlGh3~i#GKlUQi4R$2Qgb1p*t4?*hthU_r6b1~ZH z(P+Yh4$QlRcHo$J0q{g;LT`uY14PT~szjqA!!I{GtnV^^e*gdg|NnRa5@29tNMK-K zP)X9uW(3kqKr95r!R~(Xey$-tp1~pUu6`jwkxUF6K;h-93T=QCSQ$5vc6N7+_jmGg zbq-->hye1nbax*C83V#1AbA(3_+WR(5Z8DQPuC#FAZL$A7KRF-#Baxhl|Tw?7e9(Z zKYtfjR)!9sSf}GAFFqg*GK?2Rji)~wg9A`xjnD2HJs_C4Hm0LVHTZO+0Bl@SKg2s``( zfL;pm58`6*0E#5P-!{X4R5H!?6F zF)=SOF)uPOGB6-hN+3*WbY&n#WNCD1Z*Im1000000086x00000003G70000000000 z003kI00000004La>{UHa!$1r@pnNkhFtCG^1<)B77}yX}hl&L%szx0uHKLV5C`!UV zX9mA>F7Z`CVxk~n$+4g9b9}z|(lJ8YEVjPEs~odeF$;6Vy#I^%fNMEq25m4Of5FDA zNWd(cmxVn+JQEw0nF8}VyOP&(oLU4ip%<=c*-O#xNQ->-lqHj3#SX7Zi!y6*nGRAi z`2~VJ#38LQNBzi&fe0&tL<~hdis*^xia3ps0-GGv4-1X(7`E74oH5IIGgrj)|7H{Y z#5pgy+ZYNN#rSfhz=a0q8juFI0i+X9tP)VH5>TuXP;5uIE!-62i{pvD#i&D1i+eZ3 zyH4*{bGyk%3a&MR=9XFPpqJ$N!*rYlfYjdp_C{s%xH3Tg;)32Z1Za`!K3}n?>6k~7 zHb4Xvbac_+BJ{Z-AUrQv^l1WLS5Y5KtO}t%1O|kw{#{4G3!~pZup|G2^td**Mz-d3 z{}sI+hM-0`QRB_?{O;^+I{5?u0RR7Z0bG$gO9Md=$2Skn+Zf*li+~EErH!PK%elE* z$=!wB4dkkA6ipL|xk4-LEd2z211rHIwVy%k#Ks2*_BP_o=5h%J{>)|O$A4yLiX=wb zgpkKx?;&deAqPqe>NCip*fBP1l z5}-v8x>?+7HI?+6A(2ax;Tlc2*B-fkgy1^PqlkRIT=dvrhLU ztzEiTpFR>PPysY_@oIH?O??psT*x0z^kx+Ac-V;7eksIz}Z+G&hZBT0RR6?uYXwp literal 0 HcmV?d00001 diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.qmsg b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.qmsg new file mode 100644 index 0000000..2dc70b1 --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.qmsg @@ -0,0 +1,7 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1679318860805 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition " "Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1679318860805 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 20 13:27:40 2023 " "Processing started: Mon Mar 20 13:27:40 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1679318860805 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1679318860805 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo " "Command: quartus_asm --read_settings_files=off --write_settings_files=off CmpN_Demo -c CmpN_Demo" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1679318860805 ""} +{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1679318860924 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1679318862373 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1679318862434 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "367 " "Peak virtual memory: 367 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1679318862612 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 20 13:27:42 2023 " "Processing ended: Mon Mar 20 13:27:42 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1679318862612 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1679318862612 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1679318862612 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1679318862612 ""} diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.rdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.asm.rdb new file mode 100644 index 0000000000000000000000000000000000000000..7a699ea56549845803ac42034f397f770048018a GIT binary patch literal 824 zcmV-81IPRn000233jqKC0001M0BZm=00011WpZ4R5H!?6F zF)=SOF)uPOGB6-hN+3*WbY&n#WNCD1Z*Hyx00000003qJ000000027y0000000000 z001}x00000004LaoK#tF6EP4@pxie?2zZ(&cxt`bHdM`9l%oPEiAsbRX?E7%&U|xtlD$@|^^o*7sh4)Ub&pKn7*yXRRyBCdqustm=u^@c zYx;`bZ;%qpGcqd{m^!6+wIu9Xsma~e@o9~eE~mD7Lw$Kh_*5)0X!<^+x5IqsgO4{0joMjiZ6Cifc@ zWNTS0x6XtwZ^=wumQj|uldumHUBHA_kS5SM?4`%Oqm? zWLEhD^pecEF83uaP{OFN!Y+45+@XjuS3<@$e&k7)nbZZshYJ`5UhfqyC!Bpnqt8c! zQK!=#rzeBs#w}c4INv2R4T~87A2-A~chbTImo9elhG4%}b*Zo=Au=PwuCzjC1ue2&9>Sm>YAgfgOlp^8QXiSNN6+3jf%Jp05D&hcj+Gmr-95QM5mR>cOkI&J!IJ5>8L9dob)e;4b)2$+qs7OJvV625Im1vbxueMQeU`TSLf~ZuZ z0^)!~Q7^XCV!?_CecJaz~123UcJ_W|E7bFUVZ_AYgk{8o;rEblu1)Y&)u|U-RjXZrcNF`WeOGi zoH`l&_TvSk7p~dpH`-zQL>{+`x78`Nr8;)BioBnIbAh+37gLe;eEtDKs|t@yim9>&LcxL6^^ zOOYfkbtez}NsHp;(bd>@`Srz*J(Wl!uA$bTG>rYZ9L2>2xCX~OJ-LB8&1W&VLVO8t zz*{xclN98H_Ik~7PJ+2);2JvnvGPZn=Pr4~k{CLLMz^DWkAxH^$z2{MrFu$ak>#|3 zB7D=VQu&!8e0hf1-m_KnbZ+cl^4Iyqoc(Fu`!-B!xODaTi3{$1`d)N&ie*mV)KZIa z>+JUB=NAtww?Fh%)Q}Gj{8Cj_7ts`d{k%*6k?yMlA&27G*=7mRCFdzCSM6NrA@J=ddUL)E_AUkI>*<#&JoS8BX?l8hrKtBwI(|z> z67Z4lDfGaQ4DRzjF#HI<#SgtKlihB;Q+JLMC7%&y(BDxgxo1)Y3;4pg%5=oqWoZoB zpRIGuW+satxoBu_tL6mZTO?%bt&jJq_r@no8*gWmHc`CAfLC7VflnQwFTld_Vq8te zS5;oYv+3q)DPQd{efVC?QFB=}%}ywa=k^;WL7c`T+yu;Wrh&RpyF{?J)tN73S!Yd; zN~MUw+3$z@;CW_9tHAbn(`oS|_X^v7qi<#J!G|tlN6?#i)LGeB3GWMO|s!kVE)RPpj(1*hc~7*p&BGnHBygR zeZ|c701pZodQZf3@{|>8Ym=4VvF*7!%f&G+nj@FeMMb)wweR@G$a2?{!&QhkHn`81 zRy#@gHTKat0aHumoMOHUv!C0i0g0Tkw5o0$#*7Er@UNc-mJge!bq*8HrU>IMan-fK zA?Ph{W(1pS6z?EdwUDG5oc zft;34)RANZyU{b%$q_rqUt=j@t>D{dCySyJ+13q_9YJK5-1Mq6QsUC$=?P-`Y2A|6 z@AQVr5B$rKI%KBYUp8Z=xfQ2n)78-AnV&qZf<6Az2%#Ol!^@cUA#%XipxD}@uJVd zAdW@CdmRSBBOv7F$+Mt3%!<$|Vh8r_@9uGqcO~-mE*GB)=h5r_IGm3yeVO6BcP$L( zFr0U7!v@27H|dXIIR8gmEEvwa2c`q7^M4e7gW(*8b6A}}0b5{o{*OcSFr3414#!Gx zNY=w9i>+ebe)>v;s+}A3uYH)Wk~P{~;=Y2;ZUNJ_>g1Fhy1rT(2>$tHqC45uZwRv1 zr6?$zUU#cmJf>sFZR%xUW|uO$P)wlGe=r@8xgbIMDfFUALh&V9V2C&0#ziytKB;3+ zFib+)B_b6>)$$X-w2-0tuKr_A>{o8qiva5-arvH5x&B%KlQ+i$bw4^O9!HZ+4ClmE^ znl&qf8HS>0S}e7e7R#A{(BD=qRg1OcJ^B*eJA)!ziHW`ZvYUk@-OTqeF-|g0=9v!9 zjDpzW7F8nEWUQV2ZQ2kr7}diw*5l9Eo0yn&GS__mSt3Vded7iyz8Pk_S8$D68?0n>msJU>xyk>j2Q zC|{i6joX^AKcXG^D&N34-y6v(e2s%9ZlGuaRUk)%d+U#aT!HjGPGR=Zl_yJU40D;B zVQmz%(A$5NV%9<*rAbqb95sL^2m#!NZTsw=q6Ny(%~-$Q(*aGPN*OI&ZTEsHk59cDeWQEpF~Hihr`Mi3*@-HLdMPnN zHmi}gPmr7L=-N0>Kv9D)D3~~ppaDotMCZRwx33aOR(Ihtdl%&h0 z1?vHqFa_UG6)Gbcl?Fu5P%}m}&Itla0|STwa>w?&{y|INZOcAG4#a;+-uaquzr)MZ z(=X4TkJB+7MKeg3(MBcA00Jq5Pz{aULTlr`1ICjygCB)8ssBSzboreqx}60)07aJy zD7q|9trrmR@M=Ay*Gzqo)`Zs~qcml@z66ud5co7jm$^OEtc>Y^&h2$$Oml~V6@820 zvkt=3>#ef{IZm$^PWaTT!D$NwxgZ@8D<$AV8m;BA$i9@mmx1uASSA^(KOKTUUvE4K<)72ixD zn(c%#h1Gx2_Tn| zcud8#hD3e;`VO)?r<1B0eoU=T%{q;>o@4=4HI|=P$fxEy4a89_Z=Woi{%BE<@(w-8 zMYCdTl-#Eu^+uwdP~~?4sH**}uqF0MeiNh%EEaW;2(2LP{U6orczsXxD_2v6tre8J zeUrp{UlQ*MwpLIp8VYQ8xm-AGtzfK%>hxW$wGUgXuBT-FIqLe7DiHW(UiBI_Y^`8x z1=Dqxr)$_+!PW}4R*4JcSY?RB<0DfC*l`P zC+H$Tdx*?SF`5CH{ALD3>ty#vm;o*IU4n!brUSdT^i-Ba6jz=Qfiv;SUsPpeqYN7V z88e`%4}hx7ea$e!N9i~1i;Oxzqk5v&M1rPoPzSDO`u-VI4EejQfQ6T1yF(fHLeU;L@Z7e3rZEuc|7 z@xyt8EVg=le17Hg*Y1TA;hY$DB*DUK8t@+Y(58k9G|>2M8fYZCR`EbYh;|+(EWJEC zS$cIg0|b^{alq0m-G*Ze%m8h5UKo2s<5D%=Lf^xd8G1+NoJhg!pSJV@B#eHtl%q_- z(=w>Td6Az<(5Rj`FG9^un67(hx<<(3#48CF9*`CUS!rZH7tN4+kttBX z2%w=x$ynt&VRCvUKVBz`qqYUIOLGBWqhj;lr9CDXn zJN4SNQ~JD{BTioXsn-pa6(iAq8hN}?DCcq4vftbV65($9HNQcSJ{ae7;iBSj4Nb6K(Py0 z5yB|b6-@y|H6W_-+MycjUO9yjZe&3Oy2}yhSAMEr`2sZ*yMVE}D+oQ^xX*b7cp)4Z z!+|kO*Ik~jVQU3jE10gkJYB=q3dZU#kJYfXf~^&d)muWYXw^?n6A4# zUBlK2wpK7*cX_&otrd*bT^_4pYXw^?7^}NHR>RhcaKC~&f?vIf8j?_>?4P^-a4iI` zg}}8CxEAuh4HGI-z);Z5Ljlwg?B);X74X?$b@+FyL%4Ad_p9K3Rafj+J%xV4)~b8g zQ`jom?)_B@Vn${D`_RHK3MVL!N37_-Y(I55*KzQc)PIji_5b$x2>ZV5Ug_m4Hn)Cv zWOef<&+F%3HOBy^yT6d`8pu23czLElR-tQ@CgNMHnD}*ISm0h2XYDvW*nnt~o1&Q7 zkjBVhG)R9?2Bh7$tdQ9|C99$n*`phBLp?;bhLaSsn~Nr*!cZVTrhOPKh$YnuVmY=b z`nJkWpQ0(f$tl3kV_Okv^KDj=%hDKe|9XY1tVr=QO*?^OOWwoB`i>VS>OCG6scJOK z485sBsow?Da)U}p2BPodn)k;0c6ceQF|>IpP3 z>V&(R)kFp(eU4MeeRNH?bxQVeo?rl~K9wTnUeQP8@iYmW8C=uWgrc+%`goyfAuUU) z{GrTqmpp7q43koZ+L68&JJtATjy3v}q|0>$>qR;EUG#|&36-NPUBeJe-tVFrA0GJy z!$P7k`uqH(7-MoPi_mtjTR5N~e_erSIXx`Idi2Wtovq+bL1_voO;PgaqDb9%GmPGD znc!%&Oc)9*6U^>K^2(B=13Ai1)K{q-Ct#VtbmU%For{t?oK?jq+|kWv(Dt^LJ02aPH!F+q%|hz+{d!La7pO`(D>^4&YN{=4SM6NrA^3+wR;#GpiiBshA~BiEpqaFmp8&1STry`Ex7nRZxI9|&$O@;1 zME#)pjvU1a64flt=9^3Uen&wUWg$zgmY{^o;~b;Qqsr*=cm~-}6)GdmH22k3rvsPA zm1CpiANM2ONVI#>L#>j!0*9aZj$@OG51Ai`E;-Q2ILp1l+9vHysm7lIpt^B&1Lp+K zr@e;I76@_)54a$cec*$Q*)F;DSrR$hQ)H>FegaxZ6aOM;!7@ZWG0rMl-T*f?LdPhdsr!F$ury2irmJ18QKrfoP!VGhqv)SKrxr%|Hh z!6O>y1mX8IgZq5xJA{;9v+4Z^$?EfxPL6c@gMP_}h!@1!dtxeY-~*QKS;Ab=YR*Z} zM)eO*WcRDjC1CIf0E6o*;sgnx`J!6UABWy|(Y$-F16kKKwc~<|8QkMRc&g)RuIeO9 zvh5Io(WtTc~)cwc~TyU3s;8k6mWKK&auq7rNZHc)EVM{F5TDl5U*jDHAQ#`K2 zM4{z}sT6ud(=9t;BHMR+s970(GdH}~VQ_&0LXOT~2~xf$qYeQ6CS&dFZwtm+0T=_$ zM;JNRh8&7#XG0!Em-8t8xin^q68~RC zD*w@+(x~uV0od*H_>gG4j`@+^av@iP2gx=6m7xRTh#r;iEdWF?myA!#oP!Q>rfWim zqJq1{fns4~y(h`Y5A*F92R;u!jIJxaNvGpqNw;91JQldr8(2e$S7X2fLc9Q@B?+|2 z<`O#ot+kS#qFie|6<^rgLa--&xX1)y=LQyh-vWUZ`e@wy29fPY&Q-{EIiJsHWp3Y9 zX!608RRYg*V7kaWd>zZdwSCLdQz=Lb=RQ;A<~U4}GIwj4d&O}IGOUjhU{5ZZWV2(c z{XrBVGon{EsO}lq1e5CQu~xg}-qy2a#$f@Utvm_l zQ9FX6>>A<`PStqbq-zIlm5S9ugBaJ!S}>FWNE63ia12Z~$g@?ZqXxXdt`&}au=Kgu z>$t5@<64Tj6F}SWN16rfSiDY?!es~H;vEG9Iha}Y4Ql>scxh-7DZ4UtCdK4n%Um7Rr7Q`mXg(g zxY*-gmLfazskm$aKjn&d4bG9^lVealDI6I@>=5CUCW7ULYhQThm9FzvB3vn&s1n<% z__FNbuEI2}B$5pO`F&0lacHw*XGJhLGvn``iXQBn{u zA35?B{$&jAAf8c?$p%Xz_=am>F5LelVn`X0@Ck!Pd5*m+D}1U_1fXpXyy8L+KUt7a z-+ehR4fs3?&eQYv;u(OYjjo-l`?)iLh>pl_Ad{bvhW_%5CJG}CGCg$-T42|5Z#;|{cxW+H9c_cc|>k<&!%k8(AcAjUypop$0;rUhb2kG(q&UsRl~u9OTY85 z9JkJ{JU_p5%9OOlM<)S5JSRFjebwh*oSL;9%)`QMY*=|$t}obh5$q}U_w*>+v-41F z?M8x4nGm1#?$BwrcWQ`c&e1;D;r%bXzAqxCh(Q7J%?q!;%r8WzFGwgCP(z$&e)Eff zs&z24kXYY}Om8d-K9+73K@uou%5;fLM_;W|gNx?v`h=o254|lUVZTO(dL(UPE{!oQ zOk^LsfZCbf@%L`^viddDR^>%wZnuxpxPu)m5r_F`(FNt*xFVO}l~*h!nP!7-xMWa7 zeh0T5)O{r#XL9SaA(2%Z&uo~Iy7;L4VyVi7)z9tQs(B&vM}fcSsqg9QcS_(Z`rS=d z+RW3eO_(UEQ-xp;E3;(ZYeQ#IJ!Xd(ZVIF1BZ{4piY}(;TNv1Ra!WyQ6;1D@pTsp*4~H)@D)7xklS4 z`Rv+U<7cxI_FcoEEqcH_u&p-DHq@3>n;jc!%cthXU%k$+NdDM&7G1@wHke44R#Z2C zF6P^kr+@v};Qhd`O!MsvT-*%0w*Zjh-7EIS|M;ItA9{WNv0y+0ulk+dJNL!AQFl7O zvQPyN;qMM%w@WA8`Wa~zC#ps?>Jn#!kJ(YLOGNvwWLWj#1l7@wnugRd)Q{YG3PE!1 z)yh-iBHtL%rAGUscR79xD>u#s>BeQMSeM|@6NRR`bOiy6IGg=gk~!Jw0W68a?_kxkI&JQs|reQ6hrse~8ob?H;!1%nr?8@0{w zIKG~>D9m8p1ebyr3|_F8(1XDe@%4eSVaR|bA}kSKhoMxrzR9pege786pZa$D3lYSxy+S&F=^kQ-cVjm?BtH4r6 zE#WUO@d;jpC$h%z^Qgs$`Gy^6gZ}$jr&QkPu+yjYO{8MOPo(S?3cKl4UNAEJVo;Vc z^gbBh-D@AXeMeHod(;V1DWsD?7jXl!bkO&rAM4LJo>qA^o?#2#4z!rY{ZW6~Be+I? z2h7b>@0=iG$I}IG)eqF??4Sy_SdTg!6~IU+m~1*lwN~QZ?^wpzLHRYyDnDO+YL;YE zx_I-y`wSUlzt49_N4*CTV&L6)J%NWF6jl&! zjAJebKojdt_K~^dwZ@ExBW|DlH5%67qf#u29abC})F=wkL^KryR%WwA(tW?iq+x`ztvzV^=?o3wU!)V|o-nBs>R{?XmP8wOa6yOFaD3zi5f znYXYqZ?ZY6x#=2gFm1jZXC*c8&HvK7!l8R}^-ZGK6y&{lI=>mbFiseG4^cLp(QW)v z&_V(9n!FBr%>$OhGcPS=u8!$8-DK>C0q)zI@=bltiaYs_y>c)jJTj6FzZr)`u~g69)ZY@?Ebx{0|J5l^0l9R z3rYy~u={AkpMGD@NvKo$#IzjuK!?Q2)H99(7q`df#Fsgn!lki_Hgcl4Ovob(V#OOa zAQy7dvH(R8_4Wm4)8Gv}tX_m8_(xPDPN8@+mdC9Y*PWpz>3){0Myn!^uWY`{nKfM; z5(AFkDl&KYI5J>PVKctjZ(8C*oJ92keG{E`G*4S@Ig@ubUA}($ZZZ~bCv?#)eDqMa z(P}O8Q5z9MV~R&r>TmnkpIK+lngi;}OX5C4s=?n24=LoDBHuKZJ@f^fjYG5f_${U_ zqPxMDC9OZj8+j3r{w6BV9mV4t2I_zJh~%d8G~*DA=6RM>F#{Zi;Qf51xIsCFUXxHX zK0|)0FV|`34NzgCUf^xI$PnC{DDwC-p$1B`3)6L6uve;)%vaKrGP{g92VExRr;v(=G?ezNQlI`!SIi zFVsKoi)tHuc&X{~LlV^qeIfZ;ip@l!&2ZVnhPLlsqhlTxvmbe*oH|CU7cEWCjbUnY z)h(dhHmS_c%%*?}Ka7Up?usKMeQi3+NmwTIKOpAG-I3wXyhf=ES;JL?F%7L}TuXd3 z*X23}w}w<%9Bm;P`mL(5HSx0;k%?Aspx$87nv%uFOU_@)rFVW)+n+v)pVHhg<+hX> z-_&UZGFQzh`nPRQrYy4*)bzBW)e03l9o1Y);pz;$RMsBFA-n+RgwdG=GBj31mM9Y0 z+fyk=uK57cE17FfTMsI%^=#G9J~s)Xk?0n|gJ3>*!5f3SUN=5KZ4+yM(a+be{<2_` z(EGRnHT?&Pv*N@bNSm~=r`d(b28F}{ADxf`4l|xDuV^lm(fwa6W+`-_VN!3yKC>4! zeygJn)%Bt8)vj-+IxdSLnXBR?$F%j}Id2PLNy>!Mg310y)f~7+!u!gfJbhD67%I2`Xp?js7H6&nk=xEvn^M;7 z5Oc*OXEIVif4iYrh%L$9e#vITIi~H%TpzQyHycFTEb{faA<&2hJbW`Fak{wjMoY|InIo8^C?-L6zuhvEl$bx)h-19_2UJzB&X73=Jz`F1cs#y>_8G5gj&)r+U!;MdBvb`=Rk%a zln*vh&Qkb{2VDONf%j#Pu8ngJ*EQtMn@GV%(=YKhv{J{i5Sd`kNeeE!^t_eEr}MqUboln%$eH783c*HGY^_r2nm_FU zv1jONR-$r2Omh+)O|(q_ULYy&o@gR4C4jsUt$tGW^AxgLG}~t>6W^Vr=dTwJ_>~`6 z&YUKHd~l{8nD3lQqm1l|@ea!)_J;@R3loZEWGwl=c*+U$STYuOEsrdrS4WcDs#RnJ zF}%`=N?verjO;)xj_Ih*om;6_vx@rkbAvpF?zk@ex1Z6|_iseVAKgDy@(bL*X)M3y zq#e!rxV`=R?Ncw=QG}{J$z(*z$IpABnwB^oX%JF^evbq7sAQ4>!4)hTrWWB*)RPb>(D zDQi*_p!LdXP(Ft#D~1-_(RERI zp0h)iV14cB)D{+AAybl^d1CsF+G(D03CS6iZF131HrECWv66_CJZ?)f@BNB&gAG?- z!s6!f){&9>h#J-DP)yC|s^Z9q5)rN9)O>2FTgtvyM@?Ec$?2vpmq4|;sAzFON;5R> zzc|iZ#eB5Ai3xz)#H_D(&#XW54Cb9RUFG$`pF#1kXzeaa1AjYo{QbrPG_&}?UcGwZ zcu?=pSFTt+c?I~PN23o7cAM7wr_p8(Z|Sb-X3o0m5WM|Ls5V10Z3?BAOYw$D)n*6$ zR+#nv+;_<*m#@EVH+%5#UWfj*m~q%U{!l{P;l#a%ymR`T8`#IA?2|ren!TTl^&e}| I+xTVvAO81y6951J literal 0 HcmV?d00001 diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml new file mode 100644 index 0000000..c0faa1f --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.bpm b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.bpm new file mode 100644 index 0000000000000000000000000000000000000000..3c37d0ce6536c6b899ebbdab06c3f079c7e45f61 GIT binary patch literal 836 zcmV-K1H1eb000233jqKC0001M0BZm=00011WpZ4R5H!?6F zF)=SOF)uPOGB6-hN+3*WbY&n#WNCD1Z*JfV00000006H700000006}R0000000000 z002Y-00000004La>{d;0(?AdnP`)|A1#zf^#1%H7aT522+6$M!p`0z(-li*TueEkL zBk@1^5%hwfkj~retn1PwmS_csuCy8L^P4wscD+_MdcEEYn)m**d6WD+a&zh;h29PP z(73e-J~F;6-gbO`&TH0Td|B+uTb6%~FAm_U_TdT1L;JGyACuMtn&DRT{>|>&Y1Dt} zkkOctZ?c&~wPnqAy?T2YdF)_bCfI0vCZr-+kDN`p+FSY#{Ut z*3ee8tltg_?50=Pj5NpQJMSWhN6P263Uq>q_Rbs*My`m5S2DwMycCAa?R{8tuwl3soeBI7J<2 zQMxY@otG+;X;j9hR<+Va)sSBqt?T9q{KFX>^1%8$hG&~J4`Y)?`>Go1Yp}nSq?0a6#93dC&-m}l;qs!Bl}a0~*OerEdDkj+ z+D!iUu(DjI&Ai*ic&D?&H*{@x#92@3w3!!{W23Gq8@^FVd|_M9uxJ4;zEP(3vJ=M9Q0;E-eSQ4tw!_&pZ)eluWGs6U+ ztoQA88$mWO12G>|b%0|~h-ZkWzaI+&3s49KK#l?NGxJJV88~2~KpG^$1H{E8DOOg+ OB}JKe=>Px#0RR7O9D4i! literal 0 HcmV?d00001 diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.cdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.cdb new file mode 100644 index 0000000000000000000000000000000000000000..d8e884358d0b5525295c545a3a3e977d91f06606 GIT binary patch literal 8229 zcmeHs_ct6s_dXJY)mIR`B&)67C2E3*8g=#F$?BaA(MgaXx@ggZ=&MFgv?bQ+OORmo z-qwD-@8@6m{`j7mbMG_f%-s9TJ@?MJ=L{_#9$pOq|4!oJx!n!%J8k6P?c)M{!!9Z; zC?Y7ruI%UHZqF_yD$Fh-B6K%Jh3}yLD|Ss6Uk7#-dl%okz0@#*|C+!s|5xD&5&fV3 zk9@-Ze>f0-#{yPoi1h2)Cy6RjQqln0rXv0#Ik?{Ua}cql(U)>%;RO-=Mi5o!>8(lo zZ?n0$3fR2FNK3wpS9f=#;dYRnE(+S!#gsJOOEvviP+p*37#GXuKg0qh3!Rgd=e%-y z;!FkGOhVaPl5|15a$0+y|2!?%SU$wu(n1sR|1bdrB!(a^eruRbLu}PKgVZ8~>G#%R z6Xd?j66Vsv8@fB@9Wmc5X(8Bq4ZwCzvJZU|`MPy++yf>*>Xs1~Uw^aSw{8YAl)q@- zsFRt5i87#lZ#|zO#!Z(lQrM2o+YjyD%V zAqm}`YHH1x7s{B_Cylbdkc9wY4QQ zMF-IAd;V|9QJ*|H#=Hrf$i(G~bMjJ>of3okn5TB<3FS?eIRjE`hzA!WCQb-_Ru+dN zT$hZ!B7!{MtmChZN*8F!=nfR}Y3FId_2_3Pd{#!+6(15;O8=0~&5}k;oQU}-b`M0b zk;Mkiz=sDYo0ku&z2p{d6v_U`_A^Vjd#^yTpBdcjEnYkiJ-J7JN{)VC60B4JVlfsB zo(MsQZ6J+>f)nLi zPm3o@AEW1cH3P$(Gq^0}zUVpT3Tl{ac7_ho-%bP-j*rLzkRw!dt`X)#9WWTA6N18B zjv$H!ByKxfoY}U8k+2(zCK~gK+rxxj{y))aH~Zn2693p{v$xqonX{Wrp&z-BFyHJe zp@#$9PZF4jBu1uQ8?d#QDx5ut;MqGvW%}hL|Cyl3_cUd#nEbN`^*bw4sSqUXzOJ>a zA`BcdMQRM|V{nBK{At2{cNy(p63=iK6#Zq(Bm8W7*V{!0nz20Y4}TLm1ynvsB=Dr# zje4=_fA~z7f;?M!1Rc1e#?sW``lNNcrqwZTBKpMuH1*pE+i_c3b>Q!#C;Q#2sGj4F z+SqoEbLeWa)cY{7m@} z<75CSPPdS=_8Cpd1RoW9iPk{Ftr03!2u3-&-`^>&I*KOy671%)!NUT{RH%4gtozxs zBRG?n{EJIE*D!-%5uDv8B%3vf@fgdLg1+-vHQutY5#<#`-m}Wot7Hlqc>5E*opeqq z|KwgNl4GE0e?LiF->>zW?6l!B=d2GeyKh7ITe z73A`2XX`d9e8szLJn^$TW{1#B0&}np6ca#A8S!bCYx4@xHk1uDScSz-NcF<#x{aSC z>K(&&>QNTq9LDH;@Igw+qLBo^ zN#$qHCTiAeX2`=!+v>hgeHpYKnQ!UbeEdiDMax>(UYE~H%%8ZEvYYRo#;J1^w>d(e zBDzYi&MnIF{K8uTNWU1k-r%YmhreFu6frfH{~G$`zIK=!6(DmkmTHH%u03x#l_5FV z4h-BAgR1FZfy00TLmYBr3<%pfR-WQdOU@Lc`+dH@lO|P5X|e8zQ%nA)kO7{3lG-Fe zpP@K%&&|?1V^ubH;Cslgf3i*iXeV(Ey}3@s#+&u9ycs-XAu@RWx@AO8#J3F#;2_5$ zCZW^3rZz%J`rqYh%R)X!yf%fS^3hYBu0czXs^Jrevz0>a+`>}0w|Nezo6ywL&|1gjamNNq@-6JsCjDng?$5<2 ze($g7_};d>LU+mzAMPGs30(O-d|ief6>!0_1FlXl{vA(lpTAe^RwKYt1Y(zuDaJ-* zvH4g4l2Wzw#%)&rbiYp&^|n9!n2l%1`IHhH!j6FTV7k{s#%`YKVOL?Buxo}>nEU~* zP!VTmiMxg)aX7=DR-?%+(>k5%=LEjx4pzrEH_6twv5}V^ej&Gp?{zG0a5tpSg!(tJ zuT!IuM<@Si!&Ix#5sKZr5#ijOu)U72KA}1{KJf4qjAE0zPLfu)Fs_;CD(~oO3FFl{ z4$~1*#{{$tN8&88h}rEmOazXV>;#ix{1no)-8_C8Hs+CMyq}YgI6rX>gMMnuh`TAa zo5n>e;s_&de|O%R#UAb-I!(2Uhp5c(#^b~$Ds``?q4%>{nps2#dNQNj8R zf1axS5{}o2gC!@;oo~;c!1xes6aF)F!Pstj#3KcCu*bjC-wM_*LfWvFxZ@8=0t#Kg zO$7l2EFOj11mqo_>ea%UZVPBlVh7I8Lv7rz!k!{(r4Z08)P9APW^M9Q>`g7UkCz_C zB71atIG26-`TA1mHhui!l6xXqunVJNQ>|mgx^}G6+J%020j)v7(4S?8P$#v60rkVZ z$3s6=4+TQHk?`5{pHdqU)byu16X>I5p=2rFTS6=5zGNZk1QxvE>3M~UKN|b;e}Yl= z+$LE!*D($$?@ymI%_2-ei*W=v_#!1Fh6gM%35C z2MkW=MuAt%LQdTn{TLbLA+uV48z@u2s#xbDoJe*#kuoUHOkn9zZ%fH=d{Kq{&ixg+ zOV6C{Os{-Ir>J){_8n`RfbUFM;wfiPyi>avA}9}m3ciBB?K0Y&{kHfO7;oRX2@JL= zPSKFu^Si1L7>V-f{9K)HNK$twsDq{*l?I3@e`(y+{%}-Fb=9eS{CwRtaW=4Qkq%jI z_%^WS?r8ff#ZbGv7Sb{~yBwU=N3u4v&A^r^DgU-qf749|lDHU^vnORW+j#s32EN}} zc)7n2UeP_Afg>wQZ-$@DMwS_R{E9N~We$%sw`tb$t}6afb(hR7A(H7uQYjt6AFXBW zLaR=Jv8;9OE$k5=uHzOxXhKGES7snk51+{Io%j9?()=5z$i=+M#jeo8b~2uKOBpyV z^U-l|vr)qx6J*J={LO{T?(J1ebt)v{7Ua&cl+PO;N#HV0Fo6V}w#*x`p~!Eea|nw_Ry;bzk9(d5vV zaJ6ztd7cxcHt_O}!Hk8nmF33{v&T7~zr=3b^!1WJ>5(NL*=Vjf+M-&Twg??x&>|#d zKTfrfb{_BrdpVgjR(a@DA-Qu8__}yeUnL{EmR|k{lH*))GG`ra)xA*QJMpW0n}kSI zQATqF+=WPqz}8&+y-=et*p&LEs_GJdAHCsYA$r+mUck?kI?Xo$%`(W0tzMah1{U(i zI>0Ms9R(^x*#j2oMRZ0n{gSd!h+o7g)Y35I>$^(IU&*AhA-!P>MfzAoH<2tQojze=-dK>+x5y#gBqFh&qBV>2m8y~SXL zj3ID%VfOERj~vf$JV`VOdzuQoISelJ(_I1RV+O5^G4ppyoLpYh1DdH=^U z$=uRT+%m+#+(0S8iFSA>A93 zBJV~2-oK-MaQjC)`iwzVn*8N{h`n);Wi^3ZX}wys(`#GsN&L{b;CmL@{LA?Idy^3B zpVd>dpL*|URqlF<({*KAG6E(h)RW{gm=k&E!v_Uv#VaId^_uCA^D`m_W?e+-vJDnA zCLtG>_Ab>6dFn~g@`oM6XSS9*xw%sdQ_~1;){sVVx^_lH$-Ebh2$Dm0H|h~VW-dFbt6NZgcAGriX6_Q33|k_068nAkM7E%Odho*hM^t{0QT9xz=o>_hMjF*7|57$5<>(Zp zYoOIK7PQw^y4Oc4BQH6)#`>t+Za7)NY{K#LmeYBWfBTQmdrYc9;Q({+bRowM zDVUB3t8q3K(r*?5TD9Cf|0yC9m%BLbVSx^&2!Rw-GJ9jB6%qk%7B%YL@sWK1(2GBK zHS>zkt&)fb-!yZ_ga@t78aXGsP2D3jA7bjE%_ymmdi%6_NHt z%E2CBxd3&IJp|bC&Nf26);PjF8$VtmSEbg;Na9g#x=hGgABK<-3;~>$@|I#<=z0=T z2l2R4v}Rnvb#MB6#l^Doo>x&3uRZlD^zMmF)Rw+iNe3Y!d7y55%phL*j*|#6{6TjC zLC_$){&eq=^$)PbmvMq68`eC+uc}&PDJlq3cSs}#EIjtSOQ}G$&iXH-1U^=&fguT$ z2&Mpi8zgXkKdRV=anB<(8sI=b05fQiRnxhG75#fiFIx4<-s&562?(n(+SaL4h?h1h z6w2J-Tu>5lu&XtGC?#9KcRV_yOGb#bNlCY6HWlDY5Tw-4lzir1BECP8`$1wI zsE_o5o^i&+`j+yNvHE8-Ym%=@17CB4vr$WtN%VZ%IKgzp;R;!on$$?F`1Ft3aC7;R z|HQ&XoDQ7bBP%Uep4}U{_h|gBEC3{&m?D$$NE$VO7hZexz9*8T+Wtn}H7?DM4zKLa zDc>cTeX5DIjHMI)Ri7yydV1`LgWTlg*U%@Es8@rB#(N_~D!}^)_Ne|QOvi%JArGRnB)s2kZR`I{2(kqSo77mhWbuADPy(&$YpoSrLsTZHcL&LQ? z%DW|WFE>gXQedg(`ObB|+CLiJxlK-0j0l4UKt;DfK2F7T*eQ5dhi@0PYK77T^B@m) ztgoM;DIk~2uhPSixcFPn%F8gn-1n|dR%I^*9u}XVsDZ!=*dwRn`G{@%=_cE>TlK&F z3=+$!u4&eh%_>!Ybq+sMIN@T(3vW|`9{(tfXH(^xP6dNZW)*RzckowN@HQ|UjNhj3cA zNjP`OS54#!ObpRs_r)sTz@#7Y#%V);tZ5Kq<@x3#Q7h!+Ta@LEDI-kux~dE2G7{)x zsP$GM(JIs2n@#XJ8RTkMeNq&iQ29n7k`!OMM52ZfACs>G)x~6 zY4ira?$vsX(xtR=LL=I3HY(G@s-!xg8^r70W3G4ZpT@R5!Y+n+m(ir@B!)t{kf`~!ZDC~sEQ)K<< zQvSW%uiVXNQ=(PPb_#;cSYKsOvm`<|SrQ^{!P9xWe9|BO0xVX_E!m9dz>`t>D_&^e zV7ms&Xftjt?UQJb6F5%0Xvi9UcgJ~wy0~(*ahLe+)>V;T=huFFSMUMNIO=z=fugAz z^_rU|161pJ;A357&>5|576O$W=PiS?X^WHTD+44_xBi*aVjTwoxdu6b$r&lpbiWJ| z!g`Nw0H;Y#lrm38e5p@&3P)$p4rh+v_J>v#1f`m<(Fko{9ODI9cl?x#Tdwmxog&vb z6smvQSahPgaqB>>PK^t&s{^LK5QDDjWZMOGx&%f1Y}NevZV|G49g|MH#;${_h*nm( zc_&fd!4#9u-A5a{UX3%r=h;@EeYf1EBi3h5P=qaQaRStk&v~*)KN07&e@Bha6jc-= zFIZB8{8UVs<@#xUA;JEwemf_*_{*H#(#)pew5U>$fad+c9w|*y7Yx?k=NZeCW&}rt zW7_}^SJ1agv?9gaLBO{!HZcj$l_l%G7=j5&xB`Ag;9N_H@4FP1Dpl43K=;fT^hNL= zYr?fY^!2(>7p7&yrsNP_=;O;Ju8 z>f_?9^3tNXEOkjCg;AhsCP#i0;(3cj?+nI;#dm?*J-;fuv+&JVdWf5^7_fSqAC8nM zDPjT%13f)}#y5`cbUJobn?yiFQ_o%VQ}{;dXD01SwW>)E#gGLV`fVe14Np^7Bj4xr zs%L>qx>aA0o6Qz*s%itxFquARm}Np1%{HCE426wK41_Zp9t0HjF0NxfrrBuz^hT0n zR=L~I7ceKgN%tMODQN}jHKGH(0AN8aHeJzEcdT1E(aO!bEpN$5Xun6p)jw~TLBG(e z#=;3N{dM8sCqL-6=^jtOF_ze9skY8G4diFojf(z2p8A^c0x^)j*4d`~mt&CT3b@?q=e9~W5> z^HV9D^F59^e^uQy+@4O)1@~Ya-#BYDcx``tGEmd*s=>brv~%I;o`E)H(AkYac|_ej zG$shTwWLaKg0gd!_&eoGj?alV)+0-iG1gl`tqb+UOdt}bJwww4t~AwdLf&37lH3Rl zqr0YMG$rBr_{$iBzhGA3MYnnk;YZ`ij?TE2&xAuCO_Nl+e@$;2?SOr!YZ!32yAMbl zE)YL7O~YAVi8iLJ8QHZkEkAYT?1p@)HK3(3H5=@+|2XSRerkPCGS0jtT`vW}?VRW= z@P;q$3;&NlMe_CRkrxnN9*edV&N#nfCMiCZD9#I6A8&3DNYXwtCu{%aUxCcOK^5

0x-8T?3_8c!-o)_m*`$>Tu zB6MY$PanL@Sj7~5H+gZT*d{Lxi{f7C`*B|A{n5oaLt86dWz_aNz-XVJQaUM($19Wc z>tli6%x@iQ#fjOAw?kr*^0KsSi*XJb?%ZS(Sw*grYR#qvLtKm1-4Rhr}#_O_Emx*f0 z{|OOan4e20M36_z9^Tg|t|}u;(Ia6K!zNX}vN*~_S_>oXz849c+6(b$PJC!Q=^K6Y zn$&tnxd+fnqA__hf&}puL_UfS#&3Rv5&nI?TUuvGNO|_7Zph&|s?eh)#jVcE|IkN@ zn4FS1hOKoTstySoJUCJ@}+B}j0$;4}&D?(WdIySuwJ?(PnMpY#3q-tpdj zZ*i+Qq4hP%CRRbQ&bt)?- zCkG(*9ZiM3=-1@e?_`Q9qA^)HXky>vXy_gTDSjyg=j3$1r|}h*jC;+Om;5!UI=B6O zc6vU4KUb_=NOZpxId04*pBXpA|9PG%vykG#(ty}|>jwDT=UTP5+&I=TU{1B!;0I?h zkl*$C5WEt(S`;b4Y=v>mEs#y>=E->X8R>G(nDNFxjoU+1&%aO`Va?2h4fiGJyvtdO zP`BB#Nq;fSJ;=H$Vp#p8$JtKkN&SRtiF!KZ=`*O$drfOLS0nVsp0n>Xazy_iq)vj` zDFbGAAo2k;qMnCtnPuvYAo%!v#*Bomw%%}7b&)@{1rs+KyZP<2;5kqpT2Q&3X4CMlVh)1u2z4?dTs^-c+j-Mv?I%_~B(wgd(EULZHZvKFb=FS&-sOL+ znOtaUbJ;HYlKO@IC1PMNXv1mBwTwwv#_c}jQniQt9;EG#lH;~BmJiZt`yDTx4wW8- z5!0%XSky)3^dqUfQ@ni$%%MUbB zz$CoCFAf@8?8hto0E4%OF0nG!-OL$Roonk=uJk)Y%?lvEj-zZ>mzSppoaeyq)CGXx zHUL>4VLX*4yrL*c;XxEbHq~I7KMGAOU`%EY2=*E4m?7a$q*I~jYo#_3+k`i<<h1H6 zvRPj)uuPY#uB_XZv&cjBAboO1K ziUhunSimtxUjJmEP6D{H3irZ<6}^`@`5ks9OYly$F~}*hne8}%oG4~!0}3Y|&Xu^! zr&ec#-Qb=+LP4;*KWnT}JFn~1(j4XJpB|O#6uW>T{1+GF4_9yN3~x=8vF`aa*zA&mQK>-_%4nbQ?26uMmtHFEr$K`I6p(ohG2Xbw)$klf*fYev^V17G{Ld z6IirKpxksf-y}RV+T=r}VYnAUW+hYgg%R3+tn5Z1bJ*LP!*qOp8Fcsny8R=Dm*o~( z%Tq3-`ARwF4Ei$$2{G6D;SyTE)R}iP*20QEtSY)b^Gh$iR$2kL)POJE+N!JsRxahKqre>W{Uj&T&i-;P*Uv}x73!(=jqJJ^xjkf*%K+a~b~jXi zz)8bYN5|+?ZKJR_&@yF@w>M>k4qr@IoL)mL(VwI^=tj)}c0uIsuUsfT^jjD7Xj*j2dFx8f)9 zyYh`MGmnNG-X)jH;hDiWEY^JU*FCk4S;8Ja=x25`Ww|z~Z(u5vUzidalLlU+1x>FN zFDnOcc{96dH%G(z4Qf3W$5muNvZ&4X6-()EVa7 z{Xv7j*m=CLEFM1{eBq3jS}6#U<_#JnPr_xuH{@fQAlC~C_Tf^(tKI!k4KJWlXGSLH zrtk1iIu%|co;Vjrx6#I}ZYf&!4wRaw;EbE4oD#~(2W|AAR$|7cy6M>v^ z(6*Ls%B-zM%j@HVj)NjQHQXo$3{E_WJ|s<$&ct07NTQ)Ki{kZ0bi%Kj{9W<8A!m|&l6)4Z{u^09eW*Y3+I(dQmfY=m>e>yu_t_$Te2;&y(Jfo4091;dB;H2i zEjYZN>-~JidDf@(1Tts3&=Supq6rmyXB{NdUPx{o-&9pdZ2csTs(m-ZYabVKi!_L7 zANTg`&_oj|cr*5V6ZzRO{?7aU$*UG-JvbDhK6_>J+hO2(`}wCbRwO3xp6zsM+<5wAGfBpNk+z8n4F|cYZp#*4+O7CKhN|zw zhitSpykN89n73})-sC9v!8{K!YO>otMLDjs|T;0T$==NZ=g* zRr@}>vR>J?kKY&ua?A))Frmp73b7iGtm8weT4 zs5qc#axDIBr__h;`N1x)c38jjs70Td3~hrpQ>$0Fj3nDoC$|vn8IG?L+J@aiWWp4p zU1vtwgyo|2RGUj>#R{DKew2bHcDTR8ea-^Ujh3EaRCj#sG%_~X}^grRj>Lx8En)QyL~X(f~OZW{Q)cfV^pv4^a+9( zn+`QqxqN0V6B{j9g%r!l_C2QMXkV;grywM5tXP>dUv4Rh*W~+A-0#Q`v_nEVr613+ z9-p-d9~}MWWu&-;tVO(FqjTE5X|mgYL*N2|0|Yh@SkM?cjRi?l7E?LQYyl;0E4MZ zg8)Mxrl~u z9V}blYpT7)uf64|z2$!+8YY3sa|@S^Zh+S-=Ue|sxT@naY?PTvD+-bK_mbpp`3e2% z6!}SNK+R5#3PO(AHf1`hB0hJKJ1i_|?9s&~`)wB=AF({Ta}~dA$X#BE5cUmDVd$FQ9bKxf`UWQYi;#%I7Eo8KX@ zkeo7z2!yxlGg`MZ;}lx8b+9@kPe}uGO1f655ES9t5H~t5Qb=3*qK}SG`vP!PBi7RM z`)-|02M*DB?l7*5jy|dti4ly@8RvX}Ev@0=kj1Q6wN>J;pyCfq7<)OSzH=$8pOt60 zFQh6-fl?;@HQR+Qw{j1Jf0&JZuBA8n?M6?Lbn&e?Sq81gSQdRZwt;0SOCKecBb_gE zxP}B81v&q&HBvo}+P^WBJQ7+}6`xa0bxs&j^)@)5BqLR0F3(hb&fiM)zah+2AY`Sk z8s2)N%4ksrZvF`(u0KvX4z%XmdooOoz}3VebbPJU9YEx7iE#J-HN`6bm66vp633!^ zCJQ_0IBBBCob^O3r&+w%bVdtvDW{IETFg?_ICP#DzWPZO_@C@(TXbnZ{Q7L5!R@iz^R7Af8?I<(;^z@3_hAhUUOTjcH6H! zI-uHg?^Me2-(J2w3mWc6@6O1Pq@<4l?9#;m^66p<*xdE=CBhGx)o5b6?5oMlkz;(2 zRT(U>OUuevd@hk~Dee(2?Mu8`U4Fo%4C2@|g#qWH=^MuGtW4g>@ckU&7eEsKu9 zZ^|>a(fhd&H;rqPy=R7sOiD(6L@EQ2wo$8oh4=xINkJHp)KY<@mIfrX{Qn`aAcT%5 z|A-r_03-d;+D&cQj``NEPq%;rc!vQWxi1R4<>fE1OH!5?S#pPsJcsxPlKfmAwi*Sn zK3@V){8CRU8c{2r440i&jO~|vi1B0+hU84lg}IBOJNw`J6j4MIW0y`zLp8mW-w_f8 zxan+IX@WrIO1Iw?ZIQBKwlD^C1R;x~@*qs{S!~b%(_a+Jstt`#v3pcJaOJWNhUiqs&McN6&gicV20LN1Km@>K!*0tS z@kqo0u>=AO5eIfmR05^8t6y4FLMCGI>daKxdb@;jn(lR%@#?mU?zgVV>UskFv7}as zfIs+KT0Q~5qs?d(#|Zb`xpfo0|MaV2^q01Nqoudi^4v9Hq+_;Jbk__W9???KyJNck zx1GqeNenXMPYx33mvwsENcDV&5bI!%=|KNu+^3qRo^`vD}LdZ;{R@_ znaADN_HyFl8-&`gQW)qehI0Ntnx%!Sgu=4c)64h;D@FG)NUZTIedLL34GtNGdISWkhcvn14W)YAdh&lO zKJzQm6{H=cusxSupGap?>yX6ko)8j9oRb9k$gy841f_siN#;7mNiCjqE**TaMPX54 z!Rays!ZG@^8<=U~zwX`MUjo7;N6Z+20408bKouA+_+mW$>l$c4Nf)b8l!aXyah?V8eJmm; zcMH+z+(wuMge!P;6{XMr#n$u@eG9KwImq&>0x1X}`lk_&6ca+I1eJcKa}$VZ1v82} zS42D+SA+?STYZ&Vsp-w%78ob8j+`-D-@Zv6-G2eBnX#24C?Rc;OK^OOB$*@O^;eO# z>%Hgpa@G8=&BYZ3YCM0^PFOVliS6gFXmF8Ge;elokasNCwxJeCazr@s15_Xylu1EU zMPwdneisC0jGqQ>Da`GOC`Mv_rv<;1|0c-66AiNZBg*k93UU-d|JnWpa>FG zbb?lB_+m~0WcS5_0n!rL$nPqpMB;WxTaxv{T^yf^zW#HJ)&86R9$U!+(SXnZ4^+3g zM?#}h>p(K-)c$0TTaRO9%s$BCE6JPMqL~96{r_u3E{+6OmClhrxdu>44ZjVb>Kqdd zI7EZ#D6nhw(h4V2z3&%;%Kj$;6_cBuYVmdQo zgUfw^kCS$kr~C#PH~oerdyvmYsZNBr8y3pY6dnereMO|%#!upj&MCo+{uO=)$lbF4 zWE+>=m{@)$=;!IIjOZizM~wvyA2|8cFCl=3&mmpF?U-tcJ72tYYoI(;5bXK)Yp^ci z>$LtEQ!@LLSa-B!uD%=r#QZbxkC`)y&%dPg_t+{YuQ8&<9Fbq)?}%k_Yyp!Ru3T}R zS~!zh0Q@lPdFq~I8yF!J7M_6@L1p=%0Z;t+M+XBBuk{UIQtr%AsmxMo#kY7heRDeN z#(9g*VC<~RPx?m7U_Y1lo=zP77IUYspX~+EzJ2)wJ)$-Qc5azdtN$E97Z#J`06w;xw~ zC)b5t_OX#>b}4YoOe>sN=JeG73+S22D9S$~n24#Jp`GYlA zAo){wvIk{A&5(FPhzAJqfd)ckL5P44GO~zWk%L3QaVPNMU=@F06Sn(_E+zNn^6sLm ze}Ik!`IA&d%|QF~i|V^EXeb+dVvJ;xXN+VRf?f#PA!vl48iFz&S@fCK^MUUinrmt@;u!4mNSH~N}HQ~gKMaPyf+Nf^9YTgv=m}& z$EcCQWgy%wXjLQtk1gYv-v`%*`g>wK*dirhiK_>ti;8dtfYwA1^sBaLvp9ua6Ee@J zgv>K^Fo&|LAk!#iRSMwW5(&65m1smfT9;)Fc`93BEYz8^(4<{B)EY)oqh)Kdf;Hni zI)XVHhsY)}O;MSap&lR|b!d?Jf`H)Q08D%=px2t6F;wI8Kzt)!j9r}<4sC=OF>K&M52Hi%fzbt?yOEqHk#8<9oXq>Q z64*co%|3ypEL8vXQBW05DTLYGps&sOqZ_><&x2TA?~v2|(d{w(nI5ZYTq8I(&qr~X z%O8mw^J{+TdKn|}-}``-8}rv`E!&4!Gw1PZYFid*@UNIwIenEqtR4pofivd9>?iX1 zP_2do{s`NCGz75T$r|k3Mfcb-(W2cu41O<>PH4gqAMMZ}-nXN0TxUtdx72-O%m_5o z-OjGTI72OD0xk5buX;Zse@fgl15)S1@{16qkm35M_UmMaQqf|rs}f_ls3|%Sv;ADQ zMTWA=sQTHdDE2vIj;`^WG~?&;hMSEb>P-(vr6oB4a2 z>Rd}LHp5wg>u#Vj(3ko8RkPlC|B3JKz{d2rMtg^P>Z$TpadCBjsRG&Y2LcPrZvo%Q zg$%EoF(`YhL``7|4UcOdFDyFI8=OyyQf`XWn2LXXHitXhG)rl15M6%PZNJC423+gn-dCD=!I zBY6Ex7_RYlr&~Ir&Mo*rW}OVU%(+rE#K^Mm9sgBNxm*wN*gUZBIl_*tSi1O1m4;w! z&jbw{pg!TtqUDI-*^5Iv4>e?hd{M<|*M;_}T_d+&kH0qy7DXF=el2pnS{M`a$>Ty- z!KVI}){YX6xq=w+QQckH#ppXpW^j`1=tOED~4 zkoJXZX>*n81{SNXe`rUUClhus2mbDEFxWs_*d>Bx1g~!dS19<@7>;>a_UnbQm6shw zQ|Wky$-(^3%<)sk|4FV zX#WZI@k?s#Jel>X)*@Pi5b^;3_MJV!?e+=!q5m^%gyl}?c_U+csC5;Vxz&OQR|xaf z*JFbeZi1Oj!3@1Tq%AVWEl=~mcY$7?m{$H#QkPl&l#K^J=VB-D1byNmH?1-JT*ba3 z950Ra#2R&ph2J7Cwx|GO@q%6}d4le^*!T({Fy2){aM^~YU^)o3TsvcloKa9qbA&xb zTkmtDZ4a&M1X@PLjOfrzl;0r9OR1Icn{}Grpo5?3Udpv&alsZ;i+>vSw*B$qtECUp zV4g2zzYD>gN?ttjdY%Pr4^el~HX}pX_?^4uelFWNEJfME*0RGtx9nm^3fioq`Lc$R zlL@>X*l?t`%KZv1fTvHUq7gM8<{wM%^b*i`kb2nQJi2G@!uWNyy$O@m>Niq@8vB4{ zsQhWCq05br)#P`xJW2-%hf?f%;dYfs@~7s8#P?9yL;8lS>xLihbP^p{O^)a$KMrNT zOjSkioVRqa>u7kbH!nx4<}Q9gEn0KCFIk%W!ctVp^3e4u9mx_h1;FlX&sF#gXpLE~ zDg@FJD$JTXHvTZA)9mgbeKGPX4PV9a8Iy{3W-w zg*AdPuC?AQj6xZ|st`NbNQWs3t#Q`*j@ssiZRz)(WLJxATb&7y&&@jE5_l(oH}AGC zXz_7`f;+s@PuWohMw#nehNsnJlJ93A&ikiu4#@4qw);0eMSn$-nX~TgcMjx|)BnGs z?SEBr-GqGiQMR!7E9{8m3@&cw9*Xd_5Ek2Z;FIY$w&?K2pWi9^oRK{7)Wgbb@X|YSifwA` zjpv3Rk;afpQ;+ve_RUi9)FO>*l9(DdUiaBjp9juYD(%~7klJloO4!N6Wy9(5kMXeB zL1n26i>(HLnS&$DrD&@e|GlSXSfubShKrU8_PFo@c5)>8J&ti=bN{p>wFzy34nsW` z<2;bNld7`r_R(InM4?|F7`?eYHC&rb=LRgijkxygljdV;#Oe@A6jLog%+VC$8d(o$H(`;({vq zges8+&y~R`@O}+JYAZQ{hR!gF%exn88BDmcrKu6tk_f`@2%P>+-`fj+ElTZ~S!tkU zZ}wGiIl|o5Ru}RZ3b&jOuV}=^$18lrX@CDD1;l8|s&{+S^6yr%!b1x{GBz?0XKuVF zI~X_*2Lp>H3KZB@k6oR>E#k!IGXv^d29lS+b=Fe~223>qZ@;-Y$*~h_=2DWwyzrz9 z#)rAwZoJUQ%uFbB)n0h*>_r#NZ9?NT;&b-F%4QV-g z?NrrJ9v(FrG9zFbDs@G-$evHEsJzXHnAJWTa$eZ+@Oa{FafC^~oC`kt`iF-|F{#kEoK|a=jO9S| z<7@HZ0m9D%j>AJmXlMM%O?mV&vJ4hV{S0WRdC{HZUowNhOJmW^%ftDd6UA)Y;Rq_x zrgK;=*je#&G0YB3mx7{}#w!%`ww47C69i)nEtY%kr%(gx2>7NhKk(OR->)5F`8v>i ziXLPMm}l!>Xe-yqD`&D_=!5n2kDtf*68zL#>~{y0TasERy*MUWpQiW6`m^e6D2Z#b z8fZE^aSyn|_L^HPpB!KaUoF(B&`*Z9R_`&t`gI7egd5og|N2cm6K_CYn@01b&Ui5T zsvlaL?g1^0mH61vJ^E#r^S&%QqtC@+b0HU)X?H zUtK4*mRyhAHL4Z$t?y5fXx07>pizjP0rt75b^uTEC|5WVT3_hZX~Q%w`U1^(<5UNd zQ(XPIQpd4r=Q|YP#OOxSB+PXTzZ0r-e8sDF6sL12)xAR(l_6Wp}0b>QTnPgUcT-Ldluq z=P~Zdip*9A#zRs1DmH-39AGK>QBXpSLY7T&8|U^cl#HE7D%+2eM-Hzs-O#z|^FvbL z(4lr*)~*TG4HjVBSkDGv)^A&%RXX}j+b=>{;K6zNY~1@`a!GLAREef_eC+Q+%hdYD zkM+GDKDqd>vNktD_PMsMxgAU4Z&+MU+G_`Vs|U8y@a1fhelkgV@eH7 za{9@;?S(mTAp5&{;tH$J8jh~McIBr$%u`ZGQZl^EgEWI9fonT$qUw!EHFvvh(8#U3 zmgz4X$mQ`CtmN1vOuQuifO+4SaS}q#^nvU}^YH<;Kxc1TZ9^-8qoRo)T84rH-G_a&&7;@sT+7W*L$;F$I<23mCYIEZQ z%ll$-R8uEAVK8^NBI5w2Rrm9Ofqu?<<*mGA4MHP2cER>Ctznj=e1MbSR_SzAUhzS5 z0DOONfMmef1;04PtI+h!?%-JUJ9Ad~@rxozCMo+F#A$R2ePvnSq7Y|0(4uSt08 z=4tp0i2Gk2MQl2s=hxSl^tzkxCO^uBvm_DR`i?aTo zx4Nf!3hkw5e}>MI5Q<~*q%?V9oG+HR@^vfFBQ5`EnCNlr zJ^dkm3aJ*%d|#FYEwd@u@$TNc*5ucJv8R1|h@CK+y~@U#;gg~o?fp=>^8-a@bYDPgzrBG0$lGM6BRQz)5!-|@94e}{>4+!T{+ zdhQzlZvb|J@Uc%!d^0BuWDFbf08WrnovYFRroCKy>6`8H( zRc&3>j~2-Odo#K-LAPYtUPwW?~X9jnx$`eZDpu;Q{BzkDQd zm<+I9ux}8DyRY$|uI~XINHpi)5P!_qg*&*1-$$w$Jb^&d!r4cPJ3E0w(^B6{dKfN*2w{2whe)2&$UvCf(ZuaxlV_mVlq`zmu9`wZpq_LHNIV2=TR{646Up}MFS0bqaZ_$b1!&Kw9L3)&8DH!9{<;93>5+pnxSY$~(*W}OxG z3J&;fX5Kls@4lPhlDWHPmtEODekD_XAuUL6TXz8E92Wn1#N&&*RTj^7DYZzG>SG>y zfPxH->s_D||7uMz|mU3!yH+jgK zI404{?u<(xQ!s`D`6Vm2EyWBX>cG^fn%J5BhjFgNU{mn>?5yC#f4NptoA{@e5awHE z{7ip~u(r&XBl>T&G{(ELmyt=kw|3V-*EFg{i3uH(X6|BCu&}$>X}uwmfY-|FysRu6 z0z5dA6LmWrfXRX+0MG`05F?@Yuk>#G5bLitS62aLJq7f0fu({iAHIl=YP`-99y?e2 z+p9|rTTUmZ=GTZ*Bha9dcRp6ivvV|vnD(rv>OTe1`V97`>k1|RW_RYHdb5gzTUqIv ziLs-KQcqQM%1b*)-?HFeZ=r;lj8SB>N0hlh&p|tAvP*i`7LD5oXIeVE(f-ePzg4i| zgpPJ{uxP6imH`n}4AcyiqLi2K18WJXVR@WeU(qJ9zGI}3?RIfyNc35r z_VESsdDLMmI|mZ!4)5Ix8ZNM$C|rjjL5z!I1uUTrbQh!+PRiCPYAcU!RRS+e)!nvP z>XYB?btI9@L^p@a8P*dklB{J2xvjaC0xXARVblagD09nPwE z^mUybf$~vRSiKAJ4~uI>TSvoaXe%P=Ly&rz1K6)Q|7k3JnBFD45?!zqPUZ5@z3x)> zP~4x)TPs8NwC=PyMtD?e&DyfFRM0VVU;Q-HdkmP-)`Nd{kBpz=c!6PEK>0I}SfY4! zn>8i?ijAnzmK=%wWcx{?#f4T{710JkV&#rzdWB~euA5l->#(W5m&^km=f1gg4sN~%uzf>PDy<7i#>GHK0(jDDE zznd;-vQGuhj(Z<1JX!5rQ6YbE%&fM)RvQ!jd#&%w!V#-?Y)W=qQRG=At$AXngua48 zM9dIxe~B#o_0OHUUPx}@qpH5SjUMb3A0YU}z~|TxgQ+CN0~`IUrmdan&(h<<8pSF& zaVyJ{i6Y{NJD;UR=G8_bR3MGo$}4~(er2|A`u-s<-J{XJS?wkfB8CVgoBn-$TiNA& zbJl$L{^_5-9A1xS!OUt$l!bzEgSK^u(w-{xQV*};dV#dC<{Vy=XXwo8>zjPp$48)` z$=VL(nTEvjDAVveCJnjZ6dZ>tK?#S<3z0oa2pcL=8R4Xs^8ulh#T|54Re-30lyytU4d)%5Wka47t z7$Uf*3=-Z>XkhhRg$${2C4MZ>bGW&`P0Rx%PK509A;4sm=hBU)-uVwVi)P7Q zNaj{EulTPXf8Axl(LZZ^JSLZgO_h$s17}hE-G9#gM$N8k=8>~&YDsGU4!YqzeY8o)f`33NgP`^_NxdQn1VPru{l{v|Y%bL=LN zWg4Sm>>{(h?gBTyN=-1j&H~3coGSkd!a`m6H=b8RE*nqH&t~N?;h#q&_tYCJE%O*v zIb36oo5fRV?@J-x(+MRRSC;=8#=Euq`jC)$j6=gS1%(i$dBH^161QL93!L!FU}O)F z>DDS7byv7!p;t=^&eu1(>;0(yEY(OtPKR}#q@jz?b%&$jib8C+b&2{j6}C%wUH;MP zUIQdhnIv!t>CP<9F4wtI((vwAX9MI6*4CA>ydh(|MARcwzUVTY5Lk<;x|=msdeqWx zzC(gfQPEcvQJud>BJc&`d#LRT#oNVtG*+3JkJ}sW+xXX|X5)g=pyr(R-l4O|v+5xA@B!k&bw{y+ z(pc%(SOqWRJqU>rE-?N?4iRE=V%Qt{kK>mkg6?xsi;{wjc7 zLUp*@pH(un{^3zuOg5(VR#vI|#m1S*)grFlI{(XSO!a$1?v1sj+QB{T>wxHCi<+$_ zVX+XW)Vd23$q935hJjXG`)Qo;0ZP%+YdVeB8e|o|Ct|C|QKk(L!hw7k+rwKuAU4?Y z1Eu9nKtKe{;kL*K-GNVfj>i|OdLkqUVVs)hzCH(ha@XDI)y2h*Udk=YL?yNLz||g1 zjDJBV-?3&kMRm|ZaJZ#*7l~Hd!yU(7uv)}Hm)6HI~h&~ zJJ*~6_w=R+yQS=?T>?5bSH7wt-_gwtToZn}`Q*N^VR-)=jP+ld$^WA{z)UWnmC3azP0YC>i0W{KJV-@h{P$G|lVK=vxbV+lkiJ{YmPAf3+#)qA<`8Y{xk|msoYjQ6L@l>MS=T?mQ&Q6%xgODI%(YP<7J$Vb!Zt z>^Kw)4Y4S`sWdL(JQoL1YGpn>Zrnc`%!UzHUoJ%2rcu8~2{2#a)nOoXFjH7|af?=y z4rD-*T0v$MX%_!6Se;dST1l3_>v;`=SW#qoE%;&qFQ^hf)dTFUpRXK>>5#lhm7T4D z0@YUu-&9u;c@VTcjBAk`=O~A~JWoxYKJQ>{cF4dH?_#RQF5te7FNmjkV62JR@6dsVb{JPXPQ0I0br$M@ zUvK9@MBJx`V`NDLuy3QFo2NQD=r}@pacS4)j*I zcyGCtEiF4g?+@a-z}}<=r^_q47I~DMUw%H;BDiCgyoYwC-SqJ4Zl)?kH+7u=@1xJx z@uahO#7-s2FE&jT4{PtEyVy7n58OWo=%y03c-&D68tS%K&eukA-oEs4f0}88wlCv} zFFy^8Kl=?TMc_hA#{Zr^mZ&y-xdg?gQxUt8o71<)&lkB{VtMuQI-S%vuBv%sg%Y*BsN6=1(Rr}LYL zZ<-SOyS=Zwkkwu3jO2da4Ka`%S?ZTF__1)KWk>PM)YPFQcdBtk`489fuICmeNw{lN z?odYUtp;7)F2O-OskOR#gS2`FU0(U|j?>&Cl~*+-#5|~7o<36#thMIjJGAAw_m-8= zUf3jz+RfEg~w zHukh`HU83g{zxBRZ6T}znPf9b>S!te&n$e=vIhl3nb|ivR4*me0c+g%p!!!kbk*s4 zdbPoyNpRGEPi74VOXXdo3)tB6PNuKi^ z_P_`V*tYTM_%B2LN*uk*W4^VSgi^EWtLP-(3#3L+5@#wj{~`x@7**2cFQMSKA>^UL z>oeQ?ymLI$7OZveWvuqXRJxpsF6*eMKY)>@i{^z$ks=M3%|p>0d7N=?1xUitZ{8e0 z)N9!at2_E34MVt3`u^O4jitTih3`sjB!RI4hR!P&2}kAC=RUR?YnO{kN5^G z_OVXxsaDxOC|h7rWbqlPm(fUq6TvUTU<{~u<(J7wmpG1sa4?!o&dWa$+-O?4`WG3#=sFzY@d|FO>bRdSV<7jt!*I`gA7 zk^i{r5>vhqW|RwP2$|N4o8(k4y88ajNqD)9DE}tfw-$uAE!RD0p+Y?^h#uuagt2VA z{+pfTl%E2_So|sy+I$5Xz?(<%+~M;@;xiR_znybO69$)4dhB=#yr>|T+PC8#={H{90E3Tm@@WoSVXc;c4jO|Vj=%ZX+4^3sF9bc!f zUfm288mdj3sxA-q`aX2j|FhhxG)AD@*!kzB$gg~GmF6g8#);Ey2arzB3-5yIi}C(a zx(KGa_-xUg?4%guUag#F`W-Jm#L+yxI>q8$Tv&6V%z0Rhr{={cE3B9_ zgYRh#FZk(p`(0%(A@sEmdL@|!?{9-cG5M|I@G7aaW1qx22xR?=U1Vg&nnaI+xDQY8 zr)BoG@qMq`M19lcwgvRQjb887D)Z2wo53tJ;S6u({3mn?h0X^h;Iei`!2>y?d^jF! zr9WWOv}60#i*0#ko(Q$K4v92PS!m?BL(p&qS@Tm(C=s@2cl~SCS5s_D?+x_&(}+KI za=HbN+476^Tv*-im_tHWpI2P^MH;gh+7BT8q4Aacs}Dk%mDcJE0gl6%LU4v@ZiWOs z((!~IKix^*&`m4e?8$Vm4TMa*hp4Sq_(iGn#!KI43y+t1dEZb~L>-8T3tXKZBa5D!+>OVQ@rv7NblkkDHTM^)F0(CgcaDn!W4S1fFmv218=Re*Thxq~&nb&0hMM0Guqp?yoWTQy`T z_MbMHOfGF9;k5%lZ6Plm*<2njb0Qns1zz>$dUk`#$twa1eOV%~a4=q_rQH{rRP{Jo z*FTywe323#Ycx!35N11HbydN47i9mt?)%y_JssS;`7R-Df$@s6b`ZLHa1S*9wZTn8I z)A6pg7##Th6{bmvRGsM|`AAy=ShrtZk0&K~%{zH?P~&|XpKT-j03!N+B6(uWU#(+YEjf2ICt)@4XnmY1i@b*;lA4=+HPDb^a#wz)5Ovm3d=UiSEJUCRd`t zwA*ZX)s|mBe%Iw-lQoltVylSz#zV6e-q`fw`^UVj^f@#H(;+cdvgB8?tIBAetD4NA zZam%USxEBDSqN=gp^=o&VL|T)PZXMDWDkb2brh$Enl#c=XCoh|MeZG!1YY=ysX_1? zf2hqmRSFK|BQlZ`_FE|QcY1{1p<6zS{-DL=j{2;cqZO1JYCnQe=1o9BdzW8|NR#6y zvp=W1;4Y;nNkaOm^~U5I)U2LN6VX>j1$xdmqN2RTbycO4b9&l4MKe~lXL!JgD>Ye3 zO#n29!dWX}1S(v}A@K8o(W8dRuHc!D%DfvgPiS3`ktthdkrhDb&?=RU@tXE)X=fL? zvDfY8W~H}fpsn?>=}gG|-E+@5_woC8W*?88$8%rhGc)g* z%`bE@kgIPf_ChzG9CWI$%Fc^gF~O+*F!o&$EO-;?`t1?T7i)`CvWABF1unfl%yEVZ z!9gcycu#F?$;IK`%=*3A^^^rWI&rStF%MIn=I$56AGa*&n)+3%XI~7*g%YnlN1&$8 zIfw_fAr^crD1D@dpVcUmqGmLhiKYl9R*s$tB96?jq<|t`hIGr;0@Zs=vjh=IJ z#~j_uh1alpsFNHFF4#Mz|jl|uX$1Ns7t8@Yry()O#cfLQ(5mRyD5 zRbnHv&xa8WPx|au@gVv+X}3c;x;1gcYPE%WGy2%fclGfaaKU2iy867Ww@~^tpXcb8 zv(m9a{&LEnT#=Tnhxt9j6b=;ZCx}0aVh8O_*B4TG&gNgkFPdyu=SiBZ3q4KWRx`|T zdrh-TB346`j)}M4mpObVcq*uxfEM`?4|Lz_=RZl6j&+H|X0VRWvXg8^xom$JvLE=BKw- zXGhGoIt6{(>1*AzoU3Lsr*HS)$Nku4=dt|6eIHU6LY};9l5=2oyHerG!*1^K)q&O| zzUFKz?m8utBdeP;54z?>%7 zV%s~jz+}?SL4J~~jT>Bq2(gv&yHFeU#Ujfxs_-J)7eztT%868FR5MvG+c`2FRA;CX z8T~|OsZh@^J%d`WoXIa(Ar}V1QStYot~Fu}m$ptGG`B#>>5B#hci1hJF%7-+X3SrbJ@M%FA^rCm({5*!5eWFc72!c@;&)1?`^dCUyNz+1$2Q3_2ti(o}5d zLEpF<^5V;ZXi^7+X6}7*ez-`(ufmv0Nmj1r9Shu1(=#5_wu4+7FoaUvZ25Use?{`4 z2%|}+V1I>ggat1T)km?gs>$-DOl6Q?4I}pKwt;==?YKV%2{s~k;_QNq(lrz8b|=l3 z-XChwD2zSgPrFOQ5M)(E952e|+00&P*2)B)vc_5qwck{9vKN+89ob&sv{^ZFB?!gJ zCGiM=I%@wYbCn49YA!GJ?aHRdqz8Dq-Yw=~Y|Ne6QWjn6yOxL3*AV>mr^Hh`Zood_ ze_n5(Jw)~Sr=8z2B?vD9bisTy1?Z=v0iKs1SDAO{XtqXA)Qy#39S$??w z;caq__<006=7iqlq%wt+k<|QwpSVw&pGyi)Fl2NW-tmKK+d-)f@c%}ga^N94wL`1F zaR)g`!spQt_&10uE)Z2AlR+Y?JihUQzV>#t8BR;f? zf1>v`u%V=WA-CC8VcsSAe9QM&b=$;`0ypU|td})z_Xo2M_IkJ9T&YfO1>v&MowEfR z+>tcbU3xMyHbv0wIEaTP%KSH){5yX64a?3m#W>q5KklfH+?jXbt)+%_tYw*beOMPl zU-O_)-chWXH$14hO^wIljTe6o zg}D6c+3DA&%5P;kyX<(_64s&)#DTyQ7L^xh12dcx8j(Hu@zY~_ zaFVS#*54&I?^kT@%Rg69*Aazt`uu6&BQrI{mCL%Jqw(iSJi)A^-fpcS*duaDB~{tB zZ0lA0URvI_pYHpAPTm{&ma6SPI~bqb{9y2HpE7^>`DWX%uA-u0gr(qo@h6mp;fz5?j7nR|ShM|nL&cdWpx&?DhAB-b>Zz875yL?&?&!{v|X%YICu!0hG;DD!&bX&sMT}TBtIz zDY%G=%gf!6&lD&U0}EVU## ze$TuVe?78GDp^@fIF&i;^MvrD~?Lnb1mxacBx~;lC?37w5e9wEWLuld8sA^X~GG*`h!MdUvycb zgoHz`3kjq3sB7Lk&7|u(rd~qOk#>)$ zl3&8qf)xO12?7gknat`7vWa_|_zqCd4W}taOvEJ2(Q%K#EOrOl>U26~IF1V~Rq?>~ zC;d@)grw^9g-*nrT^Bo8%f0Y>EhO+v4J(I6Z`348_29L{~aBf!XtvMbnlnnlfW|^U9`K(2Lbx<(Uhnd#B zhW5P%4_g7weP2hvV4mE!tV7iQCD`(nA?d{9FB!}8E1|fmcqr1iY{(Sy`EaUbM$@E>B+CC8j*U}vD zC!fOhx%hKRrDJIR@}ls}MyllZ_nQUBMJ}d3BuP$6W^iGngPz?$D*IwhAqi4lKkHywI zg-2Q=aP(7G41;bvwU5P|$%qa3u?F5>x}-9^wvBLVr^4-IR6d<{Fq_yP!gO~&OCC79 zGZB9?`6y32txJX_&DLcR(E2tQ!n46%f3z*5v(Ttdi<-Oy9Yd9#bGNG}%L%XAibWS=PPip;1|ht=-~gYbJ*io)1=jUF_u9p@+1gb*lo_N7ppO0m>+MQ6kV`(28W?l&PwGID zhgqCB4Bjdz7U_O{9x-2BAp9Dw2}ypjAty1^@dy*9DnV97(KhgP(x7eqA5mM4}iu%W0B!C>gX+?Qm#vh23JSXvrKmtYX z)VUFz%D@?87(?QLbGk1Fr3$LtM0l_kov)L%1JB<)?zl4xp;GNdeX1InVF<$ZyAo`q zd03Do?9#WE8eh?Np2HMA+#$%hkI(qKK@Y9i|FFZ5r@x-ZE=in5I z+{Oy<`Z4ZiuS4AWQ-|D_YC@jdn{&LeqDsgPgl+PzovV*1-i6#-* zNdYL1lu3>|*o}-nXK0xaZYx)6&=A-v5+P^io_ko`xpMpxTk|BCB|VBH|#oiuR&vzv^=g*!4Kb@xeBJKAnGs^7oeTGG_z0eKaniXu(j; z&Ru7d(4Y6rNlCf#ch_)_x=-@T{^gPuLleT?u7uDDk<^EN1q5*L_0QPlVIqJ14F0Mi>Fbi_!kT#WNwrTrEZ78~R#q z>q);d826m{D9T(BxblaB=M3-CW5ci(av<@d}XQZGT3w_Z+TT^Q0Jt)Ai7%yAxbqiZtPsl=C3)RPmKuLc6A zZdcs5r%Y7qbXmQ7#K`Ke#u?H{Am{8GpW8mAPb#wos)o#70X70M1rQwT< z*#r9@#6jZs4BxybKAIYSFXG;{quWT4TSrR@&awi& z#w1Pa^VV1fekqg}`4g6Y2lVl$i4UaIBG%6qt+TDB+8x5}_7F4T5>N7<#ABGtb^E`H z>b@-j(lK;fUHx^6Wh@1gc3KWWUMf$9wmN7Gp2j_2BeiVkV)jEg@QI>Gl1$Kpk`7tgeMaO7*<*IsRjCPTNICM9YfR zVE`2!R=J3!T6%=v&VtdO-ukvd8E3G}Tejn=HAMO3ZWyfb{&9`O-dUz=fYa_i!aqZd zMR89r{@8kcthQ+1^QV4|mc#UBis1M4S6mIp9Cu@;+ttrUGjzOqZ+Qf*EAA8kPji~p z)q}Gq7=o<}%wNA)jVsxH@;K7R`*Uw!o~{$y4|7$9>Zjv7OA+oJ@#Ng5UJJ{qNkwl> zrc3eKFV%I#If<|H6z8r|NFCTGZ7~VB?mzdN{9D*3Pb~(wam(?2xmm%CJJwPPo^1U? z7U?|QB>^zat%FH4_iEMQaO5fT7RLMu-{;?Kdwg@zuW`Y;?wO`nO|KmbNce_va!*M0 zFBy+Kf4oorCS%|a-H$YLiRxTZt;YA9iBC;S<#J667=;=)(%w@BTg&Rr=NFZ{D|=sf zGqk31DX?*e?Msmdy;(zqW;zNq#yRYcjLIyU^Oa3CyqC;3w@X)o?Eh7uFZKqQQisS> zaMGtixo@24SfNfAO^d6l78G{|r6wevuW1Zd%al->3r~l`Qp~k&`*pM~kC|TvBuuLM zLvFq6Me8vsx^5;~8x@MmXGoTL?guBWt;lfj&o#zkjULFY%6FOhr;Mf@6eQX@P zv!EkT;?J$hd2QWa<{}L7`XNH~a`htj{kp&#Hp+h<=wBzPccWftruOaJ;>c5hUyy9e z(ml3g&1b3QmzNUeCeuviA)$U|d;je9>7Q?<{y7XX&z_Wpkceve=L|8;Kq286_vbXW zJ?LPhv@7m@N5W0jI9WJj5sx#@6Eh(X=L8;r@CG<#EP|=-6@aI~ccDFy9xgb`4x6`k zY`N+pzj`?1TrhQVa8>{hu6u>%1M!H##jrip_-=G9a?1rL4g_*R$#CHJiLD@823*Md zcflZA-I+5Gk05~r+yBll2@vVf&Hu?LS4Jlbn#O|Mg$UwU8yZ*-S_jGJiqpiH$d+ZH zQ$PbOh?hVuGS>xXhZ&ZKLmmCU?ek(?Oq+g#atv@3sG%zaL2NNAA_f?vZXQH`K-vR1 zHjLPf_f!d6P8=riX*0az)?_ z*kLAU22es%>Wq`XWP=ee(2*dR2~H5jCsdXO=+SIC;RHI|-oiyte8OdeX!5Yd6?imo zV&DbF9x&Iv1_Eh#0NiDaF1RiST?@kN;JB~|vO4-7PhSHt@mXDzhZvj{TgP0N1=!Ny zF=%PzzhFp$74YE1PM9^#f_OyWj96W2`~dnpa_a$39&-SJN2AF>lB@_KKMaFhSuC1} zjvO@LoeGqv{^Y`PkV1LB{>AT>-wR*}nfuTx9c>OO6(J~KS6L7!z=s+(fSy9;KEO#~ zh9PiKfRhUvfsO^`nBYWE#zF*nY%vS;k84@GAeKJhHB$T zQE4==J~Rsu#WkUWGey;sp_cJ-C}}d#+O=MAT~dP>*Mt$y0Od>r>qgsPOdxO>z?BOc zg{}tW7~`&^hREO=ab9a+Xv$Z6M;r(vBM(;rGPt1e=mAj9EgU<_SO6~1TN)PF;w%rC zb0H{HL_c{s;hZtWM3Ffv%NV)hbZ#j{0G!l0pV7a=hDd)(p>hj-eYg-PbR!66Y$c5~ zVNQ4EI=@1C>YNQmwSNl3X`&Vrjjz;214me%=vsMDDDqMz6txIxh<+vqdZVvf)`gBh zrhyS*XaUrg82mc+fD9$4jzOy-j{Yy5rLl-tb41~>K!?$MNRNj&1O_Sx=K*rS zb!lj65S|Pt8ogT%!W(V;Z|2p+-A74_!TGW2q$s(zH-J{^Poi;=d=IT+&|08PL4quH zni|%Rw!|dJ!I^=-kfK>Z?xF-?Y*iR=-9)Y|{p;UcD+^};T*1&Bv=1mp2lpH`bP2SE z(6*SHa4#K>rIPa>xmH z9peHaNCAHb`9DP`yRFXrYrqsUZPkQDK9eIb0nRACD}TB5@1cj;v5S6R_&0KZJGd?u z?Ty;H0vE#8vDU=^cxwD0x*X{N;5aaK@^A=%=cM>_3yc2%>`5};%^t z6p%ra(}Old8WV+vagise0@YlI1oRXLW{BfOvni<3c>Q-Fe-a)82A&wrC? z9it^t;0a2u<2_;<#016xvDC0(bR;s@(Fy{Hfzw3@Y*;rM*burAnG4`}|5gd>V}B`Y z<6q?&A`&ns(RyR@r|8G0ijMM2>ti24%^%)c-~fuZ=^XJcQv?*d7}EXS5s!AqSTRn!!+7t~OI=A~*5b z|8gaB9nq6WK1VCC?5SyV1W3}f>7Uz@N%qKNz4WiN+c1%rGQ>%szOf*(0UsI|7JVI= z>x_eAhUMTK05R%Vi9g~$7&9fb=(zZE*y8h8qVVLO7kFh8s}yPc04IVeh7be+2p1w8 zodts3#u4L92oA*#vp}N&R}vV*GX-LsO4$D`=5Pl8y;8|R!Sg+6Y-&X;5JmlWY=3j8 zY|w{m3G4&lx(qZkYD)l~3N+K$4xsIk@p5o6fCpTci#7(~b#X2z50QUb4)So2tSV!D zEZ{CN>xqj0U;BXqClEbGEYd<>J@CXW9I+(?3CdUw7R0~l&@f=;4Y5UU`4Rm}wAl)A z6=L3G2+GmLIirk42(;K@CMbBjw%|Y8;pb%Mfn3`E>)8(UwX9AwUFu&85msm{utxo# zjmmY7q?%SD!XwIRLY}}@G$2n928KYeo5X_Pqbj=;5X*%+lmps`PMd#vvn&=k8dHc) z<3eeCi};6b9RQ;=Y>)v$#1DFD{sYHlqEAh8rXdji7LEhuApqyWLYeDw z0UjEBC)yi>kcY>i?LoGNxPL;Eipx@za0Pn{$>(In2@u_@`&ZktApVJW|34NX|6y7f z6+~ziU<$`M1M=8Vz>` zj<}24GN|%Z8`t6t>sc@UEk&^Ls0o&Cz$|nW(5( zrJrIP7ZjONa*?rsc-+9yyT!B*KPq1$ZYh}uSqwO-2zMHw^z`}n`YQKaUSix5-KPuo zY7hxFzVy&QuU%; zQrpJ*9afUW*GHp=k%_OXETn^#ZHhw5%CuYkOPW#pqWcbwzFk7Cs_q z>xl)N=@P%T3Jay}&95pp9XrxctxkyVaaTr%&<6AsTfPD1_1{j9d_QFc zKC@x0cpKUb7g-|rG^u_nP;U`xN0X@d`04IPg)f`_e6o%AD;}Azt4+k)hZgV!#2>NU zmk@{;S%R?5L|ztQzL68ew(YA?Qbt`o8jCV((P5h%V4(0`Z1mqkkqgA9hV?xbjJ+X4 zJnf?$>ClF?+*Fm*=`(A66zxRnUmni0s(6I~sjY>2PICSmiezj=5l{az9$k^+OkB#; zyeJrXg!O-HKFwT!4C||MylNNnmXGKBGHhHsUe~+RBwD7M=a--a^-^-x6QwZ978$AH zqse-yW1yVnUd%o=yKQwZiaT$Oce9R#`?$(tiAwP*@L{gxxN62oVvn^Z!;yuMq+Q~R zr~jJdRqS@Of7MWgyDGL84Wp?U;`*`42Bm&@TKdu*g-Xx;sQY^I+lDaka#5~jEU2hU<;Ba)jkBx}#>n39% zN_-$d@xv6F9)M_JUnW8gbLcCJDEACQX+f6|}~cR1T! zwlJ^x774anbZq@&h;kd+V6=UGZf zO}Q>wD9cT4)+NdDqh3d+rDc8z8g3)ut2arD{D-Gnt49ziInA)c9G_vePl5NGDc~Fr z2(5=Fs82#CrqCzLr4+KuR!PE&2H#ySB?%(P zF1PM}Ze8q_6_RJ9q=hubeSK-oqpBSI=ZAMD^$l6$91-wM&os1(e+vR19vfYoE(cX2 zmn_iBF*Pcr{>@=s(>DH|vjrWjg$ zTt3^9_h%RfSJEb!Aa&)w=!xfs?sz zAiO5mktKKJC>iQFZ|b>=hLP|`MH-4m7a!@5)8S~gy?3pvh-FqAcjZwS(>(rUC2!h) zJKs-0qNR3A(O2p7NB#cf!FglXh(H<{jlYdu55^4uCbb1AMf}_W_$9g7h4fC&o^5R zy~5-NeZEdvj_do=Jl<-PzyBMNY)c7o`{t_^`Ab&XfV}f)!p!M{=4>h=+dEpii&9HQn!|Bqi3gk_JXdt*4d`D+D;_mSk6@J|S ztB;@Y#{56kV@oq%7LW}kd0N%b1Iyco-p>bRcrk^dPFr-$UZi|c8)E>-ZyKVu4 zsBm2YbaLdv_xWiVta|zUaN@;+k1TFoF(x0}m?%9rwPOYc)h` z`AfjkGn-1MGH%4hCEleDU_TYT=B#u1F}~#FL9GSZjW1LVwp0;PxOU08ZG-9}fvsjg z`V+Q>woU#xn!8ThPxWKUL_Vwqdf97M>PLr=TbEeL!OD(6pQERk4dfxs>sd42*HM7;xkKbdx+M7&UvI5@ZBKk*tjr=4+@q#zWZgIWn7P9;8V{F;b z_zG}Nv}@eVqkv>f?}-Gz^ioY?1(&=Pwu?zBl_|OB8>Z~*@A>J;*ZHmVZ_)H%cby?s zwZgo?=M`<=siO;WqanHso4*iouVe3qm+H2kVKfupYH3Gq-@$}f%b(U=eQcJ*!??tf6jH?QeXvX64oTt&H zUqyeN%S}cqnaaQ9thuTKS4&!w%QG%xjn4a!qE+y%0y*E%8dM`KnUkyK!4S3)`RbXQ z7fQ>64t8nuGwNtWhv@+_L#&93UM>4U0OZ>j*X0Y7G!bv_=o@qTzOM{sTy1zuO+^#3 z%AvL!)8E$aLGNj|SXnC6pBl7pL2e{>l| z7#W3mTGG*NbqBg@|L&rE;mG6(wSEG-u6VFX7eW0th6{p}p7U@X%X^*th*TxiK)6oH zLqPSGaY4Qpx`A5Tk=8L*ubXy{+mJ?lX6LI(LS4d}D3M+zFf5!K-7tNVj0wZ|lg!5^ znH-VvP&}Eji7OZ8Prf1C?ZAK75-km~{vz}qFJW^d<7wR#gVni5@qX*$!ykoXUM=(A z$>iR#K)AkxlQ~x8V>?FHyB@n4U;^xhmCZL)7EAn%?b;GPC5e9tODQ3r9`WHuKa!sc z?q|<0PfurV;} zG)%0=a*$%r2iTph!GV!^9rrKfO9k3~T1Tu*-T2pyYQ4Ws4^0QzcFnGu%WoGh@|G;k iMi-4R5H!?6F zF)=SOF)uPOGB6-hN+3*WbY&n#WNCD1Z*Dyf00000005!`00000006530000000000 z001oo00000004La+?Gp7R8bhm&!|P&V=Q}Xb%PcbQ4lS%e7^rRg6;YT`lo{=6)gpw#AZQUm&|_11`@Va>YlnYxK#Ugk!I}T}Kfm*x zd*<9{l2Xb~&5Nm&BuYz>P9G`vvvP2rL~WwvBq~92?qkMdICw5^Jgb*a)AH$BK1s_b zYk9JkPmw&G)S|YOS_ZWh)GTW3tEpkE<3(z*9()$~Z16eYbHV3<&j()sz7Tv7_+s!S z;7h@mfiDMN0iO3-j}5?i|MjQ@&gVprD&Tyc^r!~DNQacy0ACDzBXA4&Cg4keZw8(Q zycRfLUwUi-K2L{~Zv{RV_%`4Rfo}&sANUU7bAayzz5w_x;4^{m2F~}Y9(#b#&>`h@ z!1*56qaOGy9a0_uJ{$O6;NJ7e8`c0^f3ESEAn;VLP_z*^KbQ2_5Bvc5gWy}hw}KCW z4})(5e+Ya8d=xxC1AW}b7eaZJ6^#W#!9XM!wc46PR$EJ;p|Q0w6kAKQHrg1mD#8tc zSaUdJ6^296SR~LKibX9dvCOsJD}koS;c2LSwr!gvu8t7K(+@z*`_xerqdi|X;e>^=yEZ@1hlrm|yaFZ?yGdq+V+pp-FNDE6K)(onaS$o5A>S$qfglk(+{f?)?YXU?h)OC{LA?>+R!z$ zOJn&Dzny|Xxej@k-3jFN%;t92sVr6}D)t>2WRu$O&mHajQ1bB+o7KUx?9tBWJ$;W; z+#=_9sI@PzxbK+l>q=DD67JX!Zf2=Yf1SEtv{*ff*>+RMtC9A)uzJzdp)%gkWCI22 z<#oT}Ill2*`oywT4|(=m_j+?!C(vc2DvRp}*t|Xb<<}z9PbWKz%siXsj3lmp0ssL2 z|9AlsU|?jJ!N9;EHS_TUMj*`uVgs?Ki&MOdV~C@ZW3X#{K#*scV~8tQfQdl>D1A+M z)nyPX7Kr@gVg`s#zI0fU+l)(W@4^n2i(9=k3}&e~R2|T}p3Y#G0ae>%=9SoSFlYefzQk|;4hkBOdUdE;AAf)E z(13Vg82Pxyhq(F%_yEJmrnn@<%Br}eC^IkJjuS(#E?&KXAwE`CPEP(2@kTCS%k8)@ zTq*%I0oA2R`T03^+!%`CVTt0cw4D6J5<4ESYVVXZke|RF14WhxFf9EXeO=?-Lp@!1 z8CZZqN9Wo!!j!NA8G*r(zI@=AU%gCcF-%4fBm;B5jgby0?D)Y}n7>+52U8^kQx)Lv j=@$Z3CIGhPq_X9GWM!aO1*&lk@^kb7CjkHe00960lWuFL literal 0 HcmV?d00001 diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.logdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.logdb new file mode 100644 index 0000000..599525e --- /dev/null +++ b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.logdb @@ -0,0 +1,68 @@ +v1 +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000001;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000047;IO_000046;IO_000045;IO_000027;IO_000026;IO_000024;IO_000023;IO_000022;IO_000021;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,0;26;26;0;0;26;26;0;0;0;0;0;0;8;0;0;0;18;8;0;18;0;0;8;0;26;26;26;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,26;0;0;26;26;0;0;26;26;26;26;26;26;18;26;26;26;8;18;26;8;26;26;18;26;0;0;0;26;26, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,LEDG[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDG[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LEDR[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[11],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[17],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[12],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[16],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[9],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[8],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[13],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[14],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[10],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[15],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,12, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, diff --git a/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.rdb b/1ano/2semestre/lsd/pratica05/CmpN_Demo/db/CmpN_Demo.cmp.rdb new file mode 100644 index 0000000000000000000000000000000000000000..e64a3b1e4a99e02c9eec8151a9b0525cbea1f18e GIT binary patch literal 32374 zcmeFYWl&{JtN@6+yE|N526xxN-QC^Y-JQYx;_mLw41+rtA6y3=bot)f-KwqqyFa(i zsU#<9U}M_1Ov1CdN{tYriH7UjguqUH&$jgW;QZ04;y=PGVX7z zWNd6KU+*{8FH%j8Oy0)bf=trf#{ElH{uJteR5bhl4+6u7{9pVZ^bGu8+8g|$@1N^| zOe#0+%)`u~e!xsXaZSV7m3p~1ZBlc=dYR1Gp{Zh%*?Khk0;(J$P+17FdWg>Hvrm?YXb5txdQ%C`jbf zxwfGpAnHRMmV3mpLGTpiMU!S<-2jnn5g&i6|{7iYzOAT=`XW@zP~*p&d(-Gecc66g_=PGSln^B zqK!L+;eADXcnnzkB=NKpH7SJae(q^e_;njSS zaBM+Pt>ZXx*r_>BK2#>ikOzfXI*jmvXip*lHZx4coAczcAym51^EH3_9^x|YMo@(Y zFA+wo^l=8685u6&Y9`&MjPJE7;|D_ zNRH;X3V<75^!gOMkPnqk3mLY=NOT-WxcyxeG`}2fEYG=2NKm#Ld~=RzL)un;J)W=P zRVh*F%84L87+BlAnB*@+jiE3hYPQq|UkZC!mm~rkaIR?9fpNiYxfOnEXW1GxV%V`5 zxQYn*f=ETu#(lNdd0b zE(_qpa$kPjH-oa}r6tb2NJ(sdk)tfZ*57E0Jj0{A$!W)T4?vi8A52xgI`ZMik1K^1 z%_DAxztQ$m-I~Be4@rhWBvNHkQpe)%0YMR+?SQ0uK-%7OONA0kl$HZ!iBh+6A|QWg zW-&SZ&lKeXQ?WOH-;kE5ov+&>NkCSWhr0{0Tu)-u^xHL|bBR1EGVFxYNiezE>KqUJ z1m?+_qn|H!;xY^SM@Rq1z{0Z8uV?Oqqqha_bckB{Ai0snX)HxD{<|_5lm~KzbRa1t z3es+=XizDRVS7cNY~vA4(Sfz0)LVz{N{Qxe zJJg9oC&kH~aYrn``DcRS8_~9YE!0c()WL@vpUQ!dBj{`c?c?`lP?_*A{4LU)A!4NZ z)Q+sXhlfvx0Ef#Rk1UVCMG_c7!qUb77a>bO=lbEXpmMw*vx6EHFO2fQu3n^S?vc_v zU2k?cF22XZl+(v%{_IsI!MB^h&4XO|7hqUM}+G$-t0_LzJVX@UTxw&rQ}jAQ!7J%}g4YO}!o3Wb%B#2WC&acR))udyio zd|P&?xexp4WB0&9nOrq+`8Dn8FziqzAwBMFe9vkKMPrPn8cF71TqV=ChV~gctpP?f z$oGz!D52^vcX?=Ky=0Ev;g2fw?@7ucQnT(=zt)SJtE#om{FIr?Un((vuqi4R_MY{l zR;j<4;FXlrPWyKXkVNKRQ7uiL_C9$BIs-7g4|P{?}8O%9!_Bnr!MHuyOaSSYsoQ6h_aZ%*M} z%#|?Y-HiSRU8QqV%p^B9lUQR4MGB)

D)9hxnAx%CdRRR8gTa%E#f3)3_Ggi^h~m0P;muHN#h6ile1Sc;O$7&Cl#?IDcKq?ybUi+lAxO2oh;tBgj~MS ziYB8wL|(yK8DJS8Gs$oIYv$`@4oI(}bAot9$AO;uUdMc|NKU!zIoAsh?=?bo=bdns zmU0a8jbx@DZ@ZrgY=?ZIP&R(%{GaF-zv(&9c9XeGya=F5>klU3`aU z$u;5y{K>?VG0B+Z%+SfvTarf-lLqGIL~b6F%j8;7`ow>Y=}>=sfo916Q@$Q$0cFyY zgzMPEjf6}3@qdI||C9Dg@mb4@nn@x4KYO}*Bzuaq-!<~0=6-=@)c?DGSKP0WBLVxw z3z2%19et0YlrfY*VvNnp8%6Nf_un#?74n;*lXcyCtu}Wh#3V~S)t0#MP1y5=%Bu;E zK?hmwlH>J)-eDfwgp1cF9Tlr#xi_c4&3=OT`hrC3u$$XOo7aFfVq`Ag*1M@iu^wS> zU0}kVH7rQwxs|)$n{TvWEC2CmWzib3v%(kAz7M&$@6CMe(u`1!g!^$mnk#eSj zyr(ICslmtAuH^G;vr-ak_uAX7M5Q9#JUu=9KNQ9CTJ3Nr814p>~OVg(*izD>P zy1B0Zp2w$Q@qez}X1Ysp;q%*bj4;?=N$1u|@)t3+j^1Y_?yS`dmoDP-x9zDBR@}d5 z9R@lSR`mge&lesYk~=mYx!!{=gXV<$@b>}>g_K=IXXm{H>YHYE4s$#MS2i*KZu?cd z(zg$B`KR5S!#mu;S^>FW1BsB9J47Hh8ucz0pJdN-`WM+Ch0lIELR1K^-N~}fks1~6 z2*q%*jy%a+6MkY4E&QgMFOV$++fzzpVG;HT1e17W)D(4W_KQd zbokEeLTSMz!5Ji63?s`1QQ>1_64sswbRs>yWOsUP(ijYl zJ(VK!+Bv?-63`9~lv+JXoVRzvn`*oeY0r48z9yoYAe+VAz7bXn>ewbTDVYfi7MmfK zXaK4B2nJwHH8ZZK@UB9J?4?Hkd>jENAtBvqIn)7141XJxqzkk=F=J)0mr~k(Fv3y9 zZQ;wmV!j|?Q?IO{_to^I60$o- zd-k40g2XDCX?DZbQTkzMxE!MvCXCdg(=pbMqK-eXwU`X)pd*RkME_| zCv_%ou2VSx&j*sk@Wl~S>8avgxtt3Yyk{Az8LQ%!Y?n%%{eabv{%Y&+!T=F)Hv7;l z+d;9|0v%-yq8$^ydT6?lSEbf2Ivc(Q_}iz%ZXq%>%8)M=^r^B4m*;!obhvmGTPU{V zS;DVckJ8{K=yM!J!x$tI+rQr4GUlxG#@%Y|Xbnkc#kX2KcnQL~k}ez_c4tZix=ms) zTJf1=d;n}$%3JS?hjuKaR9bM(P}}vl2o6kWX7`>V|JJK6@J2b23E*hicf1;@a_0B9 zhclXN3v@S+v&Y2_P~#pegV!kB=)6ev+))ehWXQ;FFUg(cmm7PyEMh5!JM zYyMmXa%R`v_jgLm0GOS&+gtLNWIzykAR1Fqk>bgSMCq=jGkVEA9`SjQ+>+Lge^(|` zr0@)BX9OIt&NT%EZ-y)Vj0#Yn!*zaAa>RE-pVT#A@_~F6_It>GWaC2eYt;YphE&N` zzsOpS!w>TRh_6Ph|B+-s?h5*k_~J1_|JQp+PWL+AABPLt(9$l3E| zCH5HJbzivj2wIlX8tOq6?Grv#6pB`~Tbh_R#t6i@K$02)zSrZzm;`-0i#*t^xjN*_ z^5=wmSv(Y^g$r+`nBJhMzbwzfBo0TnQ3+ zeunNoffe)P!ycUWAV*-!h?l~2uY#PHNIdF=1xyMmh0h11gH{F1yfaX{hi;hPo`gjNGm4+BrnuX!WnKlcabE*-z!>d$!&02 zyY?YTu(;n87L_+qhbgbMr|*_Rk3gB_JV@q~J!|GQcPD+34mU$zFP+`Riq-M^O!RJ3 z*yUEoNlDvaltcA*|Gvpz@0g&0#LpRar=Oh#l*wvj6(Wiuc@VtNt_X)%lXU+N#^{1S z-#pzwE!>o_;#0TNh@1zE%2C}eIP0oFgqiE`D z$gi#a!9Vn&_zmbqS!iIqitR{kZQx>wrw-5!iby}hKZwG$TKPh8g53E{{&KnX_Zt@b ze)nK~V?8r8PzqJ55k`*99h)IryH*+|DSwEB6ifM$DF9F3sx1cM8qbMyz8C8C{(Hhy zCq9IM%2+BRc$enljGow|)tY1aKN$c)jfsK0$L0M@mm4_hcW|aQy#ERR8FXz*s^9$i z109}(jiD#QWyb#R=%0guHBT}0`y5**5whcwTQA<9R2o17Octm2y-ml?sRGMfKim$c zMd+TjGpFs&)-DE93cen>M*jQKu=f&45^R3G>DpKkdtdP%3f;WZF2};6trN9)iZ@>w z34$jfW0R?%iZP*~(kT%p`r-$EZnFq)E0G!-kxlFM_;O?MQY<30zyONN(v^EqC;J)7 z^0&h2Wm+U~J(i{U|5w=Gm?yc@y|`8f^_qasZSt0bf4SEveeU0=8~p(hBkh35RkCN+ z78z}={&l0x|K7I{ampiQMUB8kqr)={) zNf{^F7YV3bmUuycQ?m2gSe$w=UV6s{`HR|RNrAi;r;IrQF`yC**Juu<_o!n~*+r0; z39y`zm@EE^`+bKac!Yi21+$SR3Izjvd3$XM(E}DDTm?>%919}N=L-Z%BsFWjwJS@O zyQSk=>l=$~!!?XBZ9VwSYKdNYA08)93g2qVEq_?lQ5m-u&I>ma21y1fC)dRnx1lxf zD)=o$RT-*hYW#FFE|P!u&>4AdfQ*VJ-(c)TW!Umc+e!&{Sof*kY%6`z!AF^QdVR;IO;a4N~RU3-U=$swrj(> zH%$qpKj%n0_(`Q=FM*eghs8J>FA6;ohl@^b`C=_vBxD*j`V*}O22#-kkyizQ0|x;R z+K@C(cQz;(W@-jq{|uYJr*dxNG@LthB7T!dRMUU=`5f_qNWRd4)D!T&+0pSiyF*rK z5QcERv+YHPRy@ewef;_FGw?3=^PGF&-^>QUT`6Caz(_y2P$=(_#sJ~lq+tIRnYQSp zZPNBiKdjD}i3t}93dgU{%onwR8R>t*;LIQ1;V8^Ik>9SmSf;(Dh}o67gk$z3p8azp zeF=ro;g3;$W}Huj)M>6}#Cc1a$BDo7EfV^dnP$@=jwhX(+HIUF=lStoLK6;=*NF++ zC(%a0A(YL=&I&VRrYNSnlLpBK?Yo@e*YQ={Xnn?K@Quv?A^;J_ej8=9*Sy_y0%f1- zatpqa4JrJ@7WQ_@wbrLN|h zbfI{fA?WSyXBXDuH^on&wGjm<*f(8!FP7y#NjZ3g%h1d^X<#X{Xn1*Orm@D3^<^LQ z06T(h6S7PceWTOEZP7Ys#?)({7JxcxA)-V_OgqLh4E2iZE(Xh^E+}MwLAsQCT=xzt zou0C33G7dj^mm84Z@Bq8rn$FndHU~X=4{7w86d)H*60TUi($GE*7sS2S?A3Sg5lx> zVloyV~ zJ^t$f@7r^$M!n3K`+c!s_%2qcdcEaTdC2ebo_(NRSnkY+k#{r)26U znD-OZ0V|LN-A3hlLAK|!+7w;gp2{BFANFeUR^?q2aicQ)8riAXnXPAezVeZOb0aCN zgFGD)*_`vU`@Fd?g23k$<`oi}6NYGQK2zV?th}c^c7iP|xLihAV-=qXa*+r;FuH$_ z3x=GW`Y?I#)u+0OY_?FU#khA2co>NsI~x1puv5-i zJ@8)I^$ve0gsS25ehvS3{&r6&U9otL&w&GFyP%MmG*8`=8oB^$_9~J3LZfs+U|p-X znuL^y`(Z@5SeTG-s6rjTY-20=EVpv7@U23tkzjKH-3yW99NduEjI3Sql)s z&m$~QpFJezLiVDrCnRL*nz!s!TnB9N{V6e|d@n#w&MUMgydmiHimy<9H2f{FN6_%9}#Sogj{@jgsYY@*EJ|ztj333nDaLB7R3{#@h9M4Ts5Bl>vix^Ir!F)a%)fRxQ5F))Hv_sXnNQ!|>a#$lJ*cz0$|C2oXB@?96Z@ScRO7qVLW96x4d{m-&*O z5bPG1RmUbhZXjxnZNhlKJMB6|VWOT`Jo?IfgtjN_00Df1FIyJ#T$A?U9A=-tzbGFY zTRDzket+&GV6jNszgZ`6*ncD|b}JGX@V>wPkDbI%^{@T|zxao~hoBac0k}3*LcQ@| z$Lu%SCq~L-jeq5t=tZy_^0U)#H z3D9!~7$nV6!O0f~ggMM`2Lna&L7e=!NjgLhLIuyf&GKdtqOccZDI3_L`Sm8D-wPL8 zZ^JF!rbN>)`{o~&cfy!?Ut#{BY#J@9f1441sH|M5xxeKMKwTRM1ivAG8 zN`t=5TW3^My=4cE^Hij=7$}=xSB$1ov5qc=?o!i?*MZNr+2=4M23o8XESJ8oCD)R( zp+gupPj&69g8xyb{6pkhln!A+Lqs$fsjA|svCd9vZ5ln|v}ipWN zeqmh4wxdfklev4-Py$;$VKvDjs{0y$@itOzk_N4yOC|xhp4t86Qybl5Z$CV_db{-Q ztmU|;quw0pOwm7R(6t^~$5J9RE06FvVh!rilcP%$(Xb!aZ0Z#%jq!Bge7^m7z#>vhR$45SYoxdos=wvZkn(8~O2|zO2>YW`>6l9}XVe^^yQ7Ei= zKqJ8?{1hwI7gP^}^>y5#3Kk&}gOC#I59*MnHH2pZfkvqP$6x#LRE&{#smhUtzs1(~ zc~H&b$6@e{12Sy?V7`+reWTAWrKn{2&K#yqEcm*5={f6{-?+*zeedAJ>59Tey`Ma! z+|CmK`7(^mgOIguGeLx2l_E@+*tYdv`Qp3^2Z3H4Qf7T$Pb57FN7^YKpgCR(Xc7IE!7SV7mam+|>k6Cq0^poJDnXIQijgz7|J3Ctp zYZ0|Fte)yVpe_fycwEISOdmY-{aFDgUX~aKygB8d(#eZSN5g`{!wrL>F-cxHw>V={ zg~w<&qBa{BcFZxa!N4CMJZW|TOa25?5`JRt(A=P)jIS%LU%gFg(Ykk&th1cNPV z(_g-wX=A&XdA17-<`5%e{dEVvon5%`)JyRUo4ysrG7=onM6ngc-;1LyQ`qH@^}1_% zVH1j7Kpk4&ZxFY!a#k9tUSl?e&IpkxMDE_6K*dldU2V^bwPxW|_AEBjDv%+oEf>;h zODTkpyx?alE5y7gBVKdK{JIs3xcL58yuH`}ncgHJ6i+ED)VX~g0`{;thu20$@1F3& zy2b+wQY7;vx{2Hq0zVFhdZGz#u4HGhOd`rwv(r$J1TsT%QlQL;&TIe42O?u|kc^{k zfwis@@Xb;A?q-D~NKsH~?SfRRiXkv}5P{;T_Rpl#BJ$)AxZzT80AINek!3-X-aR`p z8~uc$a*;~h@<|&)DUvFUxAG0tT%blX#rZvWpDirg!C$i%c<*F?jrtQ}Oy9fRfXeoN zwgaVo4mN3PNifB?nq-f!SeB_tO_0_R<-ZYj1~nAtCAt-0%J_kq>DHKf+h=n^EZo#- zSqoKcusjJvN+bEKenB_E=7UQ_TwED2gnve z)gTqCjr^=s8>EUg_#%4BZELT7;BW!D$kDevw!jsh(OLBi)K?bI@WTn9Mam^Iq=Hb% zy;IV*JmS4)s_(6baSb$ExEWw}j#TctRlYxH8PUech>?H0z;IuI%v!N7&QbRFS0*h9l>^4#g=$2;fog!rB9f`<=ptM&kq?Q4RJ zw^J&N2env8(u_d0RB|uw>xGE&P9pJ~eZnl(ARD37hVxX=`7YtEi63<0RWA*>ah$$A zq|C4zeL2!7ol>cDi%Y3~0VS0>Q;-OMl80j6DtCIq?O`&W5geFB&Pt@aMX4!fAgk6X zH->}}l;f*Rw7IM00)@-@&4n|maA=KoiIRTj{C3jv;t}RL8Jf&{QMoKX`H~br`b`F^ zldp*BH!M)$1vz`H&)5eUU%hv>T60YPRqdB*N?y}c=(tuRfCnqrka-JF%_8JV`L!Yl zxWhw{htb zExuweCuqVBw8Ow`|krid~6;->7xL!`XsDC^*RLaRs1Ao4B zS}DvRWu5ciGk5eOFlW~Qh&%^lbL>o;x-PT_h%0)6Jp}P&#+sp;nZT;^R(>)z>#2g<^d`EPHCZh)3qrmKHW>+Ya{Lz_lA&(-#?BoUx#0LaoQi$(3VP%+-G zc}{oGsx-4jsS-;-Xfb5K81<;O;)4SbG8kCW!0ba&&=lO#uh}7&2aj8SJGJ7PLr7Qk zb*9Ex|1CHQv@#vC>JZ{7HJn?l<@!a@xXF3>CFs=`ICfdkTV3Tp9BHNaO$(gcv zit#x5wcm6%GtzYgJjCeW$*T?(03URr%5|;3lUi+Je?_OU4GPlHYZ$G1d}`+9H4Z_r zrl>;|T}k}d9eIFLrQ&lLh6>L`5V^b?X{F+I*=IwORq;It#FF*8-H3sYPoOwuO3Vw6 z#wvOAiN$uxgK9HHGm=PAq-x$&^fyF`H1UEe-47&++(D0bST%i>9AXs+Rq;?_z$B4i zZ3it*hr^;HapPOWA5Y!v&c(Qnie#M(cE&+Ik)<|?j`S&0i-%DH-hOC~Ru&d75*~-q z(%h9%uEM;>nYv;{U5Vlmn!&KIgy@r!uGA-CvvNOoZPI^Dy zR2>koGYo!NS0By1BprMwNRE+3D$>;qmWQ(f=VfC)MbE~Y1gq}eOHn4=pV!exsjg?D zu2Sg3k5XZ8a16+U)2_?5_}c+O8g-2bHqLCphqwf)r^2M;SOajFkZI}Wu(`|G|HGS( zU^*c*B+EYABeV)*35{bWR8YQ~$Vdk-h%I4R)$1D%2TSAeKxZM!=ql{|(Q!{I_OPs+ z_0qEgDbvubVITVFs;=S;cvCQP{L!UfFp8wya6c3AMdfGgo9q z$>wM+`C~GwqVc(N%XrL^_1RoOn+e`!;M5L*%L>3enDpjVi-B!kt%LBq3F$gf!QkFvim-Fd`t%v^0(ToHPN%*hV)rBP+!An^1Fr8@RGHBxT@ICI*?hfad>)@$*ytWCV-PHngbFj7!b}>Uhp+(>@q#D;5V65m31t(hVsSVv0ubmq*-fsD2@Gy0_w$<3Agjz=nt;jNM$ zYHsalsyJ;|<$O+G?PrN}2!Z++4qs$-X-QW^GQ!B2bk|Z-&7*i z5b33DRP$&Hr~8R!6p}1V5@yaE{I(Ox-w1jVBRG96MB|61_L=!3)92UR1S9dKMsD#` zrOZ~_7|Y_NKutDGSBiRWxUiUdJ!wM0)O_V~y&jb|LOY3qw_d~vGUNSRJB)Tfo1mx0PptQaDunP@OP zgmv)F<)d^Jk5&vy0+EgKZk-T9aG7j%>9`-1V03Y3)~B3c7t29i**Oi{9xcwSXFJ;b z`oS1Hu|p*v33cr6t021U5+&6b)Gd7Y zUS)I_7~W6EN0;RGStcXq0*>K(v;>hs0nYhe$al4)J@-{O1Ttqw4~d6Q0ORp>`UYW4 z#R0K5-$bmd{3eXMdlz$oJ2-l)}y#wM3g-r zE#a344g|JdWl7l3c_0nS*hrLgFPd92FqJ266PmMuV(o1>LaPtZful?Fai;Tds^jjn zbZH&^GBKz1W?<~2OJ(BQvGF#ehk_OIfj@B6q;rv3(+bPR+&2vjB1{*oROAU#D);e3 z?(-f6( zs%=`1szX#*hCa4My)#g;>-w7_K7VK&6ywJ()~t(qJs_d4MF{$d3Ja*ZjNHW8YPr#s zRWEit)N15HWN$th30Y;qojGQ*i4;^Jes2N$z0-_t%YQtod2nOXfKy}?tbk;)z*1u0 z&K=bygJpbbh`Grqek>Y-e^rb`lS`cvGwr_oFyRf0(Ih6|sc?KQ2sP_;+9m3&+N;>b zLuYkP{6>(J0ts1>f=-0li^rqDjh%u8l1DPz$yvwZ>Ay)6m%^;`CAtQAu955iZMy%F1no9H0d=Rq6zpK)tZ$&Sz=h!N{`{ zvRX1lg1eo}YKxh9giER{U}c|Y zDW5E>tSrBC8V1b}urD`F@>rJD=K2SGR;!mABFwA6%p`~?LzTjA#8|a!lY#psJ2Z`h z8`cry2`lf*{?Grh|LY6Jx#ghe0jGF>e))2g*L7Qx!p7>Ff8&^VCh=v!X46Hy?aN@} zr6uIo7&Nqir(v~?*bh=sUwUw*{CTL2Ai}3*otR(zsx_@Uo`(Oq`)ShQ$)@leSb%&)qHcG*2|FQee7TW>UH}QW&NO~UeM!1(Ckb&b z8D~R_oI-~K^dOCi;7Li7<=KnkLYibbi1d1z(wdUR55$Rd0@80i(BYoKzXkpd=5c3H z8K00O%fq^#BfKB>Umm>=+?A+NxTeeZjP+}Q_A_A`FUI^J*vfUn=;KFM?yL{P+o zbMns~c@k0olzRTE9k?>=P<Uifb4wN9Jd~6TuxK|o?Pt^QHAEep9xro`)um#0{ z6YRnnDdy*hv#JL+K92|1pbyFFI1c9A%D9m@$b%0#xTk0fgc?0e|IuaXDmSBlM^)0Dne zB-0cST2Bc2GYCa@#YLSYf@fwcqMi@s+9(00;*bsESNOyRyc5#T{Bktpl`U$FBoS98 zEBU9*9&Z3p3GQFZ*g`5ga|d(EnF3eOYt*I|s4ICl?h_4KjUfsCKn4l&A6Ete4%tpBEU_N* z+@0nst}su&qBzn~>t)7UYyn^NR#mS%I@HBa^4Tbf_tmXl4#Zo)TZ}-8PqfHVei-X- zVTh)KNI6ri@qf}}?fFT=JfCn9%gAt*5V!jZzMnzTJ0oi5e6=UIKzKajc|4+kMbyF$ z8ymEHf_exOldt8vnf%d_lOgIhUIib+x*)eovA5kmL}FbT%3?ycIyKnzo-$O`ZT|p6 zIX+fGxjmn!1PZH^8Xb$<#}gtpCY6%bG0zqv7CxQQVcqktFBJ+8lTq5ZIy;yR+)bjz z0pL+NYApZDzL=*9hNg&WBLplm?@jHnD8}+6*B3b{) zc>pAM%TU+~XwmMBUsdbhM~#8@njqO`(y$aRohzG+W^E5Zlbk&fU0B;eAQ7Ek+c{Ju z76|L7S6;GQsEo^&LWp*#44eP#KiY*i&wc(w+Jy^G6pBB2TT6m}XjSWNCSoKr$y5`o zjz$$_(Z-o14SSD9x1<73jW@9#8KD5*2t~7QC8fB>mf?nNe33Ld%o+<7;w#m?_WM#8 z^D7bZbaouUc>-e!vCiV1o`j{>dXR&7e_1nT;Wb$FgUzo3To5i8$Xa`|`q=jUb0t z-?8CgI+88riL>Gegzo+dCKSShbR_GPeWoIff9FEm%5w5I&lqo9Eg5jn`hBkGN+~s< zC~8_d-XmWf}11fid8_CqIwLQelkWLco<>?&?es z2Rk7l2UTX~Ay~Hu!JO6k+rZ-4S;6QXtIKhMZ=qpCmh)+>X$ZB9!It!s2E8E=2W64s zuUH{ATrzdtvpyIc=~@X-b<7#^#u5jExZB`UMrMcYz@%n=fo-MN$H!llZySKzX244= zEWtD;h*;$;Uv@mVf>b9ww+I$MEb)oi;OhCE?DsJ6-}ZjYHyU_dk$|`h&%XJ3Ovifx_vblLcW z1%wFXm%#+B+awxkY-V4-PU$4gEh}Z^cKM|DjW^HNRiULKNYwV>Dd6US>aiW+eZ{uZ zzumO*5$XVz_X{5+1o#5LjQ^{_bL2$ zF2f0pJXnVRy9^|IV^bF>#oWJM_;5IDDa@Ot7`Z5mX4|TcI`N=0``H!{_-Xxl*z4)9 zj(WdH(1uqKB)VE1_F?g4%V!%#HPq=wydD0c`3qT#FYW4;)jFcov8RG1DCuKKx^#%P z6AnQBu9&2etMP7D`%1d2nDEya?=dV+rDqfM{_^<2@~#sfspnVZS{U}LaYs^!k`xG; z;*)B0(IG(%5Xs}gfl}$!$k>Ume}iWV`VjOWB)wWM;h{d2BGRMeUbqneDQq}(S&~DA{a%)4`GgU8sBoJ;9{R#GsE9^7h;??QY zzQNCXdAVVhfKI5$O;ozB*JRq3FPopF3Nb92&*vyD`#Fk!SXkT&F83OkQ- z_Acx7*W?znXjbvHeDgKDyf2xn<|j8nOIxi9;%b!hGMao9zfIO0rw z2SRg`?bNO##~{A;f3F9TX~!PhPDh>vI_veR)UO~$)aCDgS3^ul;#w-bWGPXKH=hHw zaW3(3fJ3~V*wa^5WOG@4Ru#Y?R2;D4?Ih>I@rC7@Xf4XTcf+8ighl7W*>Q9Ds^KS% z5W0$%7J&xf6uYSwwL~KhUq%{EHpbk;@37)`ppm#Ln~_H*BJpOE!KsZnh|qE{pSw2E z!cDnGZp}F^MYu!7_f@>s5C>4C8OM~d>^S~Q)9$4Ehl?`#bN6*aoJpG(PYhA>ro2b0 zYFyDuWv#&<)(^GQcOnf?e7mp09HR@=M$u{iOd$bXE6E^x67*n;)D8eji=m%c|6-$Y zDp1?br3g&a8(1B}`GwU4e~3XZ2gs>BN8Rlo(I|C^Iv?qSYKTYuf_d`im+yvuW>SMr zYL!?OOmtq~vG!hnXc+0Z()f4m8tOeh8>Do$S5dOpcy(8%4W zqh9tCYdW#wxjGeXtsEWEycbgjKBm|II%^O)k{JAz&asU0#K81Db#6d!u z9RlLy6cJK=cfRpAxX0JbJ!^?uKwVW=#M&IXM^88Re`S54mahyT+;^#{CB*d)=64*Q z%atf0pF5W)9A`Kl+d8Sny8XRN&j!%-mJU`@qEe{Aq^lWU|Mr@rS3i{R9XeFwc<@r- zfjiz3%zL4HsO=_?EicCU2drK@z9|6C{`ucVdUG%e znq#Ea;V;Tfz}^&BC_2uzZP~g%p}i7IOj^hA8^b^S8r`bp>lZ2kH1RD#p6z;~tp`zR zZr$0O38&CkLB??(v1zVf^C7Bx2=VZ>FWB=~zN+*vo1m%u z$+)-c@>d22bj9J{9s{q}G?5Y!l5x%OF^gLL-=C6i5`>_Z&$+0HVNE`5T@`Ro!P;ka zepW-He_%*|81fwB7!=(+i>& z2G1c+qZB65y2|REP^7q-IS}`CT(k3{<-Sm=4C14bS#MX;xVpu{Qb1nbNaGhr`qff* ze)We+b(Uk=B?wO#a)Q2(qzp2~5M?AKR(m6V-dF(TvHMU~>M%gu(y%x886N_5#?6A9 z7pmuO&=_7f{U!CBdb5y3DPFG$lSh$cCMqyWKrV>2j5c7dFdn9_Xt}RM<}c3PE4)WB zyAf1d*w5g+(90@Z)mV&k0F1C_$zMJhAsDtrEt!8Q4xC7LR364m+~a=@$Bo&dn=rK{ z$DlCYhp?*r&$|LSLcVBVHZ6P>B|CWpVZ%sZnMztYN63tZ2RFf*0b&eg zGDsGFrr|NeqX)=DS)8H8YfuS_2*%OMp<`#aOs!Gjp^sto8~l}NXG0vP$@e`=qWgrO zh0V;QkBPZR>~@_eF7~|Nu2hM)Y{E=$b%&6kNhUcF$GFBQ7_3RDC!Y~DcN1TxPt`Fv z>ydmOD`jG0Pft!+8GHl%twh1cQZKPKLdK}_df>b8_xah9j9tEC@@gm7>=c^s`E><| z-k9#0jbKbsT{a|RnTHp%<(ISefVhayiz-KujFv_x_Gq4kf>i-Lihrh~5Jgbw{$Gjh zo)hk8iOyTXX%pp0wKjxqDcDpNjSRD;)Z@lgrs`j+Qam&sOXxa8tCn#8df-qzuH|3x zs!RbaRXe?!vUtk&S=4yQ(pgikj^O3L>qL?s--SYn|I+?N5MPz65D zdfPg#iT)ArBs<{!okmh2j-k{ZBr%{eV|LIe2oyWRX3Kb)FK3}St4`Y#z>k$qUw{_I z8U9&Ke!ipJI&xFO-#6b!GfTSoN7pO9TZPITXv!y3EkGvo0`Gyxn=`HDK+jr5#C4HY z6WOxdEHV@(C4(W;uF}=+xxFIw8C)M1O7Z-)FyWp3Hoi@?$23eqagW%I49{do^3X8| zLW5(*0^j&?X^Ruh;~ON!U5G?ut~F2zC5+nc^BY&l5_U?E0d7y?j{$9GFum;X?#9=)W8&FX9EY9gT=%xxrbTmd(QlId@Nibo72}?;C)1qEu~;% zdXml4;+-hf{6`}IYb zRhM8#B9#eNf#}00O6WCbYNOH{LQm>lTo+Xc@QW}xD&A5!&C0aG%mZswe*fZ%L_E_H zP#`?G{J)AV`E%OCkpX6(8eXmn<5@H|?)o($L+jZJjNn5?X~0O2?@4Xo%ymMNC158TH1b5o$JOi-Pt3!!E6UE#xMd zj(PGc=9zxNwZAhr(OVBJA6?$(mtHi5lH2WrD|p!BWWfe*#@BE4W3e=B$t3GNRNV8F zW=a_`Q=Dbh>aQJ7+rv1)^QzWRmTxU&MRD#TnR`IQh~p&g4mqk&=PkzIoeENX#{{wd zM1<8gDrv!D%=Ls6^ZA6LqmRV{8DLh092lN`^HS4IufxvwQ!Khf{^q*V)PE~7bn1U)@ukHORUwY z)6Gk`=;|!pz(`+Ndq!UJf`y}%4&-38zy`$4jB2VI5 zid;UpL9w{A!6f6393pWE1aclTt#}-(DOJS3AP?1bg+Z3l>){tzU36^PW~P4Zd66=Y z&Y(=cVws5p#SUo;WYq}%dlbxWB|BZ~jX2jTl*}M2!K@-OZKGm2ha4;uddP6egrIWr5Tb5VPOoOS{AlHC@y&sgicBCwe`nX(;zwgS~G!0rM$z5rN!~DpbZuPpVN;+H4 zVLyqM;!nLzgL)Lt&3*=6X}kfAZ3a1x$B)2NaT=%0n&22(qDyr65a*-VV0$Sp+Q&M0 zKMg+G!eo(tF4$V1i#s=YQSYf?c~NH7^>55h6&^;Za40}iwpeF)>A%Px{n`Zd<%Ma7 zvYs@52qw;r&|RZl2$Y@*H{ru=;l*L`XPWwaC5z##bc%Utr!^PeX{{VQ3KrB6?AG)o zO7f8t_ONA5{Q;AH6Y{zspb*@<+`8qP)4q)9mg1}V)fZ5NY2uVf;{s4qp%${LlqvTm ztt^`%CYSd9yWqDwPhQA56Lw-r&P`IT4A!3w7~;^F+vl(&Ii$csHDWg3{EnqUfQ?@= zjWat3I0lJl=~jrODzIxYdIn1xRW?VUT=9iysiP%>ZOB9np<$IGVV3B0?n8y7Gl1MP z4mqmJVmrg8#B|vb16?HwlUWi}G0$=y%M$BKDLhOz*L=OL@J{uc*w=fU{URU4za^A7 z8ZGU72PAa4%c?N-hkg0TGdSv#HbxFau%BmS>H3SXJEkb6X>QDkg0<=5&+W5xu@0UH z!X%a1A!SFF%8T9!4v!x~((M8*^3r{Nb%Yw>2vzAxV1~4NQ!$&Psj~bVqIOjE@A&Ome%_}ms;Y#}oYj zh5TLTknoF8uwP zvs3eS9;P&Owd0S-OMF|KHh!vVg*}CnT@Jex5ZgE#cOoi{;oVXb0Q1A_tP>4llrTF! zqs`20|6^8KZvwxJg@HI|a*b?$w2J0V3;UaC=DQPgSw4z`BJXvfpcj;X^&--hX6@ zpHD`6lsXKAhiH%Ih{Mh1bl(SSVW_N;&ds<T?7kH9I2I?!(M%pqapvVt4n|S$%2GId0ZuqIRnUQ<2WXrN0XVcJ*8Q zLcP*N0eQ~wNoAQmzgtBxwxZZ^W_`F4okf50dgsZr(I&jx$`p}usQakd4~>5~J3ZHu z@C*RdXBk(9h3D6h>qcUo<8<(i^Pyka{I2jK{XBiCnG|X|{aB|fVQwhl^GsrtMle@V z?j)`VJ97lY)lSkA`#C4ype_GQ8#(p-hFLJtl5fD4#NV)%`ilP|d&h2>*>R zRlM=L!l;DU2FFqP6qgj+3?dOpVNXBz`YE7nQet4w<_lvW{*G;_RQ;$v`(x||#K&cG zDuh0NkHi+bW_Z~=MS2Hl6Ytx)W3cU9Jb=ZEH{Lh$F_S=IoP=B~#|LP2*_ZR&Jx^#l zou9WwUbY?69-pPgX-+8FK2jPbzrPW^6jbDs746loa}QW-{DC?=YV9-31Xrr%t)xL#=mQa_%gviz<4 zxz_cbeH_)Css>BG?Z+4@ya`Mr^BjKM$!B88laOUe8XPI^M~0F6oV*xlSk$PP$u4+o3Q}tR!NyN!z$|82!7} zTs$47aTmp}mk6-yS;BaTqN0)LisBEV$cAxiGq*rV$Y7=E?@cRDudDJbCi!td)_81c zD57=Lx!||V+CVlqxD^=L0=J?{pLQ^(hwB-K$u*6H$_?gq7TqCS@e!ZuALON|c2{0B ztF!WzXDJ0qUzQ9Dif)&BA~n?Q;(&YU0TYA_J$CY9`TJTtn+9J|)8w`Yz&6AOEE+l1 z%S3WpBw%YzDPsYA!u(-nC$(BCpp^m9CL4PU6CNOsTQp>J7T!g?BG&asaRd8K8PTQc zb1EA)V4_lfN|Eka=CakTWIaq0SoH4Nlwf#q08!>99Ww_!fyCyk9U>U3nY}(@piW{NhL+4OJOu|`Bce~>Mur!%IJogBh^;`CWNqWaQ=DQ zMb?*)3eEjOzPtUH5b>?_N`&R4kWvHdF4b?D^2UlOS-=Ai#guDeuh{yA2@1^WfF5+X zgy-S87GjKW^0{8xQ=vOJFV1kKi!iTV3;bA0!}pgq10chTuv?blr3|rxTrN|D2h=LY z!)T`Fx&fh(R`FumtgeO#%{#WUc_Q#dvxW`mQCen?t_6+k>D?wMz_$-cfERo!2>|n; z=nH@w*)WQR9}6^6w{{yebF#~vvOP_Tm>MRni+%=!XY(L8 zaG5d%jnhMtZzyJaEhI2Ivj`DCNPfCAy-_OnSbjAipdqiqlN*`_C1nD(yVywa~ zPFE$OR*aot2>QgOO#&0CtgEAAr8}9>Uq5PBo)vzfoNGQr#C!_RDb^D|0a!Lpta=fZ zNY9U=v^TGE?=4g6Az2tPbWtd3kGKhI-@8} zV%_zC+Td8#c!NXdI|pG~BbDC;Tz7IQQhxGOz_XYu3^anSl82(!3hxCr7KAQvgJ`D{ z;GlFvSG&8e*VYjjv^R^hBr z&7z=Rxl?zT>65hMUH$}Lfpx4E@isz?&iet=4cG#^9d|j}R&%}&MSBa4g&o`Y@|^t^ z!9wyX%(hUx)Y7QKK3&lgS96oF%n*8w;GHgGGo8vNjp3bIMH%8&?GT-m3}80Kwxx*? z_~ih0KLVb6xO8K&2ZHTT*o)BcvL}wKvZ8d*==ZC-`{DG!lK<#;9}cW!qn=$g*r9gRjEPUA2l0 z+jL-Dcmk6ieqXDK!km=4A;|HTv1u4ou$lwHIhoRA=l5|0SN`+{0QM?nf;3bK+2PaE zncOa~!Y@8jBqTF;`+0Lw*2n>$d~8I160O2*@KSuRW(kMox*E>TV-h6$S8a%+ zl*{%uil5UYz>f#@5?&0rhe|()(r_R%Ts5Fh)CyW}n5RS!k7EUdZ~jG+!9gY5?FUN` zffavVsNSPM)pv;77ID#DOli4iAq8v3aCoCQc9Lf5;l_iFKlk0C3I2J5@ z**Z)rCaw9N;98SyYF^GKtuU4hf|7Sqng%ORC>ZW|i7dBe1V+H=@Cz$+O7O*+wPDX#wHh%xM8^uJdZB`Q<l6wQT=gRd0v(*Fb(4^vfPo$ zu4tYD6S%+R-nbmCh$1oCvo7KZCLD=8I#UfDkZ#8H%lyZe9`#3j;+<+T361K8zQutL zRVxH8!#6L%XOZ0^62}xGy@UA0Wf#<-#dSP}S}IytXnP52HE`vZp^${Irpn%* zVnxvSaX9%#7jU^Fw7x(i`2h7EQj_!d!39@VBA27Fww1k1;N@1Tk0XAva!1;^G0ejM zh+^K0##4L+eN}xcojs@yY6R@1rU=$wf2iiMoL{TT>WzP>#J8%qySPP{+cE~bYjY(K zu|rfeClen+Eg(F!kQfCf)N`%Wq>TTSBHg}Wg%=!h#4)~MG)0B6AEGaB#||@4>*SLz zp|?o-3D{e^rQkNS;*b+YYQEZzjJKVrBr&?KV|NpuJ05bWyn%hNfWu?A*tu3+?6!#d zY7$|t;9|5gCrMNVYJwN<&&(3-)x+PNym>Vr9<^GrFGq8jDW zhZ*+E1{*Eo7Gz5B?cOht>kusfYSaU~0Bd0HDf>1dxReVRKGxDe*tq;8O@RMf&F2>k+&GG_Ps#$p%1beR) z7{^}=SqXpYFLG`pCnyf+GrNp>JBvwkf4xNu*9Uj?#;5M5)O^a^mgMdQP4Ql4p~mQ3 zxn9DcH5%6Co1+bECa*Cxq!?Fp=^;0agRqUUIT!>EjUgS|q08x+1@_qWe7z6d0#~;)sI!=umEIuF znWW{dTW?t9kvft@1=p|@QMag#Nz;BU;7q~q#Z2F$5D55E;$rF%9S+NA{jk^sRY%1T zHbM-)P~dw;v%;tmSqR(a;YFk<4Hjp%CvImiCAu7+sQ_ie9hywbkzSn>T4lCwZJ|?` zahF+|YveJYOo%G$n84a-Ziv$^yW(_&J;B~uK(0ZjvpB0meO(QkQn2S@ z03Tq7V7q4`xb}U9Sx|Q;DXJjwOG`1@9d()>GC0^>rBh`e14J{wo}8`X6PjPAZsdM| z=!$K14KKFNLyeF+KnhQc6P|Aza0LCA>Mx$_t47eAM{p?o5rvg?^tRkD zJsN`z?(Hy8m9tU&oWuUZ%$;dn=|R{?zKaX+TFmBs_Lu&5oVYq_GxHd`{&SCpPin)> z2vj=XSJ^QU8a{;tirgIl+??lpq7M&|X7_(04if z#){xU44h>9D~HaXZjH|7U2+i_(fciR4^b1^kY^=>z@ve5WZuU#7Jbt+qsxCSXR;P1 z-oc7sa|K7ZYqm=eq2_6&&2ev-+lkhf79eLqvAs`i$VvPUfL$8>Ag)yLlJ0#{(%YbBf2TogLsJc&CVg)^!8f^shyN(i^(=Drq1qOSy0;X7AQ zn9iGwryJtCt8!@iJjA-ae%||CyipBJf}msQfAHe)?X@{Rh+GuokB&m0VS!7K(6?!` z_ily(4fr_~jr>MRN;R=CBnpol=1Y{zcb_&}P6|^89@!AFr{lb(=V*AUzDiGSG+_$@ zNq+3M=}`7MQ<)N`eNy?evV{R+OG(=>=ddJXSJ}B9Pb*n4sKa(}9x#DHY`l07Yjtk10;lDIYW zjwC}R`Fctmv3n;lCT422r5G^U3PnS7VZ{FiFTYjXXa0=Ngnr@QW7QY*Cd&~$F@|qYahjN&M)W!_84D9?Th#9EtsAp!sn~>@&uh) zTGqv%4BbZMjNR=4YqYsR#AsgfC>K>D=Hg7g21o<@dZI3*ECkKNG`UKBMHV3}7|!w` zSV=1`w{DOAVYZ&}kej5tnQrNuABbY?r@T5{N^U;mX@F8-Z{Xgcl){9d)Jz&Ft*<6A zml>+=Fbd@#BzHD@$qz1(yGZU0F4R195{Y=#R`eI8Z1t?zxOR_Hg22O;-7FwwGOo31 zSjAd0b&Vi0ILd46bh#N^y%Z*&pJm?{G$1b4Mn3_@qMIjb;P`E&;^MiF6;aqyPhWPL z7FV$4lr?rLBH7pQ%y-# zfuChdpb9}ji-R}sBhX?WHLs#Fc#Pg)(9G8zCDv>2DlyrZ`3UML2v030y@MCql2CS! z^jDv@6w_^BT>9V#6@M~%VW|f98*I!!p8(D=`E{%T+=g8P2bpXqI{I}Xjrz-JTEB}( zfO1G5Y99$J*-Z`Vy~nVx%G})5}naiGW5mAOecBLJHkm>u2pS73@C5U*msO$_n zHBO-8Rxfr5JiZ%x|5aYsbY>D4-wd&{%=9Gw2-DfbJ$4tZjDaMjt!s2OaP_BQtQLP- zCkD)hFsSn(C(Ok2EN8nJ-G-#PO9CFZh;w9#63O)NDmq0bEr|Ht&RE{i$1#SH7fS1Lwj9QOn+38o=K zxY3cgtryAoxOnOKwbwd+d@oqFqP99|+l5M{yGCARG*rw4KFsFp!5$dLb7@gjb+GLX zGPyh5;^Amj1IE+a=xIiH3VUmFJLk%8*2aS>@eRtIN$Bxr*4G6DUuCRmF+dAH0aD$5_{R3Ozif ztx7Bl4g*vNwwf!1^p{({mYn9FFU5dSROouZsJ&V6PX6o*&W_P^=CqE$HN88nM4m!| zdt9YD8rsT|;F@yspU&(_@T{sMX4y64r`^tuzI6JjUbeN!3=4?)$!rvUNw$#qlHZ*A zdf4Yapbc1+EU^